sram.c 8.4 KB

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  1. /*
  2. *
  3. * OMAP SRAM detection and management
  4. *
  5. * Copyright (C) 2005 Nokia Corporation
  6. * Written by Tony Lindgren <tony@atomide.com>
  7. *
  8. * Copyright (C) 2009-2012 Texas Instruments
  9. * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/io.h>
  19. #include <asm/fncpy.h>
  20. #include <asm/tlb.h>
  21. #include <asm/cacheflush.h>
  22. #include <asm/mach/map.h>
  23. #include "soc.h"
  24. #include "iomap.h"
  25. #include "prm2xxx_3xxx.h"
  26. #include "sdrc.h"
  27. #include "sram.h"
  28. #define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
  29. #define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
  30. #ifdef CONFIG_OMAP4_ERRATA_I688
  31. #define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
  32. #else
  33. #define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
  34. #endif
  35. #define OMAP5_SRAM_PA 0x40300000
  36. #define SRAM_BOOTLOADER_SZ 0x00
  37. #define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
  38. #define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
  39. #define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
  40. #define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
  41. #define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
  42. #define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
  43. #define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
  44. #define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
  45. #define GP_DEVICE 0x300
  46. #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
  47. static unsigned long omap_sram_start;
  48. static unsigned long omap_sram_skip;
  49. static unsigned long omap_sram_size;
  50. /*
  51. * Depending on the target RAMFS firewall setup, the public usable amount of
  52. * SRAM varies. The default accessible size for all device types is 2k. A GP
  53. * device allows ARM11 but not other initiators for full size. This
  54. * functionality seems ok until some nice security API happens.
  55. */
  56. static int is_sram_locked(void)
  57. {
  58. if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  59. /* RAMFW: R/W access to all initiators for all qualifier sets */
  60. if (cpu_is_omap242x()) {
  61. __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  62. __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
  63. __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  64. }
  65. if (cpu_is_omap34xx()) {
  66. __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  67. __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
  68. __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  69. __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  70. __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  71. }
  72. return 0;
  73. } else
  74. return 1; /* assume locked with no PPA or security driver */
  75. }
  76. /*
  77. * The amount of SRAM depends on the core type.
  78. * Note that we cannot try to test for SRAM here because writes
  79. * to secure SRAM will hang the system. Also the SRAM is not
  80. * yet mapped at this point.
  81. */
  82. static void __init omap_detect_sram(void)
  83. {
  84. omap_sram_skip = SRAM_BOOTLOADER_SZ;
  85. if (is_sram_locked()) {
  86. if (cpu_is_omap34xx()) {
  87. omap_sram_start = OMAP3_SRAM_PUB_PA;
  88. if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
  89. (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
  90. omap_sram_size = 0x7000; /* 28K */
  91. omap_sram_skip += SZ_16K;
  92. } else {
  93. omap_sram_size = 0x8000; /* 32K */
  94. }
  95. } else if (cpu_is_omap44xx()) {
  96. omap_sram_start = OMAP4_SRAM_PUB_PA;
  97. omap_sram_size = 0xa000; /* 40K */
  98. } else if (soc_is_omap54xx()) {
  99. omap_sram_start = OMAP5_SRAM_PA;
  100. omap_sram_size = SZ_128K; /* 128KB */
  101. } else {
  102. omap_sram_start = OMAP2_SRAM_PUB_PA;
  103. omap_sram_size = 0x800; /* 2K */
  104. }
  105. } else {
  106. if (soc_is_am33xx()) {
  107. omap_sram_start = AM33XX_SRAM_PA;
  108. omap_sram_size = 0x10000; /* 64K */
  109. } else if (soc_is_am43xx()) {
  110. omap_sram_start = AM33XX_SRAM_PA;
  111. omap_sram_size = SZ_256K;
  112. } else if (cpu_is_omap34xx()) {
  113. omap_sram_start = OMAP3_SRAM_PA;
  114. omap_sram_size = 0x10000; /* 64K */
  115. } else if (cpu_is_omap44xx()) {
  116. omap_sram_start = OMAP4_SRAM_PA;
  117. omap_sram_size = 0xe000; /* 56K */
  118. } else if (soc_is_omap54xx()) {
  119. omap_sram_start = OMAP5_SRAM_PA;
  120. omap_sram_size = SZ_128K; /* 128KB */
  121. } else {
  122. omap_sram_start = OMAP2_SRAM_PA;
  123. if (cpu_is_omap242x())
  124. omap_sram_size = 0xa0000; /* 640K */
  125. else if (cpu_is_omap243x())
  126. omap_sram_size = 0x10000; /* 64K */
  127. }
  128. }
  129. }
  130. /*
  131. * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
  132. */
  133. static void __init omap2_map_sram(void)
  134. {
  135. int cached = 1;
  136. #ifdef CONFIG_OMAP4_ERRATA_I688
  137. if (cpu_is_omap44xx()) {
  138. omap_sram_start += PAGE_SIZE;
  139. omap_sram_size -= SZ_16K;
  140. }
  141. #endif
  142. if (cpu_is_omap34xx()) {
  143. /*
  144. * SRAM must be marked as non-cached on OMAP3 since the
  145. * CORE DPLL M2 divider change code (in SRAM) runs with the
  146. * SDRAM controller disabled, and if it is marked cached,
  147. * the ARM may attempt to write cache lines back to SDRAM
  148. * which will cause the system to hang.
  149. */
  150. cached = 0;
  151. }
  152. omap_map_sram(omap_sram_start, omap_sram_size,
  153. omap_sram_skip, cached);
  154. }
  155. static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
  156. u32 base_cs, u32 force_unlock);
  157. void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
  158. u32 base_cs, u32 force_unlock)
  159. {
  160. BUG_ON(!_omap2_sram_ddr_init);
  161. _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
  162. base_cs, force_unlock);
  163. }
  164. static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
  165. u32 mem_type);
  166. void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
  167. {
  168. BUG_ON(!_omap2_sram_reprogram_sdrc);
  169. _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
  170. }
  171. static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
  172. u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
  173. {
  174. BUG_ON(!_omap2_set_prcm);
  175. return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
  176. }
  177. #ifdef CONFIG_SOC_OMAP2420
  178. static int __init omap242x_sram_init(void)
  179. {
  180. _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
  181. omap242x_sram_ddr_init_sz);
  182. _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
  183. omap242x_sram_reprogram_sdrc_sz);
  184. _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
  185. omap242x_sram_set_prcm_sz);
  186. return 0;
  187. }
  188. #else
  189. static inline int omap242x_sram_init(void)
  190. {
  191. return 0;
  192. }
  193. #endif
  194. #ifdef CONFIG_SOC_OMAP2430
  195. static int __init omap243x_sram_init(void)
  196. {
  197. _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
  198. omap243x_sram_ddr_init_sz);
  199. _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
  200. omap243x_sram_reprogram_sdrc_sz);
  201. _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
  202. omap243x_sram_set_prcm_sz);
  203. return 0;
  204. }
  205. #else
  206. static inline int omap243x_sram_init(void)
  207. {
  208. return 0;
  209. }
  210. #endif
  211. #ifdef CONFIG_ARCH_OMAP3
  212. static u32 (*_omap3_sram_configure_core_dpll)(
  213. u32 m2, u32 unlock_dll, u32 f, u32 inc,
  214. u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  215. u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  216. u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  217. u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
  218. u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
  219. u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
  220. u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
  221. u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
  222. u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
  223. {
  224. BUG_ON(!_omap3_sram_configure_core_dpll);
  225. return _omap3_sram_configure_core_dpll(
  226. m2, unlock_dll, f, inc,
  227. sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
  228. sdrc_actim_ctrl_b_0, sdrc_mr_0,
  229. sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
  230. sdrc_actim_ctrl_b_1, sdrc_mr_1);
  231. }
  232. void omap3_sram_restore_context(void)
  233. {
  234. omap_sram_reset();
  235. _omap3_sram_configure_core_dpll =
  236. omap_sram_push(omap3_sram_configure_core_dpll,
  237. omap3_sram_configure_core_dpll_sz);
  238. omap_push_sram_idle();
  239. }
  240. static inline int omap34xx_sram_init(void)
  241. {
  242. omap3_sram_restore_context();
  243. return 0;
  244. }
  245. #else
  246. static inline int omap34xx_sram_init(void)
  247. {
  248. return 0;
  249. }
  250. #endif /* CONFIG_ARCH_OMAP3 */
  251. static inline int am33xx_sram_init(void)
  252. {
  253. return 0;
  254. }
  255. int __init omap_sram_init(void)
  256. {
  257. omap_detect_sram();
  258. omap2_map_sram();
  259. if (cpu_is_omap242x())
  260. omap242x_sram_init();
  261. else if (cpu_is_omap2430())
  262. omap243x_sram_init();
  263. else if (soc_is_am33xx())
  264. am33xx_sram_init();
  265. else if (cpu_is_omap34xx())
  266. omap34xx_sram_init();
  267. return 0;
  268. }