omap-smp.c 6.5 KB

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  1. /*
  2. * OMAP4 SMP source file. It contains platform specific fucntions
  3. * needed for the linux smp kernel.
  4. *
  5. * Copyright (C) 2009 Texas Instruments, Inc.
  6. *
  7. * Author:
  8. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  9. *
  10. * Platform file needed for the OMAP4 SMP. This file is based on arm
  11. * realview smp platform.
  12. * * Copyright (c) 2002 ARM Limited.
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. */
  18. #include <linux/init.h>
  19. #include <linux/device.h>
  20. #include <linux/smp.h>
  21. #include <linux/io.h>
  22. #include <linux/irqchip/arm-gic.h>
  23. #include <asm/smp_scu.h>
  24. #include "omap-secure.h"
  25. #include "omap-wakeupgen.h"
  26. #include <asm/cputype.h>
  27. #include "soc.h"
  28. #include "iomap.h"
  29. #include "common.h"
  30. #include "clockdomain.h"
  31. #include "pm.h"
  32. #define CPU_MASK 0xff0ffff0
  33. #define CPU_CORTEX_A9 0x410FC090
  34. #define CPU_CORTEX_A15 0x410FC0F0
  35. #define OMAP5_CORE_COUNT 0x2
  36. u16 pm44xx_errata;
  37. /* SCU base address */
  38. static void __iomem *scu_base;
  39. static DEFINE_SPINLOCK(boot_lock);
  40. void __iomem *omap4_get_scu_base(void)
  41. {
  42. return scu_base;
  43. }
  44. static void omap4_secondary_init(unsigned int cpu)
  45. {
  46. /*
  47. * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
  48. * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
  49. * init and for CPU1, a secure PPA API provided. CPU0 must be ON
  50. * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
  51. * OMAP443X GP devices- SMP bit isn't accessible.
  52. * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
  53. */
  54. if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
  55. omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
  56. 4, 0, 0, 0, 0, 0);
  57. /*
  58. * Synchronise with the boot thread.
  59. */
  60. spin_lock(&boot_lock);
  61. spin_unlock(&boot_lock);
  62. }
  63. static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
  64. {
  65. static struct clockdomain *cpu1_clkdm;
  66. static bool booted;
  67. static struct powerdomain *cpu1_pwrdm;
  68. void __iomem *base = omap_get_wakeupgen_base();
  69. /*
  70. * Set synchronisation state between this boot processor
  71. * and the secondary one
  72. */
  73. spin_lock(&boot_lock);
  74. /*
  75. * Update the AuxCoreBoot0 with boot state for secondary core.
  76. * omap4_secondary_startup() routine will hold the secondary core till
  77. * the AuxCoreBoot1 register is updated with cpu state
  78. * A barrier is added to ensure that write buffer is drained
  79. */
  80. if (omap_secure_apis_support())
  81. omap_modify_auxcoreboot0(0x200, 0xfffffdff);
  82. else
  83. __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
  84. if (!cpu1_clkdm && !cpu1_pwrdm) {
  85. cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
  86. cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
  87. }
  88. /*
  89. * The SGI(Software Generated Interrupts) are not wakeup capable
  90. * from low power states. This is known limitation on OMAP4 and
  91. * needs to be worked around by using software forced clockdomain
  92. * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
  93. * software force wakeup. The clockdomain is then put back to
  94. * hardware supervised mode.
  95. * More details can be found in OMAP4430 TRM - Version J
  96. * Section :
  97. * 4.3.4.2 Power States of CPU0 and CPU1
  98. */
  99. if (booted && cpu1_pwrdm && cpu1_clkdm) {
  100. /*
  101. * GIC distributor control register has changed between
  102. * CortexA9 r1pX and r2pX. The Control Register secure
  103. * banked version is now composed of 2 bits:
  104. * bit 0 == Secure Enable
  105. * bit 1 == Non-Secure Enable
  106. * The Non-Secure banked register has not changed
  107. * Because the ROM Code is based on the r1pX GIC, the CPU1
  108. * GIC restoration will cause a problem to CPU0 Non-Secure SW.
  109. * The workaround must be:
  110. * 1) Before doing the CPU1 wakeup, CPU0 must disable
  111. * the GIC distributor
  112. * 2) CPU1 must re-enable the GIC distributor on
  113. * it's wakeup path.
  114. */
  115. if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
  116. local_irq_disable();
  117. gic_dist_disable();
  118. }
  119. /*
  120. * Ensure that CPU power state is set to ON to avoid CPU
  121. * powerdomain transition on wfi
  122. */
  123. clkdm_wakeup(cpu1_clkdm);
  124. omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
  125. clkdm_allow_idle(cpu1_clkdm);
  126. if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
  127. while (gic_dist_disabled()) {
  128. udelay(1);
  129. cpu_relax();
  130. }
  131. gic_timer_retrigger();
  132. local_irq_enable();
  133. }
  134. } else {
  135. dsb_sev();
  136. booted = true;
  137. }
  138. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  139. /*
  140. * Now the secondary core is starting up let it run its
  141. * calibrations, then wait for it to finish
  142. */
  143. spin_unlock(&boot_lock);
  144. return 0;
  145. }
  146. /*
  147. * Initialise the CPU possible map early - this describes the CPUs
  148. * which may be present or become present in the system.
  149. */
  150. static void __init omap4_smp_init_cpus(void)
  151. {
  152. unsigned int i = 0, ncores = 1, cpu_id;
  153. /* Use ARM cpuid check here, as SoC detection will not work so early */
  154. cpu_id = read_cpuid_id() & CPU_MASK;
  155. if (cpu_id == CPU_CORTEX_A9) {
  156. /*
  157. * Currently we can't call ioremap here because
  158. * SoC detection won't work until after init_early.
  159. */
  160. scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
  161. BUG_ON(!scu_base);
  162. ncores = scu_get_core_count(scu_base);
  163. } else if (cpu_id == CPU_CORTEX_A15) {
  164. ncores = OMAP5_CORE_COUNT;
  165. }
  166. /* sanity check */
  167. if (ncores > nr_cpu_ids) {
  168. pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
  169. ncores, nr_cpu_ids);
  170. ncores = nr_cpu_ids;
  171. }
  172. for (i = 0; i < ncores; i++)
  173. set_cpu_possible(i, true);
  174. }
  175. static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
  176. {
  177. void *startup_addr = omap4_secondary_startup;
  178. void __iomem *base = omap_get_wakeupgen_base();
  179. /*
  180. * Initialise the SCU and wake up the secondary core using
  181. * wakeup_secondary().
  182. */
  183. if (scu_base)
  184. scu_enable(scu_base);
  185. if (cpu_is_omap446x()) {
  186. startup_addr = omap4460_secondary_startup;
  187. pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
  188. }
  189. /*
  190. * Write the address of secondary startup routine into the
  191. * AuxCoreBoot1 where ROM code will jump and start executing
  192. * on secondary core once out of WFE
  193. * A barrier is added to ensure that write buffer is drained
  194. */
  195. if (omap_secure_apis_support())
  196. omap_auxcoreboot_addr(virt_to_phys(startup_addr));
  197. else
  198. __raw_writel(virt_to_phys(omap5_secondary_startup),
  199. base + OMAP_AUX_CORE_BOOT_1);
  200. }
  201. struct smp_operations omap4_smp_ops __initdata = {
  202. .smp_init_cpus = omap4_smp_init_cpus,
  203. .smp_prepare_cpus = omap4_smp_prepare_cpus,
  204. .smp_secondary_init = omap4_secondary_init,
  205. .smp_boot_secondary = omap4_boot_secondary,
  206. #ifdef CONFIG_HOTPLUG_CPU
  207. .cpu_die = omap4_cpu_die,
  208. #endif
  209. };