io.c 16 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/io.c
  3. *
  4. * OMAP2 I/O mapping code
  5. *
  6. * Copyright (C) 2005 Nokia Corporation
  7. * Copyright (C) 2007-2009 Texas Instruments
  8. *
  9. * Author:
  10. * Juha Yrjola <juha.yrjola@nokia.com>
  11. * Syed Khasim <x0khasim@ti.com>
  12. *
  13. * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License version 2 as
  17. * published by the Free Software Foundation.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/io.h>
  23. #include <linux/clk.h>
  24. #include <asm/tlb.h>
  25. #include <asm/mach/map.h>
  26. #include <linux/omap-dma.h>
  27. #include "omap_hwmod.h"
  28. #include "soc.h"
  29. #include "iomap.h"
  30. #include "voltage.h"
  31. #include "powerdomain.h"
  32. #include "clockdomain.h"
  33. #include "common.h"
  34. #include "clock.h"
  35. #include "clock2xxx.h"
  36. #include "clock3xxx.h"
  37. #include "clock44xx.h"
  38. #include "omap-pm.h"
  39. #include "sdrc.h"
  40. #include "control.h"
  41. #include "serial.h"
  42. #include "sram.h"
  43. #include "cm2xxx.h"
  44. #include "cm3xxx.h"
  45. #include "prm.h"
  46. #include "cm.h"
  47. #include "prcm_mpu44xx.h"
  48. #include "prminst44xx.h"
  49. #include "cminst44xx.h"
  50. #include "prm2xxx.h"
  51. #include "prm3xxx.h"
  52. #include "prm44xx.h"
  53. /*
  54. * omap_clk_init: points to a function that does the SoC-specific
  55. * clock initializations
  56. */
  57. int (*omap_clk_init)(void);
  58. /*
  59. * The machine specific code may provide the extra mapping besides the
  60. * default mapping provided here.
  61. */
  62. #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
  63. static struct map_desc omap24xx_io_desc[] __initdata = {
  64. {
  65. .virtual = L3_24XX_VIRT,
  66. .pfn = __phys_to_pfn(L3_24XX_PHYS),
  67. .length = L3_24XX_SIZE,
  68. .type = MT_DEVICE
  69. },
  70. {
  71. .virtual = L4_24XX_VIRT,
  72. .pfn = __phys_to_pfn(L4_24XX_PHYS),
  73. .length = L4_24XX_SIZE,
  74. .type = MT_DEVICE
  75. },
  76. };
  77. #ifdef CONFIG_SOC_OMAP2420
  78. static struct map_desc omap242x_io_desc[] __initdata = {
  79. {
  80. .virtual = DSP_MEM_2420_VIRT,
  81. .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
  82. .length = DSP_MEM_2420_SIZE,
  83. .type = MT_DEVICE
  84. },
  85. {
  86. .virtual = DSP_IPI_2420_VIRT,
  87. .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
  88. .length = DSP_IPI_2420_SIZE,
  89. .type = MT_DEVICE
  90. },
  91. {
  92. .virtual = DSP_MMU_2420_VIRT,
  93. .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
  94. .length = DSP_MMU_2420_SIZE,
  95. .type = MT_DEVICE
  96. },
  97. };
  98. #endif
  99. #ifdef CONFIG_SOC_OMAP2430
  100. static struct map_desc omap243x_io_desc[] __initdata = {
  101. {
  102. .virtual = L4_WK_243X_VIRT,
  103. .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
  104. .length = L4_WK_243X_SIZE,
  105. .type = MT_DEVICE
  106. },
  107. {
  108. .virtual = OMAP243X_GPMC_VIRT,
  109. .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
  110. .length = OMAP243X_GPMC_SIZE,
  111. .type = MT_DEVICE
  112. },
  113. {
  114. .virtual = OMAP243X_SDRC_VIRT,
  115. .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
  116. .length = OMAP243X_SDRC_SIZE,
  117. .type = MT_DEVICE
  118. },
  119. {
  120. .virtual = OMAP243X_SMS_VIRT,
  121. .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
  122. .length = OMAP243X_SMS_SIZE,
  123. .type = MT_DEVICE
  124. },
  125. };
  126. #endif
  127. #endif
  128. #ifdef CONFIG_ARCH_OMAP3
  129. static struct map_desc omap34xx_io_desc[] __initdata = {
  130. {
  131. .virtual = L3_34XX_VIRT,
  132. .pfn = __phys_to_pfn(L3_34XX_PHYS),
  133. .length = L3_34XX_SIZE,
  134. .type = MT_DEVICE
  135. },
  136. {
  137. .virtual = L4_34XX_VIRT,
  138. .pfn = __phys_to_pfn(L4_34XX_PHYS),
  139. .length = L4_34XX_SIZE,
  140. .type = MT_DEVICE
  141. },
  142. {
  143. .virtual = OMAP34XX_GPMC_VIRT,
  144. .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
  145. .length = OMAP34XX_GPMC_SIZE,
  146. .type = MT_DEVICE
  147. },
  148. {
  149. .virtual = OMAP343X_SMS_VIRT,
  150. .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
  151. .length = OMAP343X_SMS_SIZE,
  152. .type = MT_DEVICE
  153. },
  154. {
  155. .virtual = OMAP343X_SDRC_VIRT,
  156. .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
  157. .length = OMAP343X_SDRC_SIZE,
  158. .type = MT_DEVICE
  159. },
  160. {
  161. .virtual = L4_PER_34XX_VIRT,
  162. .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
  163. .length = L4_PER_34XX_SIZE,
  164. .type = MT_DEVICE
  165. },
  166. {
  167. .virtual = L4_EMU_34XX_VIRT,
  168. .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
  169. .length = L4_EMU_34XX_SIZE,
  170. .type = MT_DEVICE
  171. },
  172. #if defined(CONFIG_DEBUG_LL) && \
  173. (defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
  174. {
  175. .virtual = ZOOM_UART_VIRT,
  176. .pfn = __phys_to_pfn(ZOOM_UART_BASE),
  177. .length = SZ_1M,
  178. .type = MT_DEVICE
  179. },
  180. #endif
  181. };
  182. #endif
  183. #ifdef CONFIG_SOC_TI81XX
  184. static struct map_desc omapti81xx_io_desc[] __initdata = {
  185. {
  186. .virtual = L4_34XX_VIRT,
  187. .pfn = __phys_to_pfn(L4_34XX_PHYS),
  188. .length = L4_34XX_SIZE,
  189. .type = MT_DEVICE
  190. }
  191. };
  192. #endif
  193. #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  194. static struct map_desc omapam33xx_io_desc[] __initdata = {
  195. {
  196. .virtual = L4_34XX_VIRT,
  197. .pfn = __phys_to_pfn(L4_34XX_PHYS),
  198. .length = L4_34XX_SIZE,
  199. .type = MT_DEVICE
  200. },
  201. {
  202. .virtual = L4_WK_AM33XX_VIRT,
  203. .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
  204. .length = L4_WK_AM33XX_SIZE,
  205. .type = MT_DEVICE
  206. }
  207. };
  208. #endif
  209. #ifdef CONFIG_ARCH_OMAP4
  210. static struct map_desc omap44xx_io_desc[] __initdata = {
  211. {
  212. .virtual = L3_44XX_VIRT,
  213. .pfn = __phys_to_pfn(L3_44XX_PHYS),
  214. .length = L3_44XX_SIZE,
  215. .type = MT_DEVICE,
  216. },
  217. {
  218. .virtual = L4_44XX_VIRT,
  219. .pfn = __phys_to_pfn(L4_44XX_PHYS),
  220. .length = L4_44XX_SIZE,
  221. .type = MT_DEVICE,
  222. },
  223. {
  224. .virtual = L4_PER_44XX_VIRT,
  225. .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
  226. .length = L4_PER_44XX_SIZE,
  227. .type = MT_DEVICE,
  228. },
  229. #ifdef CONFIG_OMAP4_ERRATA_I688
  230. {
  231. .virtual = OMAP4_SRAM_VA,
  232. .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
  233. .length = PAGE_SIZE,
  234. .type = MT_MEMORY_SO,
  235. },
  236. #endif
  237. };
  238. #endif
  239. #ifdef CONFIG_SOC_OMAP5
  240. static struct map_desc omap54xx_io_desc[] __initdata = {
  241. {
  242. .virtual = L3_54XX_VIRT,
  243. .pfn = __phys_to_pfn(L3_54XX_PHYS),
  244. .length = L3_54XX_SIZE,
  245. .type = MT_DEVICE,
  246. },
  247. {
  248. .virtual = L4_54XX_VIRT,
  249. .pfn = __phys_to_pfn(L4_54XX_PHYS),
  250. .length = L4_54XX_SIZE,
  251. .type = MT_DEVICE,
  252. },
  253. {
  254. .virtual = L4_WK_54XX_VIRT,
  255. .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
  256. .length = L4_WK_54XX_SIZE,
  257. .type = MT_DEVICE,
  258. },
  259. {
  260. .virtual = L4_PER_54XX_VIRT,
  261. .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
  262. .length = L4_PER_54XX_SIZE,
  263. .type = MT_DEVICE,
  264. },
  265. #ifdef CONFIG_OMAP4_ERRATA_I688
  266. {
  267. .virtual = OMAP4_SRAM_VA,
  268. .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
  269. .length = PAGE_SIZE,
  270. .type = MT_MEMORY_SO,
  271. },
  272. #endif
  273. };
  274. #endif
  275. #ifdef CONFIG_SOC_OMAP2420
  276. void __init omap242x_map_io(void)
  277. {
  278. iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
  279. iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
  280. }
  281. #endif
  282. #ifdef CONFIG_SOC_OMAP2430
  283. void __init omap243x_map_io(void)
  284. {
  285. iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
  286. iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
  287. }
  288. #endif
  289. #ifdef CONFIG_ARCH_OMAP3
  290. void __init omap3_map_io(void)
  291. {
  292. iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
  293. }
  294. #endif
  295. #ifdef CONFIG_SOC_TI81XX
  296. void __init ti81xx_map_io(void)
  297. {
  298. iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
  299. }
  300. #endif
  301. #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
  302. void __init am33xx_map_io(void)
  303. {
  304. iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
  305. }
  306. #endif
  307. #ifdef CONFIG_ARCH_OMAP4
  308. void __init omap4_map_io(void)
  309. {
  310. iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
  311. omap_barriers_init();
  312. }
  313. #endif
  314. #ifdef CONFIG_SOC_OMAP5
  315. void __init omap5_map_io(void)
  316. {
  317. iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
  318. omap_barriers_init();
  319. }
  320. #endif
  321. /*
  322. * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
  323. *
  324. * Sets the CORE DPLL3 M2 divider to the same value that it's at
  325. * currently. This has the effect of setting the SDRC SDRAM AC timing
  326. * registers to the values currently defined by the kernel. Currently
  327. * only defined for OMAP3; will return 0 if called on OMAP2. Returns
  328. * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
  329. * or passes along the return value of clk_set_rate().
  330. */
  331. static int __init _omap2_init_reprogram_sdrc(void)
  332. {
  333. struct clk *dpll3_m2_ck;
  334. int v = -EINVAL;
  335. long rate;
  336. if (!cpu_is_omap34xx())
  337. return 0;
  338. dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
  339. if (IS_ERR(dpll3_m2_ck))
  340. return -EINVAL;
  341. rate = clk_get_rate(dpll3_m2_ck);
  342. pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
  343. v = clk_set_rate(dpll3_m2_ck, rate);
  344. if (v)
  345. pr_err("dpll3_m2_clk rate change failed: %d\n", v);
  346. clk_put(dpll3_m2_ck);
  347. return v;
  348. }
  349. static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
  350. {
  351. return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
  352. }
  353. static void __init omap_hwmod_init_postsetup(void)
  354. {
  355. u8 postsetup_state;
  356. /* Set the default postsetup state for all hwmods */
  357. #ifdef CONFIG_PM_RUNTIME
  358. postsetup_state = _HWMOD_STATE_IDLE;
  359. #else
  360. postsetup_state = _HWMOD_STATE_ENABLED;
  361. #endif
  362. omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
  363. omap_pm_if_early_init();
  364. }
  365. static void __init __maybe_unused omap_common_late_init(void)
  366. {
  367. omap_mux_late_init();
  368. omap2_common_pm_late_init();
  369. omap_soc_device_init();
  370. }
  371. #ifdef CONFIG_SOC_OMAP2420
  372. void __init omap2420_init_early(void)
  373. {
  374. omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
  375. omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
  376. OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
  377. omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
  378. NULL);
  379. omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
  380. omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
  381. omap2xxx_check_revision();
  382. omap2xxx_prm_init();
  383. omap2xxx_cm_init();
  384. omap2xxx_voltagedomains_init();
  385. omap242x_powerdomains_init();
  386. omap242x_clockdomains_init();
  387. omap2420_hwmod_init();
  388. omap_hwmod_init_postsetup();
  389. omap_clk_init = omap2420_clk_init;
  390. }
  391. void __init omap2420_init_late(void)
  392. {
  393. omap_common_late_init();
  394. omap2_pm_init();
  395. omap2_clk_enable_autoidle_all();
  396. }
  397. #endif
  398. #ifdef CONFIG_SOC_OMAP2430
  399. void __init omap2430_init_early(void)
  400. {
  401. omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
  402. omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
  403. OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
  404. omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
  405. NULL);
  406. omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
  407. omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
  408. omap2xxx_check_revision();
  409. omap2xxx_prm_init();
  410. omap2xxx_cm_init();
  411. omap2xxx_voltagedomains_init();
  412. omap243x_powerdomains_init();
  413. omap243x_clockdomains_init();
  414. omap2430_hwmod_init();
  415. omap_hwmod_init_postsetup();
  416. omap_clk_init = omap2430_clk_init;
  417. }
  418. void __init omap2430_init_late(void)
  419. {
  420. omap_common_late_init();
  421. omap2_pm_init();
  422. omap2_clk_enable_autoidle_all();
  423. }
  424. #endif
  425. /*
  426. * Currently only board-omap3beagle.c should call this because of the
  427. * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
  428. */
  429. #ifdef CONFIG_ARCH_OMAP3
  430. void __init omap3_init_early(void)
  431. {
  432. omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
  433. omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
  434. OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
  435. omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
  436. NULL);
  437. omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
  438. omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
  439. omap3xxx_check_revision();
  440. omap3xxx_check_features();
  441. omap3xxx_prm_init();
  442. omap3xxx_cm_init();
  443. omap3xxx_voltagedomains_init();
  444. omap3xxx_powerdomains_init();
  445. omap3xxx_clockdomains_init();
  446. omap3xxx_hwmod_init();
  447. omap_hwmod_init_postsetup();
  448. omap_clk_init = omap3xxx_clk_init;
  449. }
  450. void __init omap3430_init_early(void)
  451. {
  452. omap3_init_early();
  453. }
  454. void __init omap35xx_init_early(void)
  455. {
  456. omap3_init_early();
  457. }
  458. void __init omap3630_init_early(void)
  459. {
  460. omap3_init_early();
  461. }
  462. void __init am35xx_init_early(void)
  463. {
  464. omap3_init_early();
  465. }
  466. void __init ti81xx_init_early(void)
  467. {
  468. omap2_set_globals_tap(OMAP343X_CLASS,
  469. OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
  470. omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
  471. NULL);
  472. omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
  473. omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
  474. omap3xxx_check_revision();
  475. ti81xx_check_features();
  476. omap3xxx_voltagedomains_init();
  477. omap3xxx_powerdomains_init();
  478. omap3xxx_clockdomains_init();
  479. omap3xxx_hwmod_init();
  480. omap_hwmod_init_postsetup();
  481. omap_clk_init = omap3xxx_clk_init;
  482. }
  483. void __init omap3_init_late(void)
  484. {
  485. omap_common_late_init();
  486. omap3_pm_init();
  487. omap2_clk_enable_autoidle_all();
  488. }
  489. void __init omap3430_init_late(void)
  490. {
  491. omap_common_late_init();
  492. omap3_pm_init();
  493. omap2_clk_enable_autoidle_all();
  494. }
  495. void __init omap35xx_init_late(void)
  496. {
  497. omap_common_late_init();
  498. omap3_pm_init();
  499. omap2_clk_enable_autoidle_all();
  500. }
  501. void __init omap3630_init_late(void)
  502. {
  503. omap_common_late_init();
  504. omap3_pm_init();
  505. omap2_clk_enable_autoidle_all();
  506. }
  507. void __init am35xx_init_late(void)
  508. {
  509. omap_common_late_init();
  510. omap3_pm_init();
  511. omap2_clk_enable_autoidle_all();
  512. }
  513. void __init ti81xx_init_late(void)
  514. {
  515. omap_common_late_init();
  516. omap3_pm_init();
  517. omap2_clk_enable_autoidle_all();
  518. }
  519. #endif
  520. #ifdef CONFIG_SOC_AM33XX
  521. void __init am33xx_init_early(void)
  522. {
  523. omap2_set_globals_tap(AM335X_CLASS,
  524. AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
  525. omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
  526. NULL);
  527. omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
  528. omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
  529. omap3xxx_check_revision();
  530. am33xx_check_features();
  531. am33xx_powerdomains_init();
  532. am33xx_clockdomains_init();
  533. am33xx_hwmod_init();
  534. omap_hwmod_init_postsetup();
  535. omap_clk_init = am33xx_clk_init;
  536. }
  537. #endif
  538. #ifdef CONFIG_SOC_AM43XX
  539. void __init am43xx_init_early(void)
  540. {
  541. omap2_set_globals_tap(AM335X_CLASS,
  542. AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
  543. omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
  544. NULL);
  545. omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
  546. omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
  547. omap3xxx_check_revision();
  548. }
  549. #endif
  550. #ifdef CONFIG_ARCH_OMAP4
  551. void __init omap4430_init_early(void)
  552. {
  553. omap2_set_globals_tap(OMAP443X_CLASS,
  554. OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
  555. omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
  556. OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
  557. omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
  558. omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
  559. OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
  560. omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
  561. omap_prm_base_init();
  562. omap_cm_base_init();
  563. omap4xxx_check_revision();
  564. omap4xxx_check_features();
  565. omap44xx_prm_init();
  566. omap44xx_voltagedomains_init();
  567. omap44xx_powerdomains_init();
  568. omap44xx_clockdomains_init();
  569. omap44xx_hwmod_init();
  570. omap_hwmod_init_postsetup();
  571. omap_clk_init = omap4xxx_clk_init;
  572. }
  573. void __init omap4430_init_late(void)
  574. {
  575. omap_common_late_init();
  576. omap4_pm_init();
  577. omap2_clk_enable_autoidle_all();
  578. }
  579. #endif
  580. #ifdef CONFIG_SOC_OMAP5
  581. void __init omap5_init_early(void)
  582. {
  583. omap2_set_globals_tap(OMAP54XX_CLASS,
  584. OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
  585. omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
  586. OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
  587. omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
  588. omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
  589. OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
  590. omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
  591. omap_prm_base_init();
  592. omap_cm_base_init();
  593. omap44xx_prm_init();
  594. omap5xxx_check_revision();
  595. omap54xx_voltagedomains_init();
  596. omap54xx_powerdomains_init();
  597. omap54xx_clockdomains_init();
  598. omap54xx_hwmod_init();
  599. omap_hwmod_init_postsetup();
  600. }
  601. #endif
  602. void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
  603. struct omap_sdrc_params *sdrc_cs1)
  604. {
  605. omap_sram_init();
  606. if (cpu_is_omap24xx() || omap3_has_sdrc()) {
  607. omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
  608. _omap2_init_reprogram_sdrc();
  609. }
  610. }