hsmmc.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518
  1. /*
  2. * linux/arch/arm/mach-omap2/hsmmc.c
  3. *
  4. * Copyright (C) 2007-2008 Texas Instruments
  5. * Copyright (C) 2008 Nokia Corporation
  6. * Author: Texas Instruments
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/slab.h>
  14. #include <linux/string.h>
  15. #include <linux/delay.h>
  16. #include <linux/gpio.h>
  17. #include <linux/platform_data/gpio-omap.h>
  18. #include "soc.h"
  19. #include "omap_device.h"
  20. #include "omap-pm.h"
  21. #include "mux.h"
  22. #include "mmc.h"
  23. #include "hsmmc.h"
  24. #include "control.h"
  25. #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  26. static u16 control_pbias_offset;
  27. static u16 control_devconf1_offset;
  28. #define HSMMC_NAME_LEN 9
  29. #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  30. static int hsmmc_get_context_loss(struct device *dev)
  31. {
  32. return omap_pm_get_dev_context_loss_count(dev);
  33. }
  34. #else
  35. #define hsmmc_get_context_loss NULL
  36. #endif
  37. static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
  38. int power_on, int vdd)
  39. {
  40. u32 reg, prog_io;
  41. struct omap_mmc_platform_data *mmc = dev->platform_data;
  42. if (mmc->slots[0].remux)
  43. mmc->slots[0].remux(dev, slot, power_on);
  44. /*
  45. * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
  46. * card with Vcc regulator (from twl4030 or whatever). OMAP has both
  47. * 1.8V and 3.0V modes, controlled by the PBIAS register.
  48. *
  49. * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
  50. * is most naturally TWL VSIM; those pins also use PBIAS.
  51. *
  52. * FIXME handle VMMC1A as needed ...
  53. */
  54. if (power_on) {
  55. if (cpu_is_omap2430()) {
  56. reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
  57. if ((1 << vdd) >= MMC_VDD_30_31)
  58. reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
  59. else
  60. reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
  61. omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
  62. }
  63. if (mmc->slots[0].internal_clock) {
  64. reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  65. reg |= OMAP2_MMCSDIO1ADPCLKISEL;
  66. omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
  67. }
  68. reg = omap_ctrl_readl(control_pbias_offset);
  69. if (cpu_is_omap3630()) {
  70. /* Set MMC I/O to 52Mhz */
  71. prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
  72. prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
  73. omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
  74. } else {
  75. reg |= OMAP2_PBIASSPEEDCTRL0;
  76. }
  77. reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  78. omap_ctrl_writel(reg, control_pbias_offset);
  79. } else {
  80. reg = omap_ctrl_readl(control_pbias_offset);
  81. reg &= ~OMAP2_PBIASLITEPWRDNZ0;
  82. omap_ctrl_writel(reg, control_pbias_offset);
  83. }
  84. }
  85. static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
  86. int power_on, int vdd)
  87. {
  88. u32 reg;
  89. /* 100ms delay required for PBIAS configuration */
  90. msleep(100);
  91. if (power_on) {
  92. reg = omap_ctrl_readl(control_pbias_offset);
  93. reg |= (OMAP2_PBIASLITEPWRDNZ0 | OMAP2_PBIASSPEEDCTRL0);
  94. if ((1 << vdd) <= MMC_VDD_165_195)
  95. reg &= ~OMAP2_PBIASLITEVMODE0;
  96. else
  97. reg |= OMAP2_PBIASLITEVMODE0;
  98. omap_ctrl_writel(reg, control_pbias_offset);
  99. } else {
  100. reg = omap_ctrl_readl(control_pbias_offset);
  101. reg |= (OMAP2_PBIASSPEEDCTRL0 | OMAP2_PBIASLITEPWRDNZ0 |
  102. OMAP2_PBIASLITEVMODE0);
  103. omap_ctrl_writel(reg, control_pbias_offset);
  104. }
  105. }
  106. static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
  107. {
  108. u32 reg;
  109. reg = omap_ctrl_readl(control_devconf1_offset);
  110. if (mmc->slots[0].internal_clock)
  111. reg |= OMAP2_MMCSDIO2ADPCLKISEL;
  112. else
  113. reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
  114. omap_ctrl_writel(reg, control_devconf1_offset);
  115. }
  116. static void hsmmc2_before_set_reg(struct device *dev, int slot,
  117. int power_on, int vdd)
  118. {
  119. struct omap_mmc_platform_data *mmc = dev->platform_data;
  120. if (mmc->slots[0].remux)
  121. mmc->slots[0].remux(dev, slot, power_on);
  122. if (power_on)
  123. hsmmc2_select_input_clk_src(mmc);
  124. }
  125. static int am35x_hsmmc2_set_power(struct device *dev, int slot,
  126. int power_on, int vdd)
  127. {
  128. struct omap_mmc_platform_data *mmc = dev->platform_data;
  129. if (power_on)
  130. hsmmc2_select_input_clk_src(mmc);
  131. return 0;
  132. }
  133. static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
  134. int vdd)
  135. {
  136. return 0;
  137. }
  138. static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
  139. int controller_nr)
  140. {
  141. if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
  142. (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
  143. omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
  144. OMAP_PIN_INPUT_PULLUP);
  145. if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
  146. (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
  147. omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
  148. OMAP_PIN_INPUT_PULLUP);
  149. if (cpu_is_omap34xx()) {
  150. if (controller_nr == 0) {
  151. omap_mux_init_signal("sdmmc1_clk",
  152. OMAP_PIN_INPUT_PULLUP);
  153. omap_mux_init_signal("sdmmc1_cmd",
  154. OMAP_PIN_INPUT_PULLUP);
  155. omap_mux_init_signal("sdmmc1_dat0",
  156. OMAP_PIN_INPUT_PULLUP);
  157. if (mmc_controller->slots[0].caps &
  158. (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
  159. omap_mux_init_signal("sdmmc1_dat1",
  160. OMAP_PIN_INPUT_PULLUP);
  161. omap_mux_init_signal("sdmmc1_dat2",
  162. OMAP_PIN_INPUT_PULLUP);
  163. omap_mux_init_signal("sdmmc1_dat3",
  164. OMAP_PIN_INPUT_PULLUP);
  165. }
  166. if (mmc_controller->slots[0].caps &
  167. MMC_CAP_8_BIT_DATA) {
  168. omap_mux_init_signal("sdmmc1_dat4",
  169. OMAP_PIN_INPUT_PULLUP);
  170. omap_mux_init_signal("sdmmc1_dat5",
  171. OMAP_PIN_INPUT_PULLUP);
  172. omap_mux_init_signal("sdmmc1_dat6",
  173. OMAP_PIN_INPUT_PULLUP);
  174. omap_mux_init_signal("sdmmc1_dat7",
  175. OMAP_PIN_INPUT_PULLUP);
  176. }
  177. }
  178. if (controller_nr == 1) {
  179. /* MMC2 */
  180. omap_mux_init_signal("sdmmc2_clk",
  181. OMAP_PIN_INPUT_PULLUP);
  182. omap_mux_init_signal("sdmmc2_cmd",
  183. OMAP_PIN_INPUT_PULLUP);
  184. omap_mux_init_signal("sdmmc2_dat0",
  185. OMAP_PIN_INPUT_PULLUP);
  186. /*
  187. * For 8 wire configurations, Lines DAT4, 5, 6 and 7
  188. * need to be muxed in the board-*.c files
  189. */
  190. if (mmc_controller->slots[0].caps &
  191. (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
  192. omap_mux_init_signal("sdmmc2_dat1",
  193. OMAP_PIN_INPUT_PULLUP);
  194. omap_mux_init_signal("sdmmc2_dat2",
  195. OMAP_PIN_INPUT_PULLUP);
  196. omap_mux_init_signal("sdmmc2_dat3",
  197. OMAP_PIN_INPUT_PULLUP);
  198. }
  199. if (mmc_controller->slots[0].caps &
  200. MMC_CAP_8_BIT_DATA) {
  201. omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
  202. OMAP_PIN_INPUT_PULLUP);
  203. omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
  204. OMAP_PIN_INPUT_PULLUP);
  205. omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
  206. OMAP_PIN_INPUT_PULLUP);
  207. omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
  208. OMAP_PIN_INPUT_PULLUP);
  209. }
  210. }
  211. /*
  212. * For MMC3 the pins need to be muxed in the board-*.c files
  213. */
  214. }
  215. }
  216. static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
  217. struct omap_mmc_platform_data *mmc)
  218. {
  219. char *hc_name;
  220. hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
  221. if (!hc_name) {
  222. pr_err("Cannot allocate memory for controller slot name\n");
  223. kfree(hc_name);
  224. return -ENOMEM;
  225. }
  226. if (c->name)
  227. strncpy(hc_name, c->name, HSMMC_NAME_LEN);
  228. else
  229. snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
  230. c->mmc, 1);
  231. mmc->slots[0].name = hc_name;
  232. mmc->nr_slots = 1;
  233. mmc->slots[0].caps = c->caps;
  234. mmc->slots[0].pm_caps = c->pm_caps;
  235. mmc->slots[0].internal_clock = !c->ext_clock;
  236. mmc->max_freq = c->max_freq;
  237. mmc->reg_offset = 0;
  238. mmc->get_context_loss_count = hsmmc_get_context_loss;
  239. mmc->slots[0].switch_pin = c->gpio_cd;
  240. mmc->slots[0].gpio_wp = c->gpio_wp;
  241. mmc->slots[0].remux = c->remux;
  242. mmc->slots[0].init_card = c->init_card;
  243. if (c->cover_only)
  244. mmc->slots[0].cover = 1;
  245. if (c->nonremovable)
  246. mmc->slots[0].nonremovable = 1;
  247. if (c->power_saving)
  248. mmc->slots[0].power_saving = 1;
  249. if (c->no_off)
  250. mmc->slots[0].no_off = 1;
  251. if (c->no_off_init)
  252. mmc->slots[0].no_regulator_off_init = c->no_off_init;
  253. if (c->vcc_aux_disable_is_sleep)
  254. mmc->slots[0].vcc_aux_disable_is_sleep = 1;
  255. /*
  256. * NOTE: MMC slots should have a Vcc regulator set up.
  257. * This may be from a TWL4030-family chip, another
  258. * controllable regulator, or a fixed supply.
  259. *
  260. * temporary HACK: ocr_mask instead of fixed supply
  261. */
  262. if (soc_is_am35xx())
  263. mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
  264. MMC_VDD_26_27 |
  265. MMC_VDD_27_28 |
  266. MMC_VDD_29_30 |
  267. MMC_VDD_30_31 |
  268. MMC_VDD_31_32;
  269. else
  270. mmc->slots[0].ocr_mask = c->ocr_mask;
  271. if (!soc_is_am35xx())
  272. mmc->slots[0].features |= HSMMC_HAS_PBIAS;
  273. switch (c->mmc) {
  274. case 1:
  275. if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
  276. /* on-chip level shifting via PBIAS0/PBIAS1 */
  277. mmc->slots[0].before_set_reg =
  278. omap_hsmmc1_before_set_reg;
  279. mmc->slots[0].after_set_reg =
  280. omap_hsmmc1_after_set_reg;
  281. }
  282. if (soc_is_am35xx())
  283. mmc->slots[0].set_power = nop_mmc_set_power;
  284. /* OMAP3630 HSMMC1 supports only 4-bit */
  285. if (cpu_is_omap3630() &&
  286. (c->caps & MMC_CAP_8_BIT_DATA)) {
  287. c->caps &= ~MMC_CAP_8_BIT_DATA;
  288. c->caps |= MMC_CAP_4_BIT_DATA;
  289. mmc->slots[0].caps = c->caps;
  290. }
  291. break;
  292. case 2:
  293. if (soc_is_am35xx())
  294. mmc->slots[0].set_power = am35x_hsmmc2_set_power;
  295. if (c->ext_clock)
  296. c->transceiver = 1;
  297. if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
  298. c->caps &= ~MMC_CAP_8_BIT_DATA;
  299. c->caps |= MMC_CAP_4_BIT_DATA;
  300. }
  301. if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
  302. /* off-chip level shifting, or none */
  303. mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
  304. mmc->slots[0].after_set_reg = NULL;
  305. }
  306. break;
  307. case 3:
  308. case 4:
  309. case 5:
  310. mmc->slots[0].before_set_reg = NULL;
  311. mmc->slots[0].after_set_reg = NULL;
  312. break;
  313. default:
  314. pr_err("MMC%d configuration not supported!\n", c->mmc);
  315. kfree(hc_name);
  316. return -ENODEV;
  317. }
  318. return 0;
  319. }
  320. static int omap_hsmmc_done;
  321. void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
  322. {
  323. struct platform_device *pdev;
  324. struct omap_mmc_platform_data *mmc_pdata;
  325. int res;
  326. if (omap_hsmmc_done != 1)
  327. return;
  328. omap_hsmmc_done++;
  329. for (; c->mmc; c++) {
  330. if (!c->deferred)
  331. continue;
  332. pdev = c->pdev;
  333. if (!pdev)
  334. continue;
  335. mmc_pdata = pdev->dev.platform_data;
  336. if (!mmc_pdata)
  337. continue;
  338. mmc_pdata->slots[0].switch_pin = c->gpio_cd;
  339. mmc_pdata->slots[0].gpio_wp = c->gpio_wp;
  340. res = omap_device_register(pdev);
  341. if (res)
  342. pr_err("Could not late init MMC %s\n",
  343. c->name);
  344. }
  345. }
  346. #define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
  347. static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
  348. int ctrl_nr)
  349. {
  350. struct omap_hwmod *oh;
  351. struct omap_hwmod *ohs[1];
  352. struct omap_device *od;
  353. struct platform_device *pdev;
  354. char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
  355. struct omap_mmc_platform_data *mmc_data;
  356. struct omap_mmc_dev_attr *mmc_dev_attr;
  357. char *name;
  358. int res;
  359. mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
  360. if (!mmc_data) {
  361. pr_err("Cannot allocate memory for mmc device!\n");
  362. return;
  363. }
  364. res = omap_hsmmc_pdata_init(hsmmcinfo, mmc_data);
  365. if (res < 0)
  366. goto free_mmc;
  367. omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
  368. name = "omap_hsmmc";
  369. res = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
  370. "mmc%d", ctrl_nr);
  371. WARN(res >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
  372. "String buffer overflow in MMC%d device setup\n", ctrl_nr);
  373. oh = omap_hwmod_lookup(oh_name);
  374. if (!oh) {
  375. pr_err("Could not look up %s\n", oh_name);
  376. goto free_name;
  377. }
  378. ohs[0] = oh;
  379. if (oh->dev_attr != NULL) {
  380. mmc_dev_attr = oh->dev_attr;
  381. mmc_data->controller_flags = mmc_dev_attr->flags;
  382. /*
  383. * erratum 2.1.1.128 doesn't apply if board has
  384. * a transceiver is attached
  385. */
  386. if (hsmmcinfo->transceiver)
  387. mmc_data->controller_flags &=
  388. ~OMAP_HSMMC_BROKEN_MULTIBLOCK_READ;
  389. }
  390. pdev = platform_device_alloc(name, ctrl_nr - 1);
  391. if (!pdev) {
  392. pr_err("Could not allocate pdev for %s\n", name);
  393. goto free_name;
  394. }
  395. dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
  396. od = omap_device_alloc(pdev, ohs, 1);
  397. if (IS_ERR(od)) {
  398. pr_err("Could not allocate od for %s\n", name);
  399. goto put_pdev;
  400. }
  401. res = platform_device_add_data(pdev, mmc_data,
  402. sizeof(struct omap_mmc_platform_data));
  403. if (res) {
  404. pr_err("Could not add pdata for %s\n", name);
  405. goto put_pdev;
  406. }
  407. hsmmcinfo->pdev = pdev;
  408. if (hsmmcinfo->deferred)
  409. goto free_mmc;
  410. res = omap_device_register(pdev);
  411. if (res) {
  412. pr_err("Could not register od for %s\n", name);
  413. goto free_od;
  414. }
  415. goto free_mmc;
  416. free_od:
  417. omap_device_delete(od);
  418. put_pdev:
  419. platform_device_put(pdev);
  420. free_name:
  421. kfree(mmc_data->slots[0].name);
  422. free_mmc:
  423. kfree(mmc_data);
  424. }
  425. void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
  426. {
  427. if (omap_hsmmc_done)
  428. return;
  429. omap_hsmmc_done = 1;
  430. if (cpu_is_omap2430()) {
  431. control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
  432. control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
  433. } else {
  434. control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
  435. control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
  436. }
  437. for (; controllers->mmc; controllers++)
  438. omap_hsmmc_init_one(controllers, controllers->mmc);
  439. }
  440. #endif