pm.c 19 KB

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  1. /*
  2. * linux/arch/arm/mach-omap1/pm.c
  3. *
  4. * OMAP Power Management Routines
  5. *
  6. * Original code for the SA11x0:
  7. * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
  8. *
  9. * Modified for the PXA250 by Nicolas Pitre:
  10. * Copyright (c) 2002 Monta Vista Software, Inc.
  11. *
  12. * Modified for the OMAP1510 by David Singleton:
  13. * Copyright (c) 2002 Monta Vista Software, Inc.
  14. *
  15. * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16. *
  17. * This program is free software; you can redistribute it and/or modify it
  18. * under the terms of the GNU General Public License as published by the
  19. * Free Software Foundation; either version 2 of the License, or (at your
  20. * option) any later version.
  21. *
  22. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. * You should have received a copy of the GNU General Public License along
  34. * with this program; if not, write to the Free Software Foundation, Inc.,
  35. * 675 Mass Ave, Cambridge, MA 02139, USA.
  36. */
  37. #include <linux/suspend.h>
  38. #include <linux/sched.h>
  39. #include <linux/debugfs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/sysfs.h>
  43. #include <linux/module.h>
  44. #include <linux/io.h>
  45. #include <linux/atomic.h>
  46. #include <linux/cpu.h>
  47. #include <asm/fncpy.h>
  48. #include <asm/system_misc.h>
  49. #include <asm/irq.h>
  50. #include <asm/mach/time.h>
  51. #include <asm/mach/irq.h>
  52. #include <mach/tc.h>
  53. #include <mach/mux.h>
  54. #include <linux/omap-dma.h>
  55. #include <plat/dmtimer.h>
  56. #include <mach/irqs.h>
  57. #include "iomap.h"
  58. #include "clock.h"
  59. #include "pm.h"
  60. #include "sram.h"
  61. static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  62. static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  63. static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  64. static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
  65. static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  66. static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  67. #ifdef CONFIG_OMAP_32K_TIMER
  68. static unsigned short enable_dyn_sleep = 1;
  69. static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  70. char *buf)
  71. {
  72. return sprintf(buf, "%hu\n", enable_dyn_sleep);
  73. }
  74. static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  75. const char * buf, size_t n)
  76. {
  77. unsigned short value;
  78. if (sscanf(buf, "%hu", &value) != 1 ||
  79. (value != 0 && value != 1)) {
  80. printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  81. return -EINVAL;
  82. }
  83. enable_dyn_sleep = value;
  84. return n;
  85. }
  86. static struct kobj_attribute sleep_while_idle_attr =
  87. __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
  88. #endif
  89. static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
  90. /*
  91. * Let's power down on idle, but only if we are really
  92. * idle, because once we start down the path of
  93. * going idle we continue to do idle even if we get
  94. * a clock tick interrupt . .
  95. */
  96. void omap1_pm_idle(void)
  97. {
  98. extern __u32 arm_idlect1_mask;
  99. __u32 use_idlect1 = arm_idlect1_mask;
  100. int do_sleep = 0;
  101. local_fiq_disable();
  102. #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
  103. #warning Enable 32kHz OS timer in order to allow sleep states in idle
  104. use_idlect1 = use_idlect1 & ~(1 << 9);
  105. #else
  106. while (enable_dyn_sleep) {
  107. #ifdef CONFIG_CBUS_TAHVO_USB
  108. extern int vbus_active;
  109. /* Clock requirements? */
  110. if (vbus_active)
  111. break;
  112. #endif
  113. do_sleep = 1;
  114. break;
  115. }
  116. #endif
  117. #ifdef CONFIG_OMAP_DM_TIMER
  118. use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
  119. #endif
  120. if (omap_dma_running())
  121. use_idlect1 &= ~(1 << 6);
  122. /* We should be able to remove the do_sleep variable and multiple
  123. * tests above as soon as drivers, timer and DMA code have been fixed.
  124. * Even the sleep block count should become obsolete. */
  125. if ((use_idlect1 != ~0) || !do_sleep) {
  126. __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
  127. if (cpu_is_omap15xx())
  128. use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
  129. else
  130. use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
  131. omap_writel(use_idlect1, ARM_IDLECT1);
  132. __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
  133. omap_writel(saved_idlect1, ARM_IDLECT1);
  134. local_fiq_enable();
  135. return;
  136. }
  137. omap_sram_suspend(omap_readl(ARM_IDLECT1),
  138. omap_readl(ARM_IDLECT2));
  139. local_fiq_enable();
  140. }
  141. /*
  142. * Configuration of the wakeup event is board specific. For the
  143. * moment we put it into this helper function. Later it may move
  144. * to board specific files.
  145. */
  146. static void omap_pm_wakeup_setup(void)
  147. {
  148. u32 level1_wake = 0;
  149. u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
  150. /*
  151. * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
  152. * and the L2 wakeup interrupts: keypad and UART2. Note that the
  153. * drivers must still separately call omap_set_gpio_wakeup() to
  154. * wake up to a GPIO interrupt.
  155. */
  156. if (cpu_is_omap7xx())
  157. level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
  158. OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
  159. else if (cpu_is_omap15xx())
  160. level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
  161. OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
  162. else if (cpu_is_omap16xx())
  163. level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
  164. OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
  165. omap_writel(~level1_wake, OMAP_IH1_MIR);
  166. if (cpu_is_omap7xx()) {
  167. omap_writel(~level2_wake, OMAP_IH2_0_MIR);
  168. omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
  169. OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
  170. OMAP_IH2_1_MIR);
  171. } else if (cpu_is_omap15xx()) {
  172. level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
  173. omap_writel(~level2_wake, OMAP_IH2_MIR);
  174. } else if (cpu_is_omap16xx()) {
  175. level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
  176. omap_writel(~level2_wake, OMAP_IH2_0_MIR);
  177. /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
  178. omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
  179. OMAP_IH2_1_MIR);
  180. omap_writel(~0x0, OMAP_IH2_2_MIR);
  181. omap_writel(~0x0, OMAP_IH2_3_MIR);
  182. }
  183. /* New IRQ agreement, recalculate in cascade order */
  184. omap_writel(1, OMAP_IH2_CONTROL);
  185. omap_writel(1, OMAP_IH1_CONTROL);
  186. }
  187. #define EN_DSPCK 13 /* ARM_CKCTL */
  188. #define EN_APICK 6 /* ARM_IDLECT2 */
  189. #define DSP_EN 1 /* ARM_RSTCT1 */
  190. void omap1_pm_suspend(void)
  191. {
  192. unsigned long arg0 = 0, arg1 = 0;
  193. printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
  194. omap_rev());
  195. omap_serial_wake_trigger(1);
  196. if (!cpu_is_omap15xx())
  197. omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
  198. /*
  199. * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
  200. */
  201. local_irq_disable();
  202. local_fiq_disable();
  203. /*
  204. * Step 2: save registers
  205. *
  206. * The omap is a strange/beautiful device. The caches, memory
  207. * and register state are preserved across power saves.
  208. * We have to save and restore very little register state to
  209. * idle the omap.
  210. *
  211. * Save interrupt, MPUI, ARM and UPLD control registers.
  212. */
  213. if (cpu_is_omap7xx()) {
  214. MPUI7XX_SAVE(OMAP_IH1_MIR);
  215. MPUI7XX_SAVE(OMAP_IH2_0_MIR);
  216. MPUI7XX_SAVE(OMAP_IH2_1_MIR);
  217. MPUI7XX_SAVE(MPUI_CTRL);
  218. MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
  219. MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
  220. MPUI7XX_SAVE(EMIFS_CONFIG);
  221. MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
  222. } else if (cpu_is_omap15xx()) {
  223. MPUI1510_SAVE(OMAP_IH1_MIR);
  224. MPUI1510_SAVE(OMAP_IH2_MIR);
  225. MPUI1510_SAVE(MPUI_CTRL);
  226. MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
  227. MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
  228. MPUI1510_SAVE(EMIFS_CONFIG);
  229. MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
  230. } else if (cpu_is_omap16xx()) {
  231. MPUI1610_SAVE(OMAP_IH1_MIR);
  232. MPUI1610_SAVE(OMAP_IH2_0_MIR);
  233. MPUI1610_SAVE(OMAP_IH2_1_MIR);
  234. MPUI1610_SAVE(OMAP_IH2_2_MIR);
  235. MPUI1610_SAVE(OMAP_IH2_3_MIR);
  236. MPUI1610_SAVE(MPUI_CTRL);
  237. MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
  238. MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
  239. MPUI1610_SAVE(EMIFS_CONFIG);
  240. MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
  241. }
  242. ARM_SAVE(ARM_CKCTL);
  243. ARM_SAVE(ARM_IDLECT1);
  244. ARM_SAVE(ARM_IDLECT2);
  245. if (!(cpu_is_omap15xx()))
  246. ARM_SAVE(ARM_IDLECT3);
  247. ARM_SAVE(ARM_EWUPCT);
  248. ARM_SAVE(ARM_RSTCT1);
  249. ARM_SAVE(ARM_RSTCT2);
  250. ARM_SAVE(ARM_SYSST);
  251. ULPD_SAVE(ULPD_CLOCK_CTRL);
  252. ULPD_SAVE(ULPD_STATUS_REQ);
  253. /* (Step 3 removed - we now allow deep sleep by default) */
  254. /*
  255. * Step 4: OMAP DSP Shutdown
  256. */
  257. /* stop DSP */
  258. omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
  259. /* shut down dsp_ck */
  260. if (!cpu_is_omap7xx())
  261. omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
  262. /* temporarily enabling api_ck to access DSP registers */
  263. omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
  264. /* save DSP registers */
  265. DSP_SAVE(DSP_IDLECT2);
  266. /* Stop all DSP domain clocks */
  267. __raw_writew(0, DSP_IDLECT2);
  268. /*
  269. * Step 5: Wakeup Event Setup
  270. */
  271. omap_pm_wakeup_setup();
  272. /*
  273. * Step 6: ARM and Traffic controller shutdown
  274. */
  275. /* disable ARM watchdog */
  276. omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
  277. omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
  278. /*
  279. * Step 6b: ARM and Traffic controller shutdown
  280. *
  281. * Step 6 continues here. Prepare jump to power management
  282. * assembly code in internal SRAM.
  283. *
  284. * Since the omap_cpu_suspend routine has been copied to
  285. * SRAM, we'll do an indirect procedure call to it and pass the
  286. * contents of arm_idlect1 and arm_idlect2 so it can restore
  287. * them when it wakes up and it will return.
  288. */
  289. arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
  290. arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
  291. /*
  292. * Step 6c: ARM and Traffic controller shutdown
  293. *
  294. * Jump to assembly code. The processor will stay there
  295. * until wake up.
  296. */
  297. omap_sram_suspend(arg0, arg1);
  298. /*
  299. * If we are here, processor is woken up!
  300. */
  301. /*
  302. * Restore DSP clocks
  303. */
  304. /* again temporarily enabling api_ck to access DSP registers */
  305. omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
  306. /* Restore DSP domain clocks */
  307. DSP_RESTORE(DSP_IDLECT2);
  308. /*
  309. * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
  310. */
  311. if (!(cpu_is_omap15xx()))
  312. ARM_RESTORE(ARM_IDLECT3);
  313. ARM_RESTORE(ARM_CKCTL);
  314. ARM_RESTORE(ARM_EWUPCT);
  315. ARM_RESTORE(ARM_RSTCT1);
  316. ARM_RESTORE(ARM_RSTCT2);
  317. ARM_RESTORE(ARM_SYSST);
  318. ULPD_RESTORE(ULPD_CLOCK_CTRL);
  319. ULPD_RESTORE(ULPD_STATUS_REQ);
  320. if (cpu_is_omap7xx()) {
  321. MPUI7XX_RESTORE(EMIFS_CONFIG);
  322. MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
  323. MPUI7XX_RESTORE(OMAP_IH1_MIR);
  324. MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
  325. MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
  326. } else if (cpu_is_omap15xx()) {
  327. MPUI1510_RESTORE(MPUI_CTRL);
  328. MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
  329. MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
  330. MPUI1510_RESTORE(EMIFS_CONFIG);
  331. MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
  332. MPUI1510_RESTORE(OMAP_IH1_MIR);
  333. MPUI1510_RESTORE(OMAP_IH2_MIR);
  334. } else if (cpu_is_omap16xx()) {
  335. MPUI1610_RESTORE(MPUI_CTRL);
  336. MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
  337. MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
  338. MPUI1610_RESTORE(EMIFS_CONFIG);
  339. MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
  340. MPUI1610_RESTORE(OMAP_IH1_MIR);
  341. MPUI1610_RESTORE(OMAP_IH2_0_MIR);
  342. MPUI1610_RESTORE(OMAP_IH2_1_MIR);
  343. MPUI1610_RESTORE(OMAP_IH2_2_MIR);
  344. MPUI1610_RESTORE(OMAP_IH2_3_MIR);
  345. }
  346. if (!cpu_is_omap15xx())
  347. omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
  348. /*
  349. * Re-enable interrupts
  350. */
  351. local_irq_enable();
  352. local_fiq_enable();
  353. omap_serial_wake_trigger(0);
  354. printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
  355. omap_rev());
  356. }
  357. #ifdef CONFIG_DEBUG_FS
  358. /*
  359. * Read system PM registers for debugging
  360. */
  361. static int omap_pm_debug_show(struct seq_file *m, void *v)
  362. {
  363. ARM_SAVE(ARM_CKCTL);
  364. ARM_SAVE(ARM_IDLECT1);
  365. ARM_SAVE(ARM_IDLECT2);
  366. if (!(cpu_is_omap15xx()))
  367. ARM_SAVE(ARM_IDLECT3);
  368. ARM_SAVE(ARM_EWUPCT);
  369. ARM_SAVE(ARM_RSTCT1);
  370. ARM_SAVE(ARM_RSTCT2);
  371. ARM_SAVE(ARM_SYSST);
  372. ULPD_SAVE(ULPD_IT_STATUS);
  373. ULPD_SAVE(ULPD_CLOCK_CTRL);
  374. ULPD_SAVE(ULPD_SOFT_REQ);
  375. ULPD_SAVE(ULPD_STATUS_REQ);
  376. ULPD_SAVE(ULPD_DPLL_CTRL);
  377. ULPD_SAVE(ULPD_POWER_CTRL);
  378. if (cpu_is_omap7xx()) {
  379. MPUI7XX_SAVE(MPUI_CTRL);
  380. MPUI7XX_SAVE(MPUI_DSP_STATUS);
  381. MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
  382. MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
  383. MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
  384. MPUI7XX_SAVE(EMIFS_CONFIG);
  385. } else if (cpu_is_omap15xx()) {
  386. MPUI1510_SAVE(MPUI_CTRL);
  387. MPUI1510_SAVE(MPUI_DSP_STATUS);
  388. MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
  389. MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
  390. MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
  391. MPUI1510_SAVE(EMIFS_CONFIG);
  392. } else if (cpu_is_omap16xx()) {
  393. MPUI1610_SAVE(MPUI_CTRL);
  394. MPUI1610_SAVE(MPUI_DSP_STATUS);
  395. MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
  396. MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
  397. MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
  398. MPUI1610_SAVE(EMIFS_CONFIG);
  399. }
  400. seq_printf(m,
  401. "ARM_CKCTL_REG: 0x%-8x \n"
  402. "ARM_IDLECT1_REG: 0x%-8x \n"
  403. "ARM_IDLECT2_REG: 0x%-8x \n"
  404. "ARM_IDLECT3_REG: 0x%-8x \n"
  405. "ARM_EWUPCT_REG: 0x%-8x \n"
  406. "ARM_RSTCT1_REG: 0x%-8x \n"
  407. "ARM_RSTCT2_REG: 0x%-8x \n"
  408. "ARM_SYSST_REG: 0x%-8x \n"
  409. "ULPD_IT_STATUS_REG: 0x%-4x \n"
  410. "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
  411. "ULPD_SOFT_REQ_REG: 0x%-4x \n"
  412. "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
  413. "ULPD_STATUS_REQ_REG: 0x%-4x \n"
  414. "ULPD_POWER_CTRL_REG: 0x%-4x \n",
  415. ARM_SHOW(ARM_CKCTL),
  416. ARM_SHOW(ARM_IDLECT1),
  417. ARM_SHOW(ARM_IDLECT2),
  418. ARM_SHOW(ARM_IDLECT3),
  419. ARM_SHOW(ARM_EWUPCT),
  420. ARM_SHOW(ARM_RSTCT1),
  421. ARM_SHOW(ARM_RSTCT2),
  422. ARM_SHOW(ARM_SYSST),
  423. ULPD_SHOW(ULPD_IT_STATUS),
  424. ULPD_SHOW(ULPD_CLOCK_CTRL),
  425. ULPD_SHOW(ULPD_SOFT_REQ),
  426. ULPD_SHOW(ULPD_DPLL_CTRL),
  427. ULPD_SHOW(ULPD_STATUS_REQ),
  428. ULPD_SHOW(ULPD_POWER_CTRL));
  429. if (cpu_is_omap7xx()) {
  430. seq_printf(m,
  431. "MPUI7XX_CTRL_REG 0x%-8x \n"
  432. "MPUI7XX_DSP_STATUS_REG: 0x%-8x \n"
  433. "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
  434. "MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n"
  435. "MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n"
  436. "MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n",
  437. MPUI7XX_SHOW(MPUI_CTRL),
  438. MPUI7XX_SHOW(MPUI_DSP_STATUS),
  439. MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
  440. MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
  441. MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
  442. MPUI7XX_SHOW(EMIFS_CONFIG));
  443. } else if (cpu_is_omap15xx()) {
  444. seq_printf(m,
  445. "MPUI1510_CTRL_REG 0x%-8x \n"
  446. "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
  447. "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
  448. "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
  449. "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
  450. "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
  451. MPUI1510_SHOW(MPUI_CTRL),
  452. MPUI1510_SHOW(MPUI_DSP_STATUS),
  453. MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
  454. MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
  455. MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
  456. MPUI1510_SHOW(EMIFS_CONFIG));
  457. } else if (cpu_is_omap16xx()) {
  458. seq_printf(m,
  459. "MPUI1610_CTRL_REG 0x%-8x \n"
  460. "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
  461. "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
  462. "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
  463. "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
  464. "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
  465. MPUI1610_SHOW(MPUI_CTRL),
  466. MPUI1610_SHOW(MPUI_DSP_STATUS),
  467. MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
  468. MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
  469. MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
  470. MPUI1610_SHOW(EMIFS_CONFIG));
  471. }
  472. return 0;
  473. }
  474. static int omap_pm_debug_open(struct inode *inode, struct file *file)
  475. {
  476. return single_open(file, omap_pm_debug_show,
  477. &inode->i_private);
  478. }
  479. static const struct file_operations omap_pm_debug_fops = {
  480. .open = omap_pm_debug_open,
  481. .read = seq_read,
  482. .llseek = seq_lseek,
  483. .release = single_release,
  484. };
  485. static void omap_pm_init_debugfs(void)
  486. {
  487. struct dentry *d;
  488. d = debugfs_create_dir("pm_debug", NULL);
  489. if (!d)
  490. return;
  491. (void) debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO,
  492. d, NULL, &omap_pm_debug_fops);
  493. }
  494. #endif /* CONFIG_DEBUG_FS */
  495. /*
  496. * omap_pm_prepare - Do preliminary suspend work.
  497. *
  498. */
  499. static int omap_pm_prepare(void)
  500. {
  501. /* We cannot sleep in idle until we have resumed */
  502. cpu_idle_poll_ctrl(true);
  503. return 0;
  504. }
  505. /*
  506. * omap_pm_enter - Actually enter a sleep state.
  507. * @state: State we're entering.
  508. *
  509. */
  510. static int omap_pm_enter(suspend_state_t state)
  511. {
  512. switch (state)
  513. {
  514. case PM_SUSPEND_STANDBY:
  515. case PM_SUSPEND_MEM:
  516. omap1_pm_suspend();
  517. break;
  518. default:
  519. return -EINVAL;
  520. }
  521. return 0;
  522. }
  523. /**
  524. * omap_pm_finish - Finish up suspend sequence.
  525. *
  526. * This is called after we wake back up (or if entering the sleep state
  527. * failed).
  528. */
  529. static void omap_pm_finish(void)
  530. {
  531. cpu_idle_poll_ctrl(false);
  532. }
  533. static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
  534. {
  535. return IRQ_HANDLED;
  536. }
  537. static struct irqaction omap_wakeup_irq = {
  538. .name = "peripheral wakeup",
  539. .flags = IRQF_DISABLED,
  540. .handler = omap_wakeup_interrupt
  541. };
  542. static const struct platform_suspend_ops omap_pm_ops = {
  543. .prepare = omap_pm_prepare,
  544. .enter = omap_pm_enter,
  545. .finish = omap_pm_finish,
  546. .valid = suspend_valid_only_mem,
  547. };
  548. static int __init omap_pm_init(void)
  549. {
  550. #ifdef CONFIG_OMAP_32K_TIMER
  551. int error;
  552. #endif
  553. if (!cpu_class_is_omap1())
  554. return -ENODEV;
  555. printk("Power Management for TI OMAP.\n");
  556. /*
  557. * We copy the assembler sleep/wakeup routines to SRAM.
  558. * These routines need to be in SRAM as that's the only
  559. * memory the MPU can see when it wakes up.
  560. */
  561. if (cpu_is_omap7xx()) {
  562. omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
  563. omap7xx_cpu_suspend_sz);
  564. } else if (cpu_is_omap15xx()) {
  565. omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
  566. omap1510_cpu_suspend_sz);
  567. } else if (cpu_is_omap16xx()) {
  568. omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
  569. omap1610_cpu_suspend_sz);
  570. }
  571. if (omap_sram_suspend == NULL) {
  572. printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
  573. return -ENODEV;
  574. }
  575. arm_pm_idle = omap1_pm_idle;
  576. if (cpu_is_omap7xx())
  577. setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
  578. else if (cpu_is_omap16xx())
  579. setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
  580. /* Program new power ramp-up time
  581. * (0 for most boards since we don't lower voltage when in deep sleep)
  582. */
  583. omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
  584. /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
  585. omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
  586. /* Configure IDLECT3 */
  587. if (cpu_is_omap7xx())
  588. omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
  589. else if (cpu_is_omap16xx())
  590. omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
  591. suspend_set_ops(&omap_pm_ops);
  592. #ifdef CONFIG_DEBUG_FS
  593. omap_pm_init_debugfs();
  594. #endif
  595. #ifdef CONFIG_OMAP_32K_TIMER
  596. error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
  597. if (error)
  598. printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
  599. #endif
  600. if (cpu_is_omap16xx()) {
  601. /* configure LOW_PWR pin */
  602. omap_cfg_reg(T20_1610_LOW_PWR);
  603. }
  604. return 0;
  605. }
  606. __initcall(omap_pm_init);