timer.c 8.0 KB

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  1. /*
  2. *
  3. * Copyright (C) 2007 Google, Inc.
  4. * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
  5. *
  6. * This software is licensed under the terms of the GNU General Public
  7. * License version 2, as published by the Free Software Foundation, and
  8. * may be copied, distributed, and modified under those terms.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. */
  16. #include <linux/clocksource.h>
  17. #include <linux/clockchips.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/irq.h>
  21. #include <linux/io.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/sched_clock.h>
  26. #include <asm/mach/time.h>
  27. #include <asm/localtimer.h>
  28. #include "common.h"
  29. #define TIMER_MATCH_VAL 0x0000
  30. #define TIMER_COUNT_VAL 0x0004
  31. #define TIMER_ENABLE 0x0008
  32. #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
  33. #define TIMER_ENABLE_EN BIT(0)
  34. #define TIMER_CLEAR 0x000C
  35. #define DGT_CLK_CTL 0x10
  36. #define DGT_CLK_CTL_DIV_4 0x3
  37. #define TIMER_STS_GPT0_CLR_PEND BIT(10)
  38. #define GPT_HZ 32768
  39. #define MSM_DGT_SHIFT 5
  40. static void __iomem *event_base;
  41. static void __iomem *sts_base;
  42. static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
  43. {
  44. struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
  45. /* Stop the timer tick */
  46. if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
  47. u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  48. ctrl &= ~TIMER_ENABLE_EN;
  49. writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  50. }
  51. evt->event_handler(evt);
  52. return IRQ_HANDLED;
  53. }
  54. static int msm_timer_set_next_event(unsigned long cycles,
  55. struct clock_event_device *evt)
  56. {
  57. u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  58. ctrl &= ~TIMER_ENABLE_EN;
  59. writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  60. writel_relaxed(ctrl, event_base + TIMER_CLEAR);
  61. writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
  62. if (sts_base)
  63. while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
  64. cpu_relax();
  65. writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
  66. return 0;
  67. }
  68. static void msm_timer_set_mode(enum clock_event_mode mode,
  69. struct clock_event_device *evt)
  70. {
  71. u32 ctrl;
  72. ctrl = readl_relaxed(event_base + TIMER_ENABLE);
  73. ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
  74. switch (mode) {
  75. case CLOCK_EVT_MODE_RESUME:
  76. case CLOCK_EVT_MODE_PERIODIC:
  77. break;
  78. case CLOCK_EVT_MODE_ONESHOT:
  79. /* Timer is enabled in set_next_event */
  80. break;
  81. case CLOCK_EVT_MODE_UNUSED:
  82. case CLOCK_EVT_MODE_SHUTDOWN:
  83. break;
  84. }
  85. writel_relaxed(ctrl, event_base + TIMER_ENABLE);
  86. }
  87. static struct clock_event_device msm_clockevent = {
  88. .name = "gp_timer",
  89. .features = CLOCK_EVT_FEAT_ONESHOT,
  90. .rating = 200,
  91. .set_next_event = msm_timer_set_next_event,
  92. .set_mode = msm_timer_set_mode,
  93. };
  94. static union {
  95. struct clock_event_device *evt;
  96. struct clock_event_device * __percpu *percpu_evt;
  97. } msm_evt;
  98. static void __iomem *source_base;
  99. static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
  100. {
  101. return readl_relaxed(source_base + TIMER_COUNT_VAL);
  102. }
  103. static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
  104. {
  105. /*
  106. * Shift timer count down by a constant due to unreliable lower bits
  107. * on some targets.
  108. */
  109. return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
  110. }
  111. static struct clocksource msm_clocksource = {
  112. .name = "dg_timer",
  113. .rating = 300,
  114. .read = msm_read_timer_count,
  115. .mask = CLOCKSOURCE_MASK(32),
  116. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  117. };
  118. #ifdef CONFIG_LOCAL_TIMERS
  119. static int msm_local_timer_setup(struct clock_event_device *evt)
  120. {
  121. /* Use existing clock_event for cpu 0 */
  122. if (!smp_processor_id())
  123. return 0;
  124. evt->irq = msm_clockevent.irq;
  125. evt->name = "local_timer";
  126. evt->features = msm_clockevent.features;
  127. evt->rating = msm_clockevent.rating;
  128. evt->set_mode = msm_timer_set_mode;
  129. evt->set_next_event = msm_timer_set_next_event;
  130. *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
  131. clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
  132. enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
  133. return 0;
  134. }
  135. static void msm_local_timer_stop(struct clock_event_device *evt)
  136. {
  137. evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
  138. disable_percpu_irq(evt->irq);
  139. }
  140. static struct local_timer_ops msm_local_timer_ops = {
  141. .setup = msm_local_timer_setup,
  142. .stop = msm_local_timer_stop,
  143. };
  144. #endif /* CONFIG_LOCAL_TIMERS */
  145. static notrace u32 msm_sched_clock_read(void)
  146. {
  147. return msm_clocksource.read(&msm_clocksource);
  148. }
  149. static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
  150. bool percpu)
  151. {
  152. struct clock_event_device *ce = &msm_clockevent;
  153. struct clocksource *cs = &msm_clocksource;
  154. int res;
  155. ce->cpumask = cpumask_of(0);
  156. ce->irq = irq;
  157. clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
  158. if (percpu) {
  159. msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
  160. if (!msm_evt.percpu_evt) {
  161. pr_err("memory allocation failed for %s\n", ce->name);
  162. goto err;
  163. }
  164. *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
  165. res = request_percpu_irq(ce->irq, msm_timer_interrupt,
  166. ce->name, msm_evt.percpu_evt);
  167. if (!res) {
  168. enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
  169. #ifdef CONFIG_LOCAL_TIMERS
  170. local_timer_register(&msm_local_timer_ops);
  171. #endif
  172. }
  173. } else {
  174. msm_evt.evt = ce;
  175. res = request_irq(ce->irq, msm_timer_interrupt,
  176. IRQF_TIMER | IRQF_NOBALANCING |
  177. IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
  178. }
  179. if (res)
  180. pr_err("request_irq failed for %s\n", ce->name);
  181. err:
  182. writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
  183. res = clocksource_register_hz(cs, dgt_hz);
  184. if (res)
  185. pr_err("clocksource_register failed\n");
  186. setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
  187. }
  188. #ifdef CONFIG_OF
  189. static const struct of_device_id msm_timer_match[] __initconst = {
  190. { .compatible = "qcom,kpss-timer" },
  191. { .compatible = "qcom,scss-timer" },
  192. { },
  193. };
  194. void __init msm_dt_timer_init(void)
  195. {
  196. struct device_node *np;
  197. u32 freq;
  198. int irq;
  199. struct resource res;
  200. u32 percpu_offset;
  201. void __iomem *base;
  202. void __iomem *cpu0_base;
  203. np = of_find_matching_node(NULL, msm_timer_match);
  204. if (!np) {
  205. pr_err("Can't find msm timer DT node\n");
  206. return;
  207. }
  208. base = of_iomap(np, 0);
  209. if (!base) {
  210. pr_err("Failed to map event base\n");
  211. return;
  212. }
  213. /* We use GPT0 for the clockevent */
  214. irq = irq_of_parse_and_map(np, 1);
  215. if (irq <= 0) {
  216. pr_err("Can't get irq\n");
  217. return;
  218. }
  219. /* We use CPU0's DGT for the clocksource */
  220. if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
  221. percpu_offset = 0;
  222. if (of_address_to_resource(np, 0, &res)) {
  223. pr_err("Failed to parse DGT resource\n");
  224. return;
  225. }
  226. cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
  227. if (!cpu0_base) {
  228. pr_err("Failed to map source base\n");
  229. return;
  230. }
  231. if (of_property_read_u32(np, "clock-frequency", &freq)) {
  232. pr_err("Unknown frequency\n");
  233. return;
  234. }
  235. of_node_put(np);
  236. event_base = base + 0x4;
  237. sts_base = base + 0x88;
  238. source_base = cpu0_base + 0x24;
  239. freq /= 4;
  240. writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
  241. msm_timer_init(freq, 32, irq, !!percpu_offset);
  242. }
  243. #endif
  244. static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
  245. u32 sts)
  246. {
  247. void __iomem *base;
  248. base = ioremap(addr, SZ_256);
  249. if (!base) {
  250. pr_err("Failed to map timer base\n");
  251. return -ENOMEM;
  252. }
  253. event_base = base + event;
  254. source_base = base + source;
  255. if (sts)
  256. sts_base = base + sts;
  257. return 0;
  258. }
  259. void __init msm7x01_timer_init(void)
  260. {
  261. struct clocksource *cs = &msm_clocksource;
  262. if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
  263. return;
  264. cs->read = msm_read_timer_count_shift;
  265. cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
  266. /* 600 KHz */
  267. msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
  268. false);
  269. }
  270. void __init msm7x30_timer_init(void)
  271. {
  272. if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
  273. return;
  274. msm_timer_init(24576000 / 4, 32, 1, false);
  275. }
  276. void __init qsd8x50_timer_init(void)
  277. {
  278. if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
  279. return;
  280. msm_timer_init(19200000 / 4, 32, 7, false);
  281. }