mach-imx6q.c 8.0 KB

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  1. /*
  2. * Copyright 2011-2013 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/clk-provider.h>
  14. #include <linux/clkdev.h>
  15. #include <linux/clocksource.h>
  16. #include <linux/cpu.h>
  17. #include <linux/delay.h>
  18. #include <linux/export.h>
  19. #include <linux/init.h>
  20. #include <linux/io.h>
  21. #include <linux/irq.h>
  22. #include <linux/irqchip.h>
  23. #include <linux/of.h>
  24. #include <linux/of_address.h>
  25. #include <linux/of_irq.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/opp.h>
  28. #include <linux/phy.h>
  29. #include <linux/reboot.h>
  30. #include <linux/regmap.h>
  31. #include <linux/micrel_phy.h>
  32. #include <linux/mfd/syscon.h>
  33. #include <asm/hardware/cache-l2x0.h>
  34. #include <asm/mach/arch.h>
  35. #include <asm/mach/map.h>
  36. #include <asm/system_misc.h>
  37. #include "common.h"
  38. #include "cpuidle.h"
  39. #include "hardware.h"
  40. static u32 chip_revision;
  41. int imx6q_revision(void)
  42. {
  43. return chip_revision;
  44. }
  45. static void __init imx6q_init_revision(void)
  46. {
  47. u32 rev = imx_anatop_get_digprog();
  48. switch (rev & 0xff) {
  49. case 0:
  50. chip_revision = IMX_CHIP_REVISION_1_0;
  51. break;
  52. case 1:
  53. chip_revision = IMX_CHIP_REVISION_1_1;
  54. break;
  55. case 2:
  56. chip_revision = IMX_CHIP_REVISION_1_2;
  57. break;
  58. default:
  59. chip_revision = IMX_CHIP_REVISION_UNKNOWN;
  60. }
  61. mxc_set_cpu_type(rev >> 16 & 0xff);
  62. }
  63. static void imx6q_restart(enum reboot_mode mode, const char *cmd)
  64. {
  65. struct device_node *np;
  66. void __iomem *wdog_base;
  67. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
  68. wdog_base = of_iomap(np, 0);
  69. if (!wdog_base)
  70. goto soft;
  71. imx_src_prepare_restart();
  72. /* enable wdog */
  73. writew_relaxed(1 << 2, wdog_base);
  74. /* write twice to ensure the request will not get ignored */
  75. writew_relaxed(1 << 2, wdog_base);
  76. /* wait for reset to assert ... */
  77. mdelay(500);
  78. pr_err("Watchdog reset failed to assert reset\n");
  79. /* delay to allow the serial port to show the message */
  80. mdelay(50);
  81. soft:
  82. /* we'll take a jump through zero as a poor second */
  83. soft_restart(0);
  84. }
  85. /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
  86. static int ksz9021rn_phy_fixup(struct phy_device *phydev)
  87. {
  88. if (IS_BUILTIN(CONFIG_PHYLIB)) {
  89. /* min rx data delay */
  90. phy_write(phydev, 0x0b, 0x8105);
  91. phy_write(phydev, 0x0c, 0x0000);
  92. /* max rx/tx clock delay, min rx/tx control delay */
  93. phy_write(phydev, 0x0b, 0x8104);
  94. phy_write(phydev, 0x0c, 0xf0f0);
  95. phy_write(phydev, 0x0b, 0x104);
  96. }
  97. return 0;
  98. }
  99. static void __init imx6q_sabrelite_cko1_setup(void)
  100. {
  101. struct clk *cko1_sel, *ahb, *cko1;
  102. unsigned long rate;
  103. cko1_sel = clk_get_sys(NULL, "cko1_sel");
  104. ahb = clk_get_sys(NULL, "ahb");
  105. cko1 = clk_get_sys(NULL, "cko1");
  106. if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
  107. pr_err("cko1 setup failed!\n");
  108. goto put_clk;
  109. }
  110. clk_set_parent(cko1_sel, ahb);
  111. rate = clk_round_rate(cko1, 16000000);
  112. clk_set_rate(cko1, rate);
  113. put_clk:
  114. if (!IS_ERR(cko1_sel))
  115. clk_put(cko1_sel);
  116. if (!IS_ERR(ahb))
  117. clk_put(ahb);
  118. if (!IS_ERR(cko1))
  119. clk_put(cko1);
  120. }
  121. static void __init imx6q_sabrelite_init(void)
  122. {
  123. if (IS_BUILTIN(CONFIG_PHYLIB))
  124. phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
  125. ksz9021rn_phy_fixup);
  126. imx6q_sabrelite_cko1_setup();
  127. }
  128. static void __init imx6q_sabresd_cko1_setup(void)
  129. {
  130. struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
  131. unsigned long rate;
  132. cko1_sel = clk_get_sys(NULL, "cko1_sel");
  133. pll4 = clk_get_sys(NULL, "pll4_audio");
  134. pll4_post = clk_get_sys(NULL, "pll4_post_div");
  135. cko1 = clk_get_sys(NULL, "cko1");
  136. if (IS_ERR(cko1_sel) || IS_ERR(pll4)
  137. || IS_ERR(pll4_post) || IS_ERR(cko1)) {
  138. pr_err("cko1 setup failed!\n");
  139. goto put_clk;
  140. }
  141. /*
  142. * Setting pll4 at 768MHz (24MHz * 32)
  143. * So its child clock can get 24MHz easily
  144. */
  145. clk_set_rate(pll4, 768000000);
  146. clk_set_parent(cko1_sel, pll4_post);
  147. rate = clk_round_rate(cko1, 24000000);
  148. clk_set_rate(cko1, rate);
  149. put_clk:
  150. if (!IS_ERR(cko1_sel))
  151. clk_put(cko1_sel);
  152. if (!IS_ERR(pll4_post))
  153. clk_put(pll4_post);
  154. if (!IS_ERR(pll4))
  155. clk_put(pll4);
  156. if (!IS_ERR(cko1))
  157. clk_put(cko1);
  158. }
  159. static void __init imx6q_sabresd_init(void)
  160. {
  161. imx6q_sabresd_cko1_setup();
  162. }
  163. static void __init imx6q_1588_init(void)
  164. {
  165. struct regmap *gpr;
  166. gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
  167. if (!IS_ERR(gpr))
  168. regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21);
  169. else
  170. pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
  171. }
  172. static void __init imx6q_usb_init(void)
  173. {
  174. imx_anatop_usb_chrg_detect_disable();
  175. }
  176. static void __init imx6q_init_machine(void)
  177. {
  178. if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
  179. imx6q_sabrelite_init();
  180. else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
  181. of_machine_is_compatible("fsl,imx6dl-sabresd"))
  182. imx6q_sabresd_init();
  183. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  184. imx_anatop_init();
  185. imx6q_pm_init();
  186. imx6q_usb_init();
  187. imx6q_1588_init();
  188. }
  189. #define OCOTP_CFG3 0x440
  190. #define OCOTP_CFG3_SPEED_SHIFT 16
  191. #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
  192. static void __init imx6q_opp_check_1p2ghz(struct device *cpu_dev)
  193. {
  194. struct device_node *np;
  195. void __iomem *base;
  196. u32 val;
  197. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
  198. if (!np) {
  199. pr_warn("failed to find ocotp node\n");
  200. return;
  201. }
  202. base = of_iomap(np, 0);
  203. if (!base) {
  204. pr_warn("failed to map ocotp\n");
  205. goto put_node;
  206. }
  207. val = readl_relaxed(base + OCOTP_CFG3);
  208. val >>= OCOTP_CFG3_SPEED_SHIFT;
  209. if ((val & 0x3) != OCOTP_CFG3_SPEED_1P2GHZ)
  210. if (opp_disable(cpu_dev, 1200000000))
  211. pr_warn("failed to disable 1.2 GHz OPP\n");
  212. put_node:
  213. of_node_put(np);
  214. }
  215. static void __init imx6q_opp_init(struct device *cpu_dev)
  216. {
  217. struct device_node *np;
  218. np = of_find_node_by_path("/cpus/cpu@0");
  219. if (!np) {
  220. pr_warn("failed to find cpu0 node\n");
  221. return;
  222. }
  223. cpu_dev->of_node = np;
  224. if (of_init_opp_table(cpu_dev)) {
  225. pr_warn("failed to init OPP table\n");
  226. goto put_node;
  227. }
  228. imx6q_opp_check_1p2ghz(cpu_dev);
  229. put_node:
  230. of_node_put(np);
  231. }
  232. static struct platform_device imx6q_cpufreq_pdev = {
  233. .name = "imx6q-cpufreq",
  234. };
  235. static void __init imx6q_init_late(void)
  236. {
  237. /*
  238. * WAIT mode is broken on TO 1.0 and 1.1, so there is no point
  239. * to run cpuidle on them.
  240. */
  241. if (imx6q_revision() > IMX_CHIP_REVISION_1_1)
  242. imx6q_cpuidle_init();
  243. if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
  244. imx6q_opp_init(&imx6q_cpufreq_pdev.dev);
  245. platform_device_register(&imx6q_cpufreq_pdev);
  246. }
  247. }
  248. static void __init imx6q_map_io(void)
  249. {
  250. debug_ll_io_init();
  251. imx_scu_map_io();
  252. }
  253. #ifdef CONFIG_CACHE_L2X0
  254. static void __init imx6q_init_l2cache(void)
  255. {
  256. void __iomem *l2x0_base;
  257. struct device_node *np;
  258. unsigned int val;
  259. np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
  260. if (!np)
  261. goto out;
  262. l2x0_base = of_iomap(np, 0);
  263. if (!l2x0_base) {
  264. of_node_put(np);
  265. goto out;
  266. }
  267. /* Configure the L2 PREFETCH and POWER registers */
  268. val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
  269. val |= 0x70800000;
  270. writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
  271. val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
  272. writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
  273. iounmap(l2x0_base);
  274. of_node_put(np);
  275. out:
  276. l2x0_of_init(0, ~0UL);
  277. }
  278. #else
  279. static inline void imx6q_init_l2cache(void) {}
  280. #endif
  281. static void __init imx6q_init_irq(void)
  282. {
  283. imx6q_init_revision();
  284. imx6q_init_l2cache();
  285. imx_src_init();
  286. imx_gpc_init();
  287. irqchip_init();
  288. }
  289. static void __init imx6q_timer_init(void)
  290. {
  291. of_clk_init(NULL);
  292. clocksource_of_init();
  293. imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
  294. imx6q_revision());
  295. }
  296. static const char *imx6q_dt_compat[] __initdata = {
  297. "fsl,imx6dl",
  298. "fsl,imx6q",
  299. NULL,
  300. };
  301. DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)")
  302. .smp = smp_ops(imx_smp_ops),
  303. .map_io = imx6q_map_io,
  304. .init_irq = imx6q_init_irq,
  305. .init_time = imx6q_timer_init,
  306. .init_machine = imx6q_init_machine,
  307. .init_late = imx6q_init_late,
  308. .dt_compat = imx6q_dt_compat,
  309. .restart = imx6q_restart,
  310. MACHINE_END