pm.c 8.4 KB

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  1. /*
  2. * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * EXYNOS - Power Management support
  6. *
  7. * Based on arch/arm/mach-s3c2410/pm.c
  8. * Copyright (c) 2006 Simtec Electronics
  9. * Ben Dooks <ben@simtec.co.uk>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/suspend.h>
  17. #include <linux/syscore_ops.h>
  18. #include <linux/io.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <asm/cacheflush.h>
  22. #include <asm/hardware/cache-l2x0.h>
  23. #include <asm/smp_scu.h>
  24. #include <plat/cpu.h>
  25. #include <plat/pm.h>
  26. #include <plat/pll.h>
  27. #include <plat/regs-srom.h>
  28. #include <mach/regs-irq.h>
  29. #include <mach/regs-clock.h>
  30. #include <mach/regs-pmu.h>
  31. #include <mach/pm-core.h>
  32. #include "common.h"
  33. static struct sleep_save exynos4_set_clksrc[] = {
  34. { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
  35. { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
  36. { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
  37. { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
  38. { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
  39. { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },
  40. { .reg = EXYNOS4_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
  41. { .reg = EXYNOS4_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
  42. { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, },
  43. };
  44. static struct sleep_save exynos4210_set_clksrc[] = {
  45. { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
  46. };
  47. static struct sleep_save exynos4_epll_save[] = {
  48. SAVE_ITEM(EXYNOS4_EPLL_CON0),
  49. SAVE_ITEM(EXYNOS4_EPLL_CON1),
  50. };
  51. static struct sleep_save exynos4_vpll_save[] = {
  52. SAVE_ITEM(EXYNOS4_VPLL_CON0),
  53. SAVE_ITEM(EXYNOS4_VPLL_CON1),
  54. };
  55. static struct sleep_save exynos5_sys_save[] = {
  56. SAVE_ITEM(EXYNOS5_SYS_I2C_CFG),
  57. };
  58. static struct sleep_save exynos_core_save[] = {
  59. /* SROM side */
  60. SAVE_ITEM(S5P_SROM_BW),
  61. SAVE_ITEM(S5P_SROM_BC0),
  62. SAVE_ITEM(S5P_SROM_BC1),
  63. SAVE_ITEM(S5P_SROM_BC2),
  64. SAVE_ITEM(S5P_SROM_BC3),
  65. };
  66. /* For Cortex-A9 Diagnostic and Power control register */
  67. static unsigned int save_arm_register[2];
  68. static int exynos_cpu_suspend(unsigned long arg)
  69. {
  70. #ifdef CONFIG_CACHE_L2X0
  71. outer_flush_all();
  72. #endif
  73. if (soc_is_exynos5250())
  74. flush_cache_all();
  75. /* issue the standby signal into the pm unit. */
  76. cpu_do_idle();
  77. pr_info("Failed to suspend the system\n");
  78. return 1; /* Aborting suspend */
  79. }
  80. static void exynos_pm_prepare(void)
  81. {
  82. unsigned int tmp;
  83. s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
  84. if (!soc_is_exynos5250()) {
  85. s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
  86. s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
  87. } else {
  88. s3c_pm_do_save(exynos5_sys_save, ARRAY_SIZE(exynos5_sys_save));
  89. /* Disable USE_RETENTION of JPEG_MEM_OPTION */
  90. tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
  91. tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
  92. __raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
  93. }
  94. /* Set value of power down register for sleep mode */
  95. exynos_sys_powerdown_conf(SYS_SLEEP);
  96. __raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
  97. /* ensure at least INFORM0 has the resume address */
  98. __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
  99. /* Before enter central sequence mode, clock src register have to set */
  100. if (!soc_is_exynos5250())
  101. s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
  102. if (soc_is_exynos4210())
  103. s3c_pm_do_restore_core(exynos4210_set_clksrc, ARRAY_SIZE(exynos4210_set_clksrc));
  104. }
  105. static int exynos_pm_add(struct device *dev, struct subsys_interface *sif)
  106. {
  107. pm_cpu_prep = exynos_pm_prepare;
  108. pm_cpu_sleep = exynos_cpu_suspend;
  109. return 0;
  110. }
  111. static unsigned long pll_base_rate;
  112. static void exynos4_restore_pll(void)
  113. {
  114. unsigned long pll_con, locktime, lockcnt;
  115. unsigned long pll_in_rate;
  116. unsigned int p_div, epll_wait = 0, vpll_wait = 0;
  117. if (pll_base_rate == 0)
  118. return;
  119. pll_in_rate = pll_base_rate;
  120. /* EPLL */
  121. pll_con = exynos4_epll_save[0].val;
  122. if (pll_con & (1 << 31)) {
  123. pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
  124. p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
  125. pll_in_rate /= 1000000;
  126. locktime = (3000 / pll_in_rate) * p_div;
  127. lockcnt = locktime * 10000 / (10000 / pll_in_rate);
  128. __raw_writel(lockcnt, EXYNOS4_EPLL_LOCK);
  129. s3c_pm_do_restore_core(exynos4_epll_save,
  130. ARRAY_SIZE(exynos4_epll_save));
  131. epll_wait = 1;
  132. }
  133. pll_in_rate = pll_base_rate;
  134. /* VPLL */
  135. pll_con = exynos4_vpll_save[0].val;
  136. if (pll_con & (1 << 31)) {
  137. pll_in_rate /= 1000000;
  138. /* 750us */
  139. locktime = 750;
  140. lockcnt = locktime * 10000 / (10000 / pll_in_rate);
  141. __raw_writel(lockcnt, EXYNOS4_VPLL_LOCK);
  142. s3c_pm_do_restore_core(exynos4_vpll_save,
  143. ARRAY_SIZE(exynos4_vpll_save));
  144. vpll_wait = 1;
  145. }
  146. /* Wait PLL locking */
  147. do {
  148. if (epll_wait) {
  149. pll_con = __raw_readl(EXYNOS4_EPLL_CON0);
  150. if (pll_con & (1 << EXYNOS4_EPLLCON0_LOCKED_SHIFT))
  151. epll_wait = 0;
  152. }
  153. if (vpll_wait) {
  154. pll_con = __raw_readl(EXYNOS4_VPLL_CON0);
  155. if (pll_con & (1 << EXYNOS4_VPLLCON0_LOCKED_SHIFT))
  156. vpll_wait = 0;
  157. }
  158. } while (epll_wait || vpll_wait);
  159. }
  160. static struct subsys_interface exynos_pm_interface = {
  161. .name = "exynos_pm",
  162. .subsys = &exynos_subsys,
  163. .add_dev = exynos_pm_add,
  164. };
  165. static __init int exynos_pm_drvinit(void)
  166. {
  167. struct clk *pll_base;
  168. unsigned int tmp;
  169. if (soc_is_exynos5440())
  170. return 0;
  171. s3c_pm_init();
  172. /* All wakeup disable */
  173. tmp = __raw_readl(S5P_WAKEUP_MASK);
  174. tmp |= ((0xFF << 8) | (0x1F << 1));
  175. __raw_writel(tmp, S5P_WAKEUP_MASK);
  176. if (!soc_is_exynos5250()) {
  177. pll_base = clk_get(NULL, "xtal");
  178. if (!IS_ERR(pll_base)) {
  179. pll_base_rate = clk_get_rate(pll_base);
  180. clk_put(pll_base);
  181. }
  182. }
  183. return subsys_interface_register(&exynos_pm_interface);
  184. }
  185. arch_initcall(exynos_pm_drvinit);
  186. static int exynos_pm_suspend(void)
  187. {
  188. unsigned long tmp;
  189. /* Setting Central Sequence Register for power down mode */
  190. tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
  191. tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
  192. __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
  193. /* Setting SEQ_OPTION register */
  194. tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
  195. __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
  196. if (!soc_is_exynos5250()) {
  197. /* Save Power control register */
  198. asm ("mrc p15, 0, %0, c15, c0, 0"
  199. : "=r" (tmp) : : "cc");
  200. save_arm_register[0] = tmp;
  201. /* Save Diagnostic register */
  202. asm ("mrc p15, 0, %0, c15, c0, 1"
  203. : "=r" (tmp) : : "cc");
  204. save_arm_register[1] = tmp;
  205. }
  206. return 0;
  207. }
  208. static void exynos_pm_resume(void)
  209. {
  210. unsigned long tmp;
  211. /*
  212. * If PMU failed while entering sleep mode, WFI will be
  213. * ignored by PMU and then exiting cpu_do_idle().
  214. * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
  215. * in this situation.
  216. */
  217. tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
  218. if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
  219. tmp |= S5P_CENTRAL_LOWPWR_CFG;
  220. __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
  221. /* clear the wakeup state register */
  222. __raw_writel(0x0, S5P_WAKEUP_STAT);
  223. /* No need to perform below restore code */
  224. goto early_wakeup;
  225. }
  226. if (!soc_is_exynos5250()) {
  227. /* Restore Power control register */
  228. tmp = save_arm_register[0];
  229. asm volatile ("mcr p15, 0, %0, c15, c0, 0"
  230. : : "r" (tmp)
  231. : "cc");
  232. /* Restore Diagnostic register */
  233. tmp = save_arm_register[1];
  234. asm volatile ("mcr p15, 0, %0, c15, c0, 1"
  235. : : "r" (tmp)
  236. : "cc");
  237. }
  238. /* For release retention */
  239. __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
  240. __raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
  241. __raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
  242. __raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
  243. __raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
  244. __raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
  245. __raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
  246. if (soc_is_exynos5250())
  247. s3c_pm_do_restore(exynos5_sys_save,
  248. ARRAY_SIZE(exynos5_sys_save));
  249. s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
  250. if (!soc_is_exynos5250()) {
  251. exynos4_restore_pll();
  252. #ifdef CONFIG_SMP
  253. scu_enable(S5P_VA_SCU);
  254. #endif
  255. }
  256. early_wakeup:
  257. /* Clear SLEEP mode set in INFORM1 */
  258. __raw_writel(0x0, S5P_INFORM1);
  259. return;
  260. }
  261. static struct syscore_ops exynos_pm_syscore_ops = {
  262. .suspend = exynos_pm_suspend,
  263. .resume = exynos_pm_resume,
  264. };
  265. static __init int exynos_pm_syscore_init(void)
  266. {
  267. if (soc_is_exynos5440())
  268. return 0;
  269. register_syscore_ops(&exynos_pm_syscore_ops);
  270. return 0;
  271. }
  272. arch_initcall(exynos_pm_syscore_init);