common.c 9.7 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Common Codes for EXYNOS
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/bitops.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irq.h>
  15. #include <linux/irqchip.h>
  16. #include <linux/io.h>
  17. #include <linux/device.h>
  18. #include <linux/gpio.h>
  19. #include <clocksource/samsung_pwm.h>
  20. #include <linux/sched.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/of.h>
  23. #include <linux/of_fdt.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/export.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/of_address.h>
  28. #include <linux/clocksource.h>
  29. #include <linux/clk-provider.h>
  30. #include <linux/irqchip/arm-gic.h>
  31. #include <linux/irqchip/chained_irq.h>
  32. #include <asm/proc-fns.h>
  33. #include <asm/exception.h>
  34. #include <asm/hardware/cache-l2x0.h>
  35. #include <asm/mach/map.h>
  36. #include <asm/mach/irq.h>
  37. #include <asm/cacheflush.h>
  38. #include <mach/regs-irq.h>
  39. #include <mach/regs-pmu.h>
  40. #include <plat/cpu.h>
  41. #include <plat/pm.h>
  42. #include <plat/regs-serial.h>
  43. #include "common.h"
  44. #define L2_AUX_VAL 0x7C470001
  45. #define L2_AUX_MASK 0xC200ffff
  46. static const char name_exynos4210[] = "EXYNOS4210";
  47. static const char name_exynos4212[] = "EXYNOS4212";
  48. static const char name_exynos4412[] = "EXYNOS4412";
  49. static const char name_exynos5250[] = "EXYNOS5250";
  50. static const char name_exynos5420[] = "EXYNOS5420";
  51. static const char name_exynos5440[] = "EXYNOS5440";
  52. static void exynos4_map_io(void);
  53. static void exynos5_map_io(void);
  54. static int exynos_init(void);
  55. static struct cpu_table cpu_ids[] __initdata = {
  56. {
  57. .idcode = EXYNOS4210_CPU_ID,
  58. .idmask = EXYNOS4_CPU_MASK,
  59. .map_io = exynos4_map_io,
  60. .init = exynos_init,
  61. .name = name_exynos4210,
  62. }, {
  63. .idcode = EXYNOS4212_CPU_ID,
  64. .idmask = EXYNOS4_CPU_MASK,
  65. .map_io = exynos4_map_io,
  66. .init = exynos_init,
  67. .name = name_exynos4212,
  68. }, {
  69. .idcode = EXYNOS4412_CPU_ID,
  70. .idmask = EXYNOS4_CPU_MASK,
  71. .map_io = exynos4_map_io,
  72. .init = exynos_init,
  73. .name = name_exynos4412,
  74. }, {
  75. .idcode = EXYNOS5250_SOC_ID,
  76. .idmask = EXYNOS5_SOC_MASK,
  77. .map_io = exynos5_map_io,
  78. .init = exynos_init,
  79. .name = name_exynos5250,
  80. }, {
  81. .idcode = EXYNOS5420_SOC_ID,
  82. .idmask = EXYNOS5_SOC_MASK,
  83. .map_io = exynos5_map_io,
  84. .init = exynos_init,
  85. .name = name_exynos5420,
  86. }, {
  87. .idcode = EXYNOS5440_SOC_ID,
  88. .idmask = EXYNOS5_SOC_MASK,
  89. .init = exynos_init,
  90. .name = name_exynos5440,
  91. },
  92. };
  93. /* Initial IO mappings */
  94. static struct map_desc exynos4_iodesc[] __initdata = {
  95. {
  96. .virtual = (unsigned long)S3C_VA_SYS,
  97. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  98. .length = SZ_64K,
  99. .type = MT_DEVICE,
  100. }, {
  101. .virtual = (unsigned long)S3C_VA_TIMER,
  102. .pfn = __phys_to_pfn(EXYNOS4_PA_TIMER),
  103. .length = SZ_16K,
  104. .type = MT_DEVICE,
  105. }, {
  106. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  107. .pfn = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  108. .length = SZ_4K,
  109. .type = MT_DEVICE,
  110. }, {
  111. .virtual = (unsigned long)S5P_VA_SROMC,
  112. .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
  113. .length = SZ_4K,
  114. .type = MT_DEVICE,
  115. }, {
  116. .virtual = (unsigned long)S5P_VA_SYSTIMER,
  117. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  118. .length = SZ_4K,
  119. .type = MT_DEVICE,
  120. }, {
  121. .virtual = (unsigned long)S5P_VA_PMU,
  122. .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
  123. .length = SZ_64K,
  124. .type = MT_DEVICE,
  125. }, {
  126. .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
  127. .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  128. .length = SZ_4K,
  129. .type = MT_DEVICE,
  130. }, {
  131. .virtual = (unsigned long)S5P_VA_GIC_CPU,
  132. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  133. .length = SZ_64K,
  134. .type = MT_DEVICE,
  135. }, {
  136. .virtual = (unsigned long)S5P_VA_GIC_DIST,
  137. .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  138. .length = SZ_64K,
  139. .type = MT_DEVICE,
  140. }, {
  141. .virtual = (unsigned long)S5P_VA_CMU,
  142. .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
  143. .length = SZ_128K,
  144. .type = MT_DEVICE,
  145. }, {
  146. .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
  147. .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  148. .length = SZ_8K,
  149. .type = MT_DEVICE,
  150. }, {
  151. .virtual = (unsigned long)S5P_VA_L2CC,
  152. .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
  153. .length = SZ_4K,
  154. .type = MT_DEVICE,
  155. }, {
  156. .virtual = (unsigned long)S5P_VA_DMC0,
  157. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
  158. .length = SZ_64K,
  159. .type = MT_DEVICE,
  160. }, {
  161. .virtual = (unsigned long)S5P_VA_DMC1,
  162. .pfn = __phys_to_pfn(EXYNOS4_PA_DMC1),
  163. .length = SZ_64K,
  164. .type = MT_DEVICE,
  165. }, {
  166. .virtual = (unsigned long)S3C_VA_USB_HSPHY,
  167. .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
  168. .length = SZ_4K,
  169. .type = MT_DEVICE,
  170. },
  171. };
  172. static struct map_desc exynos4_iodesc0[] __initdata = {
  173. {
  174. .virtual = (unsigned long)S5P_VA_SYSRAM,
  175. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
  176. .length = SZ_4K,
  177. .type = MT_DEVICE,
  178. },
  179. };
  180. static struct map_desc exynos4_iodesc1[] __initdata = {
  181. {
  182. .virtual = (unsigned long)S5P_VA_SYSRAM,
  183. .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
  184. .length = SZ_4K,
  185. .type = MT_DEVICE,
  186. },
  187. };
  188. static struct map_desc exynos4210_iodesc[] __initdata = {
  189. {
  190. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  191. .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
  192. .length = SZ_4K,
  193. .type = MT_DEVICE,
  194. },
  195. };
  196. static struct map_desc exynos4x12_iodesc[] __initdata = {
  197. {
  198. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  199. .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
  200. .length = SZ_4K,
  201. .type = MT_DEVICE,
  202. },
  203. };
  204. static struct map_desc exynos5250_iodesc[] __initdata = {
  205. {
  206. .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
  207. .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
  208. .length = SZ_4K,
  209. .type = MT_DEVICE,
  210. },
  211. };
  212. static struct map_desc exynos5_iodesc[] __initdata = {
  213. {
  214. .virtual = (unsigned long)S3C_VA_SYS,
  215. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
  216. .length = SZ_64K,
  217. .type = MT_DEVICE,
  218. }, {
  219. .virtual = (unsigned long)S3C_VA_TIMER,
  220. .pfn = __phys_to_pfn(EXYNOS5_PA_TIMER),
  221. .length = SZ_16K,
  222. .type = MT_DEVICE,
  223. }, {
  224. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  225. .pfn = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
  226. .length = SZ_4K,
  227. .type = MT_DEVICE,
  228. }, {
  229. .virtual = (unsigned long)S5P_VA_SROMC,
  230. .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
  231. .length = SZ_4K,
  232. .type = MT_DEVICE,
  233. }, {
  234. .virtual = (unsigned long)S5P_VA_SYSRAM,
  235. .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
  236. .length = SZ_4K,
  237. .type = MT_DEVICE,
  238. }, {
  239. .virtual = (unsigned long)S5P_VA_CMU,
  240. .pfn = __phys_to_pfn(EXYNOS5_PA_CMU),
  241. .length = 144 * SZ_1K,
  242. .type = MT_DEVICE,
  243. }, {
  244. .virtual = (unsigned long)S5P_VA_PMU,
  245. .pfn = __phys_to_pfn(EXYNOS5_PA_PMU),
  246. .length = SZ_64K,
  247. .type = MT_DEVICE,
  248. },
  249. };
  250. void exynos4_restart(enum reboot_mode mode, const char *cmd)
  251. {
  252. __raw_writel(0x1, S5P_SWRESET);
  253. }
  254. void exynos5_restart(enum reboot_mode mode, const char *cmd)
  255. {
  256. struct device_node *np;
  257. u32 val;
  258. void __iomem *addr;
  259. val = 0x1;
  260. addr = EXYNOS_SWRESET;
  261. if (of_machine_is_compatible("samsung,exynos5440")) {
  262. u32 status;
  263. np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
  264. addr = of_iomap(np, 0) + 0xbc;
  265. status = __raw_readl(addr);
  266. addr = of_iomap(np, 0) + 0xcc;
  267. val = __raw_readl(addr);
  268. val = (val & 0xffff0000) | (status & 0xffff);
  269. }
  270. __raw_writel(val, addr);
  271. }
  272. void __init exynos_init_late(void)
  273. {
  274. if (of_machine_is_compatible("samsung,exynos5440"))
  275. /* to be supported later */
  276. return;
  277. exynos_pm_late_initcall();
  278. }
  279. static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  280. int depth, void *data)
  281. {
  282. struct map_desc iodesc;
  283. __be32 *reg;
  284. unsigned long len;
  285. if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
  286. !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
  287. return 0;
  288. reg = of_get_flat_dt_prop(node, "reg", &len);
  289. if (reg == NULL || len != (sizeof(unsigned long) * 2))
  290. return 0;
  291. iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
  292. iodesc.length = be32_to_cpu(reg[1]) - 1;
  293. iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
  294. iodesc.type = MT_DEVICE;
  295. iotable_init(&iodesc, 1);
  296. return 1;
  297. }
  298. /*
  299. * exynos_map_io
  300. *
  301. * register the standard cpu IO areas
  302. */
  303. void __init exynos_init_io(void)
  304. {
  305. debug_ll_io_init();
  306. of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
  307. /* detect cpu id and rev. */
  308. s5p_init_cpu(S5P_VA_CHIPID);
  309. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  310. }
  311. static void __init exynos4_map_io(void)
  312. {
  313. iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
  314. if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
  315. iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
  316. else
  317. iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
  318. if (soc_is_exynos4210())
  319. iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
  320. if (soc_is_exynos4212() || soc_is_exynos4412())
  321. iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
  322. }
  323. static void __init exynos5_map_io(void)
  324. {
  325. iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
  326. if (soc_is_exynos5250())
  327. iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
  328. }
  329. void __init exynos_init_time(void)
  330. {
  331. of_clk_init(NULL);
  332. clocksource_of_init();
  333. }
  334. struct bus_type exynos_subsys = {
  335. .name = "exynos-core",
  336. .dev_name = "exynos-core",
  337. };
  338. static struct device exynos4_dev = {
  339. .bus = &exynos_subsys,
  340. };
  341. static int __init exynos_core_init(void)
  342. {
  343. return subsys_system_register(&exynos_subsys, NULL);
  344. }
  345. core_initcall(exynos_core_init);
  346. static int __init exynos4_l2x0_cache_init(void)
  347. {
  348. int ret;
  349. ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
  350. if (ret)
  351. return ret;
  352. l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
  353. clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
  354. return 0;
  355. }
  356. early_initcall(exynos4_l2x0_cache_init);
  357. static int __init exynos_init(void)
  358. {
  359. printk(KERN_INFO "EXYNOS: Initializing architecture\n");
  360. return device_register(&exynos4_dev);
  361. }