common.c 9.2 KB

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  1. /*
  2. * linux/arch/arm/mach-clps711x/core.c
  3. *
  4. * Core support for the CLPS711x-based machines.
  5. *
  6. * Copyright (C) 2001,2011 Deep Blue Solutions Ltd
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/io.h>
  23. #include <linux/init.h>
  24. #include <linux/sizes.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/irq.h>
  27. #include <linux/clk.h>
  28. #include <linux/clkdev.h>
  29. #include <linux/clockchips.h>
  30. #include <linux/clocksource.h>
  31. #include <linux/clk-provider.h>
  32. #include <asm/exception.h>
  33. #include <asm/mach/irq.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/mach/time.h>
  36. #include <asm/sched_clock.h>
  37. #include <asm/system_misc.h>
  38. #include <mach/hardware.h>
  39. static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh,
  40. *clk_tint, *clk_spi;
  41. /*
  42. * This maps the generic CLPS711x registers
  43. */
  44. static struct map_desc clps711x_io_desc[] __initdata = {
  45. {
  46. .virtual = (unsigned long)CLPS711X_VIRT_BASE,
  47. .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE),
  48. .length = SZ_64K,
  49. .type = MT_DEVICE
  50. }
  51. };
  52. void __init clps711x_map_io(void)
  53. {
  54. iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
  55. }
  56. static void int1_mask(struct irq_data *d)
  57. {
  58. u32 intmr1;
  59. intmr1 = clps_readl(INTMR1);
  60. intmr1 &= ~(1 << d->irq);
  61. clps_writel(intmr1, INTMR1);
  62. }
  63. static void int1_eoi(struct irq_data *d)
  64. {
  65. switch (d->irq) {
  66. case IRQ_CSINT: clps_writel(0, COEOI); break;
  67. case IRQ_TC1OI: clps_writel(0, TC1EOI); break;
  68. case IRQ_TC2OI: clps_writel(0, TC2EOI); break;
  69. case IRQ_RTCMI: clps_writel(0, RTCEOI); break;
  70. case IRQ_TINT: clps_writel(0, TEOI); break;
  71. case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
  72. }
  73. }
  74. static void int1_unmask(struct irq_data *d)
  75. {
  76. u32 intmr1;
  77. intmr1 = clps_readl(INTMR1);
  78. intmr1 |= 1 << d->irq;
  79. clps_writel(intmr1, INTMR1);
  80. }
  81. static struct irq_chip int1_chip = {
  82. .name = "Interrupt Vector 1",
  83. .irq_eoi = int1_eoi,
  84. .irq_mask = int1_mask,
  85. .irq_unmask = int1_unmask,
  86. };
  87. static void int2_mask(struct irq_data *d)
  88. {
  89. u32 intmr2;
  90. intmr2 = clps_readl(INTMR2);
  91. intmr2 &= ~(1 << (d->irq - 16));
  92. clps_writel(intmr2, INTMR2);
  93. }
  94. static void int2_eoi(struct irq_data *d)
  95. {
  96. switch (d->irq) {
  97. case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
  98. }
  99. }
  100. static void int2_unmask(struct irq_data *d)
  101. {
  102. u32 intmr2;
  103. intmr2 = clps_readl(INTMR2);
  104. intmr2 |= 1 << (d->irq - 16);
  105. clps_writel(intmr2, INTMR2);
  106. }
  107. static struct irq_chip int2_chip = {
  108. .name = "Interrupt Vector 2",
  109. .irq_eoi = int2_eoi,
  110. .irq_mask = int2_mask,
  111. .irq_unmask = int2_unmask,
  112. };
  113. static void int3_mask(struct irq_data *d)
  114. {
  115. u32 intmr3;
  116. intmr3 = clps_readl(INTMR3);
  117. intmr3 &= ~(1 << (d->irq - 32));
  118. clps_writel(intmr3, INTMR3);
  119. }
  120. static void int3_unmask(struct irq_data *d)
  121. {
  122. u32 intmr3;
  123. intmr3 = clps_readl(INTMR3);
  124. intmr3 |= 1 << (d->irq - 32);
  125. clps_writel(intmr3, INTMR3);
  126. }
  127. static struct irq_chip int3_chip = {
  128. .name = "Interrupt Vector 3",
  129. .irq_mask = int3_mask,
  130. .irq_unmask = int3_unmask,
  131. };
  132. static struct {
  133. int nr;
  134. struct irq_chip *chip;
  135. irq_flow_handler_t handle;
  136. } clps711x_irqdescs[] __initdata = {
  137. { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, },
  138. { IRQ_EINT1, &int1_chip, handle_level_irq, },
  139. { IRQ_EINT2, &int1_chip, handle_level_irq, },
  140. { IRQ_EINT3, &int1_chip, handle_level_irq, },
  141. { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, },
  142. { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, },
  143. { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, },
  144. { IRQ_TINT, &int1_chip, handle_fasteoi_irq, },
  145. { IRQ_UTXINT1, &int1_chip, handle_level_irq, },
  146. { IRQ_URXINT1, &int1_chip, handle_level_irq, },
  147. { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, },
  148. { IRQ_SSEOTI, &int1_chip, handle_level_irq, },
  149. { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, },
  150. { IRQ_SS2RX, &int2_chip, handle_level_irq, },
  151. { IRQ_SS2TX, &int2_chip, handle_level_irq, },
  152. { IRQ_UTXINT2, &int2_chip, handle_level_irq, },
  153. { IRQ_URXINT2, &int2_chip, handle_level_irq, },
  154. };
  155. void __init clps711x_init_irq(void)
  156. {
  157. unsigned int i;
  158. /* Disable interrupts */
  159. clps_writel(0, INTMR1);
  160. clps_writel(0, INTMR2);
  161. clps_writel(0, INTMR3);
  162. /* Clear down any pending interrupts */
  163. clps_writel(0, BLEOI);
  164. clps_writel(0, MCEOI);
  165. clps_writel(0, COEOI);
  166. clps_writel(0, TC1EOI);
  167. clps_writel(0, TC2EOI);
  168. clps_writel(0, RTCEOI);
  169. clps_writel(0, TEOI);
  170. clps_writel(0, UMSEOI);
  171. clps_writel(0, KBDEOI);
  172. clps_writel(0, SRXEOF);
  173. clps_writel(0xffffffff, DAISR);
  174. for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) {
  175. irq_set_chip_and_handler(clps711x_irqdescs[i].nr,
  176. clps711x_irqdescs[i].chip,
  177. clps711x_irqdescs[i].handle);
  178. set_irq_flags(clps711x_irqdescs[i].nr,
  179. IRQF_VALID | IRQF_PROBE);
  180. }
  181. if (IS_ENABLED(CONFIG_FIQ)) {
  182. init_FIQ(0);
  183. irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip,
  184. handle_bad_irq);
  185. set_irq_flags(IRQ_DAIINT,
  186. IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
  187. }
  188. }
  189. static inline u32 fls16(u32 x)
  190. {
  191. u32 r = 15;
  192. if (!(x & 0xff00)) {
  193. x <<= 8;
  194. r -= 8;
  195. }
  196. if (!(x & 0xf000)) {
  197. x <<= 4;
  198. r -= 4;
  199. }
  200. if (!(x & 0xc000)) {
  201. x <<= 2;
  202. r -= 2;
  203. }
  204. if (!(x & 0x8000))
  205. r--;
  206. return r;
  207. }
  208. asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
  209. {
  210. do {
  211. u32 irqstat;
  212. void __iomem *base = CLPS711X_VIRT_BASE;
  213. irqstat = readw_relaxed(base + INTSR1) &
  214. readw_relaxed(base + INTMR1);
  215. if (irqstat)
  216. handle_IRQ(fls16(irqstat), regs);
  217. irqstat = readw_relaxed(base + INTSR2) &
  218. readw_relaxed(base + INTMR2);
  219. if (irqstat) {
  220. handle_IRQ(fls16(irqstat) + 16, regs);
  221. continue;
  222. }
  223. break;
  224. } while (1);
  225. }
  226. static u32 notrace clps711x_sched_clock_read(void)
  227. {
  228. return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
  229. }
  230. static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
  231. struct clock_event_device *evt)
  232. {
  233. disable_irq(IRQ_TC2OI);
  234. switch (mode) {
  235. case CLOCK_EVT_MODE_PERIODIC:
  236. enable_irq(IRQ_TC2OI);
  237. break;
  238. case CLOCK_EVT_MODE_ONESHOT:
  239. /* Not supported */
  240. case CLOCK_EVT_MODE_SHUTDOWN:
  241. case CLOCK_EVT_MODE_UNUSED:
  242. case CLOCK_EVT_MODE_RESUME:
  243. /* Left event sources disabled, no more interrupts appear */
  244. break;
  245. }
  246. }
  247. static struct clock_event_device clockevent_clps711x = {
  248. .name = "clps711x-clockevent",
  249. .rating = 300,
  250. .features = CLOCK_EVT_FEAT_PERIODIC,
  251. .set_mode = clps711x_clockevent_set_mode,
  252. };
  253. static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
  254. {
  255. clockevent_clps711x.event_handler(&clockevent_clps711x);
  256. return IRQ_HANDLED;
  257. }
  258. static struct irqaction clps711x_timer_irq = {
  259. .name = "clps711x-timer",
  260. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  261. .handler = clps711x_timer_interrupt,
  262. };
  263. static void add_fixed_clk(struct clk *clk, const char *name, int rate)
  264. {
  265. clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
  266. clk_register_clkdev(clk, name, NULL);
  267. }
  268. void __init clps711x_timer_init(void)
  269. {
  270. int osc, ext, pll, cpu, bus, timl, timh, uart, spi;
  271. u32 tmp;
  272. osc = 3686400;
  273. ext = 13000000;
  274. tmp = clps_readl(PLLR) >> 24;
  275. if (tmp)
  276. pll = (osc * tmp) / 2;
  277. else
  278. pll = 73728000; /* Default value */
  279. tmp = clps_readl(SYSFLG2);
  280. if (tmp & SYSFLG2_CKMODE) {
  281. cpu = ext;
  282. bus = cpu;
  283. spi = 135400;
  284. pll = 0;
  285. } else {
  286. cpu = pll;
  287. if (cpu >= 36864000)
  288. bus = cpu / 2;
  289. else
  290. bus = 36864000 / 2;
  291. spi = cpu / 576;
  292. }
  293. uart = bus / 10;
  294. if (tmp & SYSFLG2_CKMODE) {
  295. tmp = clps_readl(SYSCON2);
  296. if (tmp & SYSCON2_OSTB)
  297. timh = ext / 26;
  298. else
  299. timh = 541440;
  300. } else
  301. timh = DIV_ROUND_CLOSEST(cpu, 144);
  302. timl = DIV_ROUND_CLOSEST(timh, 256);
  303. /* All clocks are fixed */
  304. add_fixed_clk(clk_pll, "pll", pll);
  305. add_fixed_clk(clk_bus, "bus", bus);
  306. add_fixed_clk(clk_uart, "uart", uart);
  307. add_fixed_clk(clk_timerl, "timer_lf", timl);
  308. add_fixed_clk(clk_timerh, "timer_hf", timh);
  309. add_fixed_clk(clk_tint, "tint", 64);
  310. add_fixed_clk(clk_spi, "spi", spi);
  311. pr_info("CPU frequency set at %i Hz.\n", cpu);
  312. /* Start Timer1 in free running mode (Low frequency) */
  313. tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
  314. clps_writel(tmp, SYSCON1);
  315. setup_sched_clock(clps711x_sched_clock_read, 16, timl);
  316. clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
  317. "clps711x_clocksource", timl, 300, 16,
  318. clocksource_mmio_readw_down);
  319. /* Set Timer2 prescaler */
  320. clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
  321. /* Start Timer2 in prescale mode (High frequency)*/
  322. tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
  323. clps_writel(tmp, SYSCON1);
  324. clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
  325. setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
  326. }
  327. void clps711x_restart(enum reboot_mode mode, const char *cmd)
  328. {
  329. soft_restart(0);
  330. }
  331. static void clps711x_idle(void)
  332. {
  333. clps_writel(1, HALT);
  334. asm("mov r0, r0");
  335. asm("mov r0, r0");
  336. }
  337. void __init clps711x_init_early(void)
  338. {
  339. arm_pm_idle = clps711x_idle;
  340. }