setup.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521
  1. /*
  2. * Copyright (C) 2007 Atmel Corporation.
  3. * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  4. *
  5. * Under GPLv2
  6. */
  7. #include <linux/module.h>
  8. #include <linux/io.h>
  9. #include <linux/mm.h>
  10. #include <linux/pm.h>
  11. #include <linux/of_address.h>
  12. #include <linux/pinctrl/machine.h>
  13. #include <asm/system_misc.h>
  14. #include <asm/mach/map.h>
  15. #include <mach/hardware.h>
  16. #include <mach/cpu.h>
  17. #include <mach/at91_dbgu.h>
  18. #include <mach/at91_pmc.h>
  19. #include "at91_shdwc.h"
  20. #include "soc.h"
  21. #include "generic.h"
  22. struct at91_init_soc __initdata at91_boot_soc;
  23. struct at91_socinfo at91_soc_initdata;
  24. EXPORT_SYMBOL(at91_soc_initdata);
  25. void __init at91rm9200_set_type(int type)
  26. {
  27. if (type == ARCH_REVISON_9200_PQFP)
  28. at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  29. else
  30. at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  31. pr_info("AT91: filled in soc subtype: %s\n",
  32. at91_get_soc_subtype(&at91_soc_initdata));
  33. }
  34. void __init at91_init_irq_default(void)
  35. {
  36. at91_init_interrupts(at91_boot_soc.default_irq_priority);
  37. }
  38. void __init at91_init_interrupts(unsigned int *priority)
  39. {
  40. /* Initialize the AIC interrupt controller */
  41. at91_aic_init(priority, at91_boot_soc.extern_irq);
  42. /* Enable GPIO interrupts */
  43. at91_gpio_irq_setup();
  44. }
  45. void __iomem *at91_ramc_base[2];
  46. EXPORT_SYMBOL_GPL(at91_ramc_base);
  47. void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  48. {
  49. if (id < 0 || id > 1) {
  50. pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  51. BUG();
  52. }
  53. at91_ramc_base[id] = ioremap(addr, size);
  54. if (!at91_ramc_base[id])
  55. panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
  56. }
  57. static struct map_desc sram_desc[2] __initdata;
  58. void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  59. {
  60. struct map_desc *desc = &sram_desc[bank];
  61. desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  62. if (bank > 0)
  63. desc->virtual -= sram_desc[bank - 1].length;
  64. desc->pfn = __phys_to_pfn(base);
  65. desc->length = length;
  66. desc->type = MT_MEMORY_NONCACHED;
  67. pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  68. base, length, desc->virtual);
  69. iotable_init(desc, 1);
  70. }
  71. static struct map_desc at91_io_desc __initdata __maybe_unused = {
  72. .virtual = (unsigned long)AT91_VA_BASE_SYS,
  73. .pfn = __phys_to_pfn(AT91_BASE_SYS),
  74. .length = SZ_16K,
  75. .type = MT_DEVICE,
  76. };
  77. static void __init soc_detect(u32 dbgu_base)
  78. {
  79. u32 cidr, socid;
  80. cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
  81. socid = cidr & ~AT91_CIDR_VERSION;
  82. switch (socid) {
  83. case ARCH_ID_AT91RM9200:
  84. at91_soc_initdata.type = AT91_SOC_RM9200;
  85. if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
  86. at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  87. at91_boot_soc = at91rm9200_soc;
  88. break;
  89. case ARCH_ID_AT91SAM9260:
  90. at91_soc_initdata.type = AT91_SOC_SAM9260;
  91. at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  92. at91_boot_soc = at91sam9260_soc;
  93. break;
  94. case ARCH_ID_AT91SAM9261:
  95. at91_soc_initdata.type = AT91_SOC_SAM9261;
  96. at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  97. at91_boot_soc = at91sam9261_soc;
  98. break;
  99. case ARCH_ID_AT91SAM9263:
  100. at91_soc_initdata.type = AT91_SOC_SAM9263;
  101. at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  102. at91_boot_soc = at91sam9263_soc;
  103. break;
  104. case ARCH_ID_AT91SAM9G20:
  105. at91_soc_initdata.type = AT91_SOC_SAM9G20;
  106. at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  107. at91_boot_soc = at91sam9260_soc;
  108. break;
  109. case ARCH_ID_AT91SAM9G45:
  110. at91_soc_initdata.type = AT91_SOC_SAM9G45;
  111. if (cidr == ARCH_ID_AT91SAM9G45ES)
  112. at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
  113. at91_boot_soc = at91sam9g45_soc;
  114. break;
  115. case ARCH_ID_AT91SAM9RL64:
  116. at91_soc_initdata.type = AT91_SOC_SAM9RL;
  117. at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  118. at91_boot_soc = at91sam9rl_soc;
  119. break;
  120. case ARCH_ID_AT91SAM9X5:
  121. at91_soc_initdata.type = AT91_SOC_SAM9X5;
  122. at91_boot_soc = at91sam9x5_soc;
  123. break;
  124. case ARCH_ID_AT91SAM9N12:
  125. at91_soc_initdata.type = AT91_SOC_SAM9N12;
  126. at91_boot_soc = at91sam9n12_soc;
  127. break;
  128. case ARCH_ID_SAMA5D3:
  129. at91_soc_initdata.type = AT91_SOC_SAMA5D3;
  130. at91_boot_soc = sama5d3_soc;
  131. break;
  132. }
  133. /* at91sam9g10 */
  134. if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
  135. at91_soc_initdata.type = AT91_SOC_SAM9G10;
  136. at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
  137. at91_boot_soc = at91sam9261_soc;
  138. }
  139. /* at91sam9xe */
  140. else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
  141. at91_soc_initdata.type = AT91_SOC_SAM9260;
  142. at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
  143. at91_boot_soc = at91sam9260_soc;
  144. }
  145. if (!at91_soc_is_detected())
  146. return;
  147. at91_soc_initdata.cidr = cidr;
  148. /* sub version of soc */
  149. at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
  150. if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
  151. switch (at91_soc_initdata.exid) {
  152. case ARCH_EXID_AT91SAM9M10:
  153. at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
  154. break;
  155. case ARCH_EXID_AT91SAM9G46:
  156. at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
  157. break;
  158. case ARCH_EXID_AT91SAM9M11:
  159. at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
  160. break;
  161. }
  162. }
  163. if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
  164. switch (at91_soc_initdata.exid) {
  165. case ARCH_EXID_AT91SAM9G15:
  166. at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
  167. break;
  168. case ARCH_EXID_AT91SAM9G35:
  169. at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
  170. break;
  171. case ARCH_EXID_AT91SAM9X35:
  172. at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
  173. break;
  174. case ARCH_EXID_AT91SAM9G25:
  175. at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
  176. break;
  177. case ARCH_EXID_AT91SAM9X25:
  178. at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
  179. break;
  180. }
  181. }
  182. if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
  183. switch (at91_soc_initdata.exid) {
  184. case ARCH_EXID_SAMA5D31:
  185. at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
  186. break;
  187. case ARCH_EXID_SAMA5D33:
  188. at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
  189. break;
  190. case ARCH_EXID_SAMA5D34:
  191. at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
  192. break;
  193. case ARCH_EXID_SAMA5D35:
  194. at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
  195. break;
  196. }
  197. }
  198. }
  199. static const char *soc_name[] = {
  200. [AT91_SOC_RM9200] = "at91rm9200",
  201. [AT91_SOC_SAM9260] = "at91sam9260",
  202. [AT91_SOC_SAM9261] = "at91sam9261",
  203. [AT91_SOC_SAM9263] = "at91sam9263",
  204. [AT91_SOC_SAM9G10] = "at91sam9g10",
  205. [AT91_SOC_SAM9G20] = "at91sam9g20",
  206. [AT91_SOC_SAM9G45] = "at91sam9g45",
  207. [AT91_SOC_SAM9RL] = "at91sam9rl",
  208. [AT91_SOC_SAM9X5] = "at91sam9x5",
  209. [AT91_SOC_SAM9N12] = "at91sam9n12",
  210. [AT91_SOC_SAMA5D3] = "sama5d3",
  211. [AT91_SOC_UNKNOWN] = "Unknown",
  212. };
  213. const char *at91_get_soc_type(struct at91_socinfo *c)
  214. {
  215. return soc_name[c->type];
  216. }
  217. EXPORT_SYMBOL(at91_get_soc_type);
  218. static const char *soc_subtype_name[] = {
  219. [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
  220. [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
  221. [AT91_SOC_SAM9XE] = "at91sam9xe",
  222. [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
  223. [AT91_SOC_SAM9M10] = "at91sam9m10",
  224. [AT91_SOC_SAM9G46] = "at91sam9g46",
  225. [AT91_SOC_SAM9M11] = "at91sam9m11",
  226. [AT91_SOC_SAM9G15] = "at91sam9g15",
  227. [AT91_SOC_SAM9G35] = "at91sam9g35",
  228. [AT91_SOC_SAM9X35] = "at91sam9x35",
  229. [AT91_SOC_SAM9G25] = "at91sam9g25",
  230. [AT91_SOC_SAM9X25] = "at91sam9x25",
  231. [AT91_SOC_SAMA5D31] = "sama5d31",
  232. [AT91_SOC_SAMA5D33] = "sama5d33",
  233. [AT91_SOC_SAMA5D34] = "sama5d34",
  234. [AT91_SOC_SAMA5D35] = "sama5d35",
  235. [AT91_SOC_SUBTYPE_NONE] = "None",
  236. [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
  237. };
  238. const char *at91_get_soc_subtype(struct at91_socinfo *c)
  239. {
  240. return soc_subtype_name[c->subtype];
  241. }
  242. EXPORT_SYMBOL(at91_get_soc_subtype);
  243. void __init at91_map_io(void)
  244. {
  245. /* Map peripherals */
  246. iotable_init(&at91_io_desc, 1);
  247. at91_soc_initdata.type = AT91_SOC_UNKNOWN;
  248. at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
  249. soc_detect(AT91_BASE_DBGU0);
  250. if (!at91_soc_is_detected())
  251. soc_detect(AT91_BASE_DBGU1);
  252. if (!at91_soc_is_detected())
  253. panic("AT91: Impossible to detect the SOC type");
  254. pr_info("AT91: Detected soc type: %s\n",
  255. at91_get_soc_type(&at91_soc_initdata));
  256. if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
  257. pr_info("AT91: Detected soc subtype: %s\n",
  258. at91_get_soc_subtype(&at91_soc_initdata));
  259. if (!at91_soc_is_enabled())
  260. panic("AT91: Soc not enabled");
  261. if (at91_boot_soc.map_io)
  262. at91_boot_soc.map_io();
  263. }
  264. void __iomem *at91_shdwc_base = NULL;
  265. static void at91sam9_poweroff(void)
  266. {
  267. at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
  268. }
  269. void __init at91_ioremap_shdwc(u32 base_addr)
  270. {
  271. at91_shdwc_base = ioremap(base_addr, 16);
  272. if (!at91_shdwc_base)
  273. panic("Impossible to ioremap at91_shdwc_base\n");
  274. pm_power_off = at91sam9_poweroff;
  275. }
  276. void __iomem *at91_rstc_base;
  277. void __init at91_ioremap_rstc(u32 base_addr)
  278. {
  279. at91_rstc_base = ioremap(base_addr, 16);
  280. if (!at91_rstc_base)
  281. panic("Impossible to ioremap at91_rstc_base\n");
  282. }
  283. void __iomem *at91_matrix_base;
  284. EXPORT_SYMBOL_GPL(at91_matrix_base);
  285. void __init at91_ioremap_matrix(u32 base_addr)
  286. {
  287. at91_matrix_base = ioremap(base_addr, 512);
  288. if (!at91_matrix_base)
  289. panic("Impossible to ioremap at91_matrix_base\n");
  290. }
  291. #if defined(CONFIG_OF)
  292. static struct of_device_id rstc_ids[] = {
  293. { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
  294. { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
  295. { /*sentinel*/ }
  296. };
  297. static void at91_dt_rstc(void)
  298. {
  299. struct device_node *np;
  300. const struct of_device_id *of_id;
  301. np = of_find_matching_node(NULL, rstc_ids);
  302. if (!np)
  303. panic("unable to find compatible rstc node in dtb\n");
  304. at91_rstc_base = of_iomap(np, 0);
  305. if (!at91_rstc_base)
  306. panic("unable to map rstc cpu registers\n");
  307. of_id = of_match_node(rstc_ids, np);
  308. if (!of_id)
  309. panic("AT91: rtsc no restart function available\n");
  310. arm_pm_restart = of_id->data;
  311. of_node_put(np);
  312. }
  313. static struct of_device_id ramc_ids[] = {
  314. { .compatible = "atmel,at91rm9200-sdramc" },
  315. { .compatible = "atmel,at91sam9260-sdramc" },
  316. { .compatible = "atmel,at91sam9g45-ddramc" },
  317. { /*sentinel*/ }
  318. };
  319. static void at91_dt_ramc(void)
  320. {
  321. struct device_node *np;
  322. np = of_find_matching_node(NULL, ramc_ids);
  323. if (!np)
  324. panic("unable to find compatible ram controller node in dtb\n");
  325. at91_ramc_base[0] = of_iomap(np, 0);
  326. if (!at91_ramc_base[0])
  327. panic("unable to map ramc[0] cpu registers\n");
  328. /* the controller may have 2 banks */
  329. at91_ramc_base[1] = of_iomap(np, 1);
  330. of_node_put(np);
  331. }
  332. static struct of_device_id shdwc_ids[] = {
  333. { .compatible = "atmel,at91sam9260-shdwc", },
  334. { .compatible = "atmel,at91sam9rl-shdwc", },
  335. { .compatible = "atmel,at91sam9x5-shdwc", },
  336. { /*sentinel*/ }
  337. };
  338. static const char *shdwc_wakeup_modes[] = {
  339. [AT91_SHDW_WKMODE0_NONE] = "none",
  340. [AT91_SHDW_WKMODE0_HIGH] = "high",
  341. [AT91_SHDW_WKMODE0_LOW] = "low",
  342. [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
  343. };
  344. const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
  345. {
  346. const char *pm;
  347. int err, i;
  348. err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
  349. if (err < 0)
  350. return AT91_SHDW_WKMODE0_ANYLEVEL;
  351. for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
  352. if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
  353. return i;
  354. return -ENODEV;
  355. }
  356. static void at91_dt_shdwc(void)
  357. {
  358. struct device_node *np;
  359. int wakeup_mode;
  360. u32 reg;
  361. u32 mode = 0;
  362. np = of_find_matching_node(NULL, shdwc_ids);
  363. if (!np) {
  364. pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
  365. return;
  366. }
  367. at91_shdwc_base = of_iomap(np, 0);
  368. if (!at91_shdwc_base)
  369. panic("AT91: unable to map shdwc cpu registers\n");
  370. wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
  371. if (wakeup_mode < 0) {
  372. pr_warn("AT91: shdwc unknown wakeup mode\n");
  373. goto end;
  374. }
  375. if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
  376. if (reg > AT91_SHDW_CPTWK0_MAX) {
  377. pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
  378. reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
  379. reg = AT91_SHDW_CPTWK0_MAX;
  380. }
  381. mode |= AT91_SHDW_CPTWK0_(reg);
  382. }
  383. if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
  384. mode |= AT91_SHDW_RTCWKEN;
  385. if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
  386. mode |= AT91_SHDW_RTTWKEN;
  387. at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
  388. end:
  389. pm_power_off = at91sam9_poweroff;
  390. of_node_put(np);
  391. }
  392. void __init at91rm9200_dt_initialize(void)
  393. {
  394. at91_dt_ramc();
  395. /* Init clock subsystem */
  396. at91_dt_clock_init();
  397. /* Register the processor-specific clocks */
  398. at91_boot_soc.register_clocks();
  399. at91_boot_soc.init();
  400. }
  401. void __init at91_dt_initialize(void)
  402. {
  403. at91_dt_rstc();
  404. at91_dt_ramc();
  405. at91_dt_shdwc();
  406. /* Init clock subsystem */
  407. at91_dt_clock_init();
  408. /* Register the processor-specific clocks */
  409. at91_boot_soc.register_clocks();
  410. if (at91_boot_soc.init)
  411. at91_boot_soc.init();
  412. }
  413. #endif
  414. void __init at91_initialize(unsigned long main_clock)
  415. {
  416. at91_boot_soc.ioremap_registers();
  417. /* Init clock subsystem */
  418. at91_clock_init(main_clock);
  419. /* Register the processor-specific clocks */
  420. at91_boot_soc.register_clocks();
  421. at91_boot_soc.init();
  422. pinctrl_provide_dummies();
  423. }