irq.c 13 KB

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  1. /*
  2. * linux/arch/arm/mach-at91/irq.c
  3. *
  4. * Copyright (C) 2004 SAN People
  5. * Copyright (C) 2004 ATMEL
  6. * Copyright (C) Rick Bronson
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/mm.h>
  25. #include <linux/bitmap.h>
  26. #include <linux/types.h>
  27. #include <linux/irq.h>
  28. #include <linux/of.h>
  29. #include <linux/of_address.h>
  30. #include <linux/of_irq.h>
  31. #include <linux/irqdomain.h>
  32. #include <linux/err.h>
  33. #include <linux/slab.h>
  34. #include <mach/hardware.h>
  35. #include <asm/irq.h>
  36. #include <asm/setup.h>
  37. #include <asm/exception.h>
  38. #include <asm/mach/arch.h>
  39. #include <asm/mach/irq.h>
  40. #include <asm/mach/map.h>
  41. #include "at91_aic.h"
  42. void __iomem *at91_aic_base;
  43. static struct irq_domain *at91_aic_domain;
  44. static struct device_node *at91_aic_np;
  45. static unsigned int n_irqs = NR_AIC_IRQS;
  46. static unsigned long at91_aic_caps = 0;
  47. /* AIC5 introduces a Source Select Register */
  48. #define AT91_AIC_CAP_AIC5 (1 << 0)
  49. #define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5)
  50. #ifdef CONFIG_PM
  51. static unsigned long *wakeups;
  52. static unsigned long *backups;
  53. #define set_backup(bit) set_bit(bit, backups)
  54. #define clear_backup(bit) clear_bit(bit, backups)
  55. static int at91_aic_pm_init(void)
  56. {
  57. backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
  58. if (!backups)
  59. return -ENOMEM;
  60. wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
  61. if (!wakeups) {
  62. kfree(backups);
  63. return -ENOMEM;
  64. }
  65. return 0;
  66. }
  67. static int at91_aic_set_wake(struct irq_data *d, unsigned value)
  68. {
  69. if (unlikely(d->hwirq >= n_irqs))
  70. return -EINVAL;
  71. if (value)
  72. set_bit(d->hwirq, wakeups);
  73. else
  74. clear_bit(d->hwirq, wakeups);
  75. return 0;
  76. }
  77. void at91_irq_suspend(void)
  78. {
  79. int bit = -1;
  80. if (has_aic5()) {
  81. /* disable enabled irqs */
  82. while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
  83. at91_aic_write(AT91_AIC5_SSR,
  84. bit & AT91_AIC5_INTSEL_MSK);
  85. at91_aic_write(AT91_AIC5_IDCR, 1);
  86. }
  87. /* enable wakeup irqs */
  88. bit = -1;
  89. while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
  90. at91_aic_write(AT91_AIC5_SSR,
  91. bit & AT91_AIC5_INTSEL_MSK);
  92. at91_aic_write(AT91_AIC5_IECR, 1);
  93. }
  94. } else {
  95. at91_aic_write(AT91_AIC_IDCR, *backups);
  96. at91_aic_write(AT91_AIC_IECR, *wakeups);
  97. }
  98. }
  99. void at91_irq_resume(void)
  100. {
  101. int bit = -1;
  102. if (has_aic5()) {
  103. /* disable wakeup irqs */
  104. while ((bit = find_next_bit(wakeups, n_irqs, bit + 1)) < n_irqs) {
  105. at91_aic_write(AT91_AIC5_SSR,
  106. bit & AT91_AIC5_INTSEL_MSK);
  107. at91_aic_write(AT91_AIC5_IDCR, 1);
  108. }
  109. /* enable irqs disabled for suspend */
  110. bit = -1;
  111. while ((bit = find_next_bit(backups, n_irqs, bit + 1)) < n_irqs) {
  112. at91_aic_write(AT91_AIC5_SSR,
  113. bit & AT91_AIC5_INTSEL_MSK);
  114. at91_aic_write(AT91_AIC5_IECR, 1);
  115. }
  116. } else {
  117. at91_aic_write(AT91_AIC_IDCR, *wakeups);
  118. at91_aic_write(AT91_AIC_IECR, *backups);
  119. }
  120. }
  121. #else
  122. static inline int at91_aic_pm_init(void)
  123. {
  124. return 0;
  125. }
  126. #define set_backup(bit)
  127. #define clear_backup(bit)
  128. #define at91_aic_set_wake NULL
  129. #endif /* CONFIG_PM */
  130. asmlinkage void __exception_irq_entry
  131. at91_aic_handle_irq(struct pt_regs *regs)
  132. {
  133. u32 irqnr;
  134. u32 irqstat;
  135. irqnr = at91_aic_read(AT91_AIC_IVR);
  136. irqstat = at91_aic_read(AT91_AIC_ISR);
  137. /*
  138. * ISR value is 0 when there is no current interrupt or when there is
  139. * a spurious interrupt
  140. */
  141. if (!irqstat)
  142. at91_aic_write(AT91_AIC_EOICR, 0);
  143. else
  144. handle_IRQ(irqnr, regs);
  145. }
  146. asmlinkage void __exception_irq_entry
  147. at91_aic5_handle_irq(struct pt_regs *regs)
  148. {
  149. u32 irqnr;
  150. u32 irqstat;
  151. irqnr = at91_aic_read(AT91_AIC5_IVR);
  152. irqstat = at91_aic_read(AT91_AIC5_ISR);
  153. if (!irqstat)
  154. at91_aic_write(AT91_AIC5_EOICR, 0);
  155. else
  156. handle_IRQ(irqnr, regs);
  157. }
  158. static void at91_aic_mask_irq(struct irq_data *d)
  159. {
  160. /* Disable interrupt on AIC */
  161. at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
  162. /* Update ISR cache */
  163. clear_backup(d->hwirq);
  164. }
  165. static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
  166. {
  167. /* Disable interrupt on AIC5 */
  168. at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
  169. at91_aic_write(AT91_AIC5_IDCR, 1);
  170. /* Update ISR cache */
  171. clear_backup(d->hwirq);
  172. }
  173. static void at91_aic_unmask_irq(struct irq_data *d)
  174. {
  175. /* Enable interrupt on AIC */
  176. at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
  177. /* Update ISR cache */
  178. set_backup(d->hwirq);
  179. }
  180. static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
  181. {
  182. /* Enable interrupt on AIC5 */
  183. at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
  184. at91_aic_write(AT91_AIC5_IECR, 1);
  185. /* Update ISR cache */
  186. set_backup(d->hwirq);
  187. }
  188. static void at91_aic_eoi(struct irq_data *d)
  189. {
  190. /*
  191. * Mark end-of-interrupt on AIC, the controller doesn't care about
  192. * the value written. Moreover it's a write-only register.
  193. */
  194. at91_aic_write(AT91_AIC_EOICR, 0);
  195. }
  196. static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
  197. {
  198. at91_aic_write(AT91_AIC5_EOICR, 0);
  199. }
  200. static unsigned long *at91_extern_irq;
  201. u32 at91_get_extern_irq(void)
  202. {
  203. if (!at91_extern_irq)
  204. return 0;
  205. return *at91_extern_irq;
  206. }
  207. #define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
  208. static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
  209. {
  210. int srctype;
  211. switch (type) {
  212. case IRQ_TYPE_LEVEL_HIGH:
  213. srctype = AT91_AIC_SRCTYPE_HIGH;
  214. break;
  215. case IRQ_TYPE_EDGE_RISING:
  216. srctype = AT91_AIC_SRCTYPE_RISING;
  217. break;
  218. case IRQ_TYPE_LEVEL_LOW:
  219. if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
  220. srctype = AT91_AIC_SRCTYPE_LOW;
  221. else
  222. srctype = -EINVAL;
  223. break;
  224. case IRQ_TYPE_EDGE_FALLING:
  225. if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
  226. srctype = AT91_AIC_SRCTYPE_FALLING;
  227. else
  228. srctype = -EINVAL;
  229. break;
  230. default:
  231. srctype = -EINVAL;
  232. }
  233. return srctype;
  234. }
  235. static int at91_aic_set_type(struct irq_data *d, unsigned type)
  236. {
  237. unsigned int smr;
  238. int srctype;
  239. srctype = at91_aic_compute_srctype(d, type);
  240. if (srctype < 0)
  241. return srctype;
  242. if (has_aic5()) {
  243. at91_aic_write(AT91_AIC5_SSR,
  244. d->hwirq & AT91_AIC5_INTSEL_MSK);
  245. smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
  246. at91_aic_write(AT91_AIC5_SMR, smr | srctype);
  247. } else {
  248. smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
  249. & ~AT91_AIC_SRCTYPE;
  250. at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
  251. }
  252. return 0;
  253. }
  254. static struct irq_chip at91_aic_chip = {
  255. .name = "AIC",
  256. .irq_mask = at91_aic_mask_irq,
  257. .irq_unmask = at91_aic_unmask_irq,
  258. .irq_set_type = at91_aic_set_type,
  259. .irq_set_wake = at91_aic_set_wake,
  260. .irq_eoi = at91_aic_eoi,
  261. };
  262. static void __init at91_aic_hw_init(unsigned int spu_vector)
  263. {
  264. int i;
  265. /*
  266. * Perform 8 End Of Interrupt Command to make sure AIC
  267. * will not Lock out nIRQ
  268. */
  269. for (i = 0; i < 8; i++)
  270. at91_aic_write(AT91_AIC_EOICR, 0);
  271. /*
  272. * Spurious Interrupt ID in Spurious Vector Register.
  273. * When there is no current interrupt, the IRQ Vector Register
  274. * reads the value stored in AIC_SPU
  275. */
  276. at91_aic_write(AT91_AIC_SPU, spu_vector);
  277. /* No debugging in AIC: Debug (Protect) Control Register */
  278. at91_aic_write(AT91_AIC_DCR, 0);
  279. /* Disable and clear all interrupts initially */
  280. at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
  281. at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
  282. }
  283. static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
  284. {
  285. int i;
  286. /*
  287. * Perform 8 End Of Interrupt Command to make sure AIC
  288. * will not Lock out nIRQ
  289. */
  290. for (i = 0; i < 8; i++)
  291. at91_aic_write(AT91_AIC5_EOICR, 0);
  292. /*
  293. * Spurious Interrupt ID in Spurious Vector Register.
  294. * When there is no current interrupt, the IRQ Vector Register
  295. * reads the value stored in AIC_SPU
  296. */
  297. at91_aic_write(AT91_AIC5_SPU, spu_vector);
  298. /* No debugging in AIC: Debug (Protect) Control Register */
  299. at91_aic_write(AT91_AIC5_DCR, 0);
  300. /* Disable and clear all interrupts initially */
  301. for (i = 0; i < n_irqs; i++) {
  302. at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
  303. at91_aic_write(AT91_AIC5_IDCR, 1);
  304. at91_aic_write(AT91_AIC5_ICCR, 1);
  305. }
  306. }
  307. #if defined(CONFIG_OF)
  308. static unsigned int *at91_aic_irq_priorities;
  309. static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
  310. irq_hw_number_t hw)
  311. {
  312. /* Put virq number in Source Vector Register */
  313. at91_aic_write(AT91_AIC_SVR(hw), virq);
  314. /* Active Low interrupt, with priority */
  315. at91_aic_write(AT91_AIC_SMR(hw),
  316. AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
  317. irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
  318. set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
  319. return 0;
  320. }
  321. static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
  322. irq_hw_number_t hw)
  323. {
  324. at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
  325. /* Put virq number in Source Vector Register */
  326. at91_aic_write(AT91_AIC5_SVR, virq);
  327. /* Active Low interrupt, with priority */
  328. at91_aic_write(AT91_AIC5_SMR,
  329. AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
  330. irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
  331. set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
  332. return 0;
  333. }
  334. static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
  335. const u32 *intspec, unsigned int intsize,
  336. irq_hw_number_t *out_hwirq, unsigned int *out_type)
  337. {
  338. if (WARN_ON(intsize < 3))
  339. return -EINVAL;
  340. if (WARN_ON(intspec[0] >= n_irqs))
  341. return -EINVAL;
  342. if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
  343. || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
  344. return -EINVAL;
  345. *out_hwirq = intspec[0];
  346. *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
  347. at91_aic_irq_priorities[*out_hwirq] = intspec[2];
  348. return 0;
  349. }
  350. static struct irq_domain_ops at91_aic_irq_ops = {
  351. .map = at91_aic_irq_map,
  352. .xlate = at91_aic_irq_domain_xlate,
  353. };
  354. int __init at91_aic_of_common_init(struct device_node *node,
  355. struct device_node *parent)
  356. {
  357. struct property *prop;
  358. const __be32 *p;
  359. u32 val;
  360. at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
  361. * sizeof(*at91_extern_irq), GFP_KERNEL);
  362. if (!at91_extern_irq)
  363. return -ENOMEM;
  364. if (at91_aic_pm_init()) {
  365. kfree(at91_extern_irq);
  366. return -ENOMEM;
  367. }
  368. at91_aic_irq_priorities = kzalloc(n_irqs
  369. * sizeof(*at91_aic_irq_priorities),
  370. GFP_KERNEL);
  371. if (!at91_aic_irq_priorities)
  372. return -ENOMEM;
  373. at91_aic_base = of_iomap(node, 0);
  374. at91_aic_np = node;
  375. at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
  376. &at91_aic_irq_ops, NULL);
  377. if (!at91_aic_domain)
  378. panic("Unable to add AIC irq domain (DT)\n");
  379. of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
  380. if (val >= n_irqs)
  381. pr_warn("AIC: external irq %d >= %d skip it\n",
  382. val, n_irqs);
  383. else
  384. set_bit(val, at91_extern_irq);
  385. }
  386. irq_set_default_host(at91_aic_domain);
  387. return 0;
  388. }
  389. int __init at91_aic_of_init(struct device_node *node,
  390. struct device_node *parent)
  391. {
  392. int err;
  393. err = at91_aic_of_common_init(node, parent);
  394. if (err)
  395. return err;
  396. at91_aic_hw_init(n_irqs);
  397. return 0;
  398. }
  399. int __init at91_aic5_of_init(struct device_node *node,
  400. struct device_node *parent)
  401. {
  402. int err;
  403. at91_aic_caps |= AT91_AIC_CAP_AIC5;
  404. n_irqs = NR_AIC5_IRQS;
  405. at91_aic_chip.irq_ack = at91_aic5_mask_irq;
  406. at91_aic_chip.irq_mask = at91_aic5_mask_irq;
  407. at91_aic_chip.irq_unmask = at91_aic5_unmask_irq;
  408. at91_aic_chip.irq_eoi = at91_aic5_eoi;
  409. at91_aic_irq_ops.map = at91_aic5_irq_map;
  410. err = at91_aic_of_common_init(node, parent);
  411. if (err)
  412. return err;
  413. at91_aic5_hw_init(n_irqs);
  414. return 0;
  415. }
  416. #endif
  417. /*
  418. * Initialize the AIC interrupt controller.
  419. */
  420. void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
  421. {
  422. unsigned int i;
  423. int irq_base;
  424. at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
  425. * sizeof(*at91_extern_irq), GFP_KERNEL);
  426. if (at91_aic_pm_init() || at91_extern_irq == NULL)
  427. panic("Unable to allocate bit maps\n");
  428. *at91_extern_irq = ext_irq_mask;
  429. at91_aic_base = ioremap(AT91_AIC, 512);
  430. if (!at91_aic_base)
  431. panic("Unable to ioremap AIC registers\n");
  432. /* Add irq domain for AIC */
  433. irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
  434. if (irq_base < 0) {
  435. WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
  436. irq_base = 0;
  437. }
  438. at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
  439. irq_base, 0,
  440. &irq_domain_simple_ops, NULL);
  441. if (!at91_aic_domain)
  442. panic("Unable to add AIC irq domain\n");
  443. irq_set_default_host(at91_aic_domain);
  444. /*
  445. * The IVR is used by macro get_irqnr_and_base to read and verify.
  446. * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
  447. */
  448. for (i = 0; i < n_irqs; i++) {
  449. /* Put hardware irq number in Source Vector Register: */
  450. at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
  451. /* Active Low interrupt, with the specified priority */
  452. at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
  453. irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
  454. set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
  455. }
  456. at91_aic_hw_init(n_irqs);
  457. }