at91rm9200.c 11 KB

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  1. /*
  2. * arch/arm/mach-at91/at91rm9200.c
  3. *
  4. * Copyright (C) 2005 SAN People
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. */
  12. #include <linux/module.h>
  13. #include <linux/reboot.h>
  14. #include <asm/irq.h>
  15. #include <asm/mach/arch.h>
  16. #include <asm/mach/map.h>
  17. #include <asm/system_misc.h>
  18. #include <mach/at91rm9200.h>
  19. #include <mach/at91_pmc.h>
  20. #include <mach/at91_st.h>
  21. #include <mach/cpu.h>
  22. #include "at91_aic.h"
  23. #include "soc.h"
  24. #include "generic.h"
  25. #include "clock.h"
  26. #include "sam9_smc.h"
  27. /* --------------------------------------------------------------------
  28. * Clocks
  29. * -------------------------------------------------------------------- */
  30. /*
  31. * The peripheral clocks.
  32. */
  33. static struct clk udc_clk = {
  34. .name = "udc_clk",
  35. .pmc_mask = 1 << AT91RM9200_ID_UDP,
  36. .type = CLK_TYPE_PERIPHERAL,
  37. };
  38. static struct clk ohci_clk = {
  39. .name = "ohci_clk",
  40. .pmc_mask = 1 << AT91RM9200_ID_UHP,
  41. .type = CLK_TYPE_PERIPHERAL,
  42. };
  43. static struct clk ether_clk = {
  44. .name = "ether_clk",
  45. .pmc_mask = 1 << AT91RM9200_ID_EMAC,
  46. .type = CLK_TYPE_PERIPHERAL,
  47. };
  48. static struct clk mmc_clk = {
  49. .name = "mci_clk",
  50. .pmc_mask = 1 << AT91RM9200_ID_MCI,
  51. .type = CLK_TYPE_PERIPHERAL,
  52. };
  53. static struct clk twi_clk = {
  54. .name = "twi_clk",
  55. .pmc_mask = 1 << AT91RM9200_ID_TWI,
  56. .type = CLK_TYPE_PERIPHERAL,
  57. };
  58. static struct clk usart0_clk = {
  59. .name = "usart0_clk",
  60. .pmc_mask = 1 << AT91RM9200_ID_US0,
  61. .type = CLK_TYPE_PERIPHERAL,
  62. };
  63. static struct clk usart1_clk = {
  64. .name = "usart1_clk",
  65. .pmc_mask = 1 << AT91RM9200_ID_US1,
  66. .type = CLK_TYPE_PERIPHERAL,
  67. };
  68. static struct clk usart2_clk = {
  69. .name = "usart2_clk",
  70. .pmc_mask = 1 << AT91RM9200_ID_US2,
  71. .type = CLK_TYPE_PERIPHERAL,
  72. };
  73. static struct clk usart3_clk = {
  74. .name = "usart3_clk",
  75. .pmc_mask = 1 << AT91RM9200_ID_US3,
  76. .type = CLK_TYPE_PERIPHERAL,
  77. };
  78. static struct clk spi_clk = {
  79. .name = "spi_clk",
  80. .pmc_mask = 1 << AT91RM9200_ID_SPI,
  81. .type = CLK_TYPE_PERIPHERAL,
  82. };
  83. static struct clk pioA_clk = {
  84. .name = "pioA_clk",
  85. .pmc_mask = 1 << AT91RM9200_ID_PIOA,
  86. .type = CLK_TYPE_PERIPHERAL,
  87. };
  88. static struct clk pioB_clk = {
  89. .name = "pioB_clk",
  90. .pmc_mask = 1 << AT91RM9200_ID_PIOB,
  91. .type = CLK_TYPE_PERIPHERAL,
  92. };
  93. static struct clk pioC_clk = {
  94. .name = "pioC_clk",
  95. .pmc_mask = 1 << AT91RM9200_ID_PIOC,
  96. .type = CLK_TYPE_PERIPHERAL,
  97. };
  98. static struct clk pioD_clk = {
  99. .name = "pioD_clk",
  100. .pmc_mask = 1 << AT91RM9200_ID_PIOD,
  101. .type = CLK_TYPE_PERIPHERAL,
  102. };
  103. static struct clk ssc0_clk = {
  104. .name = "ssc0_clk",
  105. .pmc_mask = 1 << AT91RM9200_ID_SSC0,
  106. .type = CLK_TYPE_PERIPHERAL,
  107. };
  108. static struct clk ssc1_clk = {
  109. .name = "ssc1_clk",
  110. .pmc_mask = 1 << AT91RM9200_ID_SSC1,
  111. .type = CLK_TYPE_PERIPHERAL,
  112. };
  113. static struct clk ssc2_clk = {
  114. .name = "ssc2_clk",
  115. .pmc_mask = 1 << AT91RM9200_ID_SSC2,
  116. .type = CLK_TYPE_PERIPHERAL,
  117. };
  118. static struct clk tc0_clk = {
  119. .name = "tc0_clk",
  120. .pmc_mask = 1 << AT91RM9200_ID_TC0,
  121. .type = CLK_TYPE_PERIPHERAL,
  122. };
  123. static struct clk tc1_clk = {
  124. .name = "tc1_clk",
  125. .pmc_mask = 1 << AT91RM9200_ID_TC1,
  126. .type = CLK_TYPE_PERIPHERAL,
  127. };
  128. static struct clk tc2_clk = {
  129. .name = "tc2_clk",
  130. .pmc_mask = 1 << AT91RM9200_ID_TC2,
  131. .type = CLK_TYPE_PERIPHERAL,
  132. };
  133. static struct clk tc3_clk = {
  134. .name = "tc3_clk",
  135. .pmc_mask = 1 << AT91RM9200_ID_TC3,
  136. .type = CLK_TYPE_PERIPHERAL,
  137. };
  138. static struct clk tc4_clk = {
  139. .name = "tc4_clk",
  140. .pmc_mask = 1 << AT91RM9200_ID_TC4,
  141. .type = CLK_TYPE_PERIPHERAL,
  142. };
  143. static struct clk tc5_clk = {
  144. .name = "tc5_clk",
  145. .pmc_mask = 1 << AT91RM9200_ID_TC5,
  146. .type = CLK_TYPE_PERIPHERAL,
  147. };
  148. static struct clk *periph_clocks[] __initdata = {
  149. &pioA_clk,
  150. &pioB_clk,
  151. &pioC_clk,
  152. &pioD_clk,
  153. &usart0_clk,
  154. &usart1_clk,
  155. &usart2_clk,
  156. &usart3_clk,
  157. &mmc_clk,
  158. &udc_clk,
  159. &twi_clk,
  160. &spi_clk,
  161. &ssc0_clk,
  162. &ssc1_clk,
  163. &ssc2_clk,
  164. &tc0_clk,
  165. &tc1_clk,
  166. &tc2_clk,
  167. &tc3_clk,
  168. &tc4_clk,
  169. &tc5_clk,
  170. &ohci_clk,
  171. &ether_clk,
  172. // irq0 .. irq6
  173. };
  174. static struct clk_lookup periph_clocks_lookups[] = {
  175. CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
  176. CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
  177. CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
  178. CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
  179. CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
  180. CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
  181. CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
  182. CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
  183. CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
  184. CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
  185. CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
  186. CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
  187. CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
  188. /* fake hclk clock */
  189. CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
  190. CLKDEV_CON_ID("pioA", &pioA_clk),
  191. CLKDEV_CON_ID("pioB", &pioB_clk),
  192. CLKDEV_CON_ID("pioC", &pioC_clk),
  193. CLKDEV_CON_ID("pioD", &pioD_clk),
  194. /* usart lookup table for DT entries */
  195. CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
  196. CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
  197. CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
  198. CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
  199. CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
  200. /* tc lookup table for DT entries */
  201. CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
  202. CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
  203. CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
  204. CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
  205. CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
  206. CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
  207. CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
  208. CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
  209. CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
  210. CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
  211. CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
  212. CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
  213. CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
  214. CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
  215. };
  216. static struct clk_lookup usart_clocks_lookups[] = {
  217. CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
  218. CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
  219. CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
  220. CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
  221. CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
  222. };
  223. /*
  224. * The four programmable clocks.
  225. * You must configure pin multiplexing to bring these signals out.
  226. */
  227. static struct clk pck0 = {
  228. .name = "pck0",
  229. .pmc_mask = AT91_PMC_PCK0,
  230. .type = CLK_TYPE_PROGRAMMABLE,
  231. .id = 0,
  232. };
  233. static struct clk pck1 = {
  234. .name = "pck1",
  235. .pmc_mask = AT91_PMC_PCK1,
  236. .type = CLK_TYPE_PROGRAMMABLE,
  237. .id = 1,
  238. };
  239. static struct clk pck2 = {
  240. .name = "pck2",
  241. .pmc_mask = AT91_PMC_PCK2,
  242. .type = CLK_TYPE_PROGRAMMABLE,
  243. .id = 2,
  244. };
  245. static struct clk pck3 = {
  246. .name = "pck3",
  247. .pmc_mask = AT91_PMC_PCK3,
  248. .type = CLK_TYPE_PROGRAMMABLE,
  249. .id = 3,
  250. };
  251. static void __init at91rm9200_register_clocks(void)
  252. {
  253. int i;
  254. for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
  255. clk_register(periph_clocks[i]);
  256. clkdev_add_table(periph_clocks_lookups,
  257. ARRAY_SIZE(periph_clocks_lookups));
  258. clkdev_add_table(usart_clocks_lookups,
  259. ARRAY_SIZE(usart_clocks_lookups));
  260. clk_register(&pck0);
  261. clk_register(&pck1);
  262. clk_register(&pck2);
  263. clk_register(&pck3);
  264. }
  265. /* --------------------------------------------------------------------
  266. * GPIO
  267. * -------------------------------------------------------------------- */
  268. static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
  269. {
  270. .id = AT91RM9200_ID_PIOA,
  271. .regbase = AT91RM9200_BASE_PIOA,
  272. }, {
  273. .id = AT91RM9200_ID_PIOB,
  274. .regbase = AT91RM9200_BASE_PIOB,
  275. }, {
  276. .id = AT91RM9200_ID_PIOC,
  277. .regbase = AT91RM9200_BASE_PIOC,
  278. }, {
  279. .id = AT91RM9200_ID_PIOD,
  280. .regbase = AT91RM9200_BASE_PIOD,
  281. }
  282. };
  283. static void at91rm9200_idle(void)
  284. {
  285. /*
  286. * Disable the processor clock. The processor will be automatically
  287. * re-enabled by an interrupt or by a reset.
  288. */
  289. at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
  290. }
  291. static void at91rm9200_restart(enum reboot_mode reboot_mode, const char *cmd)
  292. {
  293. /*
  294. * Perform a hardware reset with the use of the Watchdog timer.
  295. */
  296. at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
  297. at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
  298. }
  299. /* --------------------------------------------------------------------
  300. * AT91RM9200 processor initialization
  301. * -------------------------------------------------------------------- */
  302. static void __init at91rm9200_map_io(void)
  303. {
  304. /* Map peripherals */
  305. at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
  306. }
  307. static void __init at91rm9200_ioremap_registers(void)
  308. {
  309. at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
  310. at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
  311. }
  312. static void __init at91rm9200_initialize(void)
  313. {
  314. arm_pm_idle = at91rm9200_idle;
  315. arm_pm_restart = at91rm9200_restart;
  316. /* Initialize GPIO subsystem */
  317. at91_gpio_init(at91rm9200_gpio,
  318. cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
  319. }
  320. /* --------------------------------------------------------------------
  321. * Interrupt initialization
  322. * -------------------------------------------------------------------- */
  323. /*
  324. * The default interrupt priority levels (0 = lowest, 7 = highest).
  325. */
  326. static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
  327. 7, /* Advanced Interrupt Controller (FIQ) */
  328. 7, /* System Peripherals */
  329. 1, /* Parallel IO Controller A */
  330. 1, /* Parallel IO Controller B */
  331. 1, /* Parallel IO Controller C */
  332. 1, /* Parallel IO Controller D */
  333. 5, /* USART 0 */
  334. 5, /* USART 1 */
  335. 5, /* USART 2 */
  336. 5, /* USART 3 */
  337. 0, /* Multimedia Card Interface */
  338. 2, /* USB Device Port */
  339. 6, /* Two-Wire Interface */
  340. 5, /* Serial Peripheral Interface */
  341. 4, /* Serial Synchronous Controller 0 */
  342. 4, /* Serial Synchronous Controller 1 */
  343. 4, /* Serial Synchronous Controller 2 */
  344. 0, /* Timer Counter 0 */
  345. 0, /* Timer Counter 1 */
  346. 0, /* Timer Counter 2 */
  347. 0, /* Timer Counter 3 */
  348. 0, /* Timer Counter 4 */
  349. 0, /* Timer Counter 5 */
  350. 2, /* USB Host port */
  351. 3, /* Ethernet MAC */
  352. 0, /* Advanced Interrupt Controller (IRQ0) */
  353. 0, /* Advanced Interrupt Controller (IRQ1) */
  354. 0, /* Advanced Interrupt Controller (IRQ2) */
  355. 0, /* Advanced Interrupt Controller (IRQ3) */
  356. 0, /* Advanced Interrupt Controller (IRQ4) */
  357. 0, /* Advanced Interrupt Controller (IRQ5) */
  358. 0 /* Advanced Interrupt Controller (IRQ6) */
  359. };
  360. AT91_SOC_START(at91rm9200)
  361. .map_io = at91rm9200_map_io,
  362. .default_irq_priority = at91rm9200_default_irq_priority,
  363. .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
  364. | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
  365. | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
  366. | (1 << AT91RM9200_ID_IRQ6),
  367. .ioremap_registers = at91rm9200_ioremap_registers,
  368. .register_clocks = at91rm9200_register_clocks,
  369. .init = at91rm9200_initialize,
  370. AT91_SOC_END