init.S 4.3 KB

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  1. /*
  2. * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  3. * Author: Christoffer Dall <c.dall@virtualopensystems.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License, version 2, as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  17. */
  18. #include <linux/linkage.h>
  19. #include <asm/unified.h>
  20. #include <asm/asm-offsets.h>
  21. #include <asm/kvm_asm.h>
  22. #include <asm/kvm_arm.h>
  23. #include <asm/kvm_mmu.h>
  24. /********************************************************************
  25. * Hypervisor initialization
  26. * - should be called with:
  27. * r0 = top of Hyp stack (kernel VA)
  28. * r1 = pointer to hyp vectors
  29. * r2,r3 = Hypervisor pgd pointer
  30. *
  31. * The init scenario is:
  32. * - We jump in HYP with four parameters: boot HYP pgd, runtime HYP pgd,
  33. * runtime stack, runtime vectors
  34. * - Enable the MMU with the boot pgd
  35. * - Jump to a target into the trampoline page (remember, this is the same
  36. * physical page!)
  37. * - Now switch to the runtime pgd (same VA, and still the same physical
  38. * page!)
  39. * - Invalidate TLBs
  40. * - Set stack and vectors
  41. * - Profit! (or eret, if you only care about the code).
  42. *
  43. * As we only have four registers available to pass parameters (and we
  44. * need six), we split the init in two phases:
  45. * - Phase 1: r0 = 0, r1 = 0, r2,r3 contain the boot PGD.
  46. * Provides the basic HYP init, and enable the MMU.
  47. * - Phase 2: r0 = ToS, r1 = vectors, r2,r3 contain the runtime PGD.
  48. * Switches to the runtime PGD, set stack and vectors.
  49. */
  50. .text
  51. .pushsection .hyp.idmap.text,"ax"
  52. .align 5
  53. __kvm_hyp_init:
  54. .globl __kvm_hyp_init
  55. @ Hyp-mode exception vector
  56. W(b) .
  57. W(b) .
  58. W(b) .
  59. W(b) .
  60. W(b) .
  61. W(b) __do_hyp_init
  62. W(b) .
  63. W(b) .
  64. __do_hyp_init:
  65. cmp r0, #0 @ We have a SP?
  66. bne phase2 @ Yes, second stage init
  67. @ Set the HTTBR to point to the hypervisor PGD pointer passed
  68. mcrr p15, 4, r2, r3, c2
  69. @ Set the HTCR and VTCR to the same shareability and cacheability
  70. @ settings as the non-secure TTBCR and with T0SZ == 0.
  71. mrc p15, 4, r0, c2, c0, 2 @ HTCR
  72. ldr r2, =HTCR_MASK
  73. bic r0, r0, r2
  74. mrc p15, 0, r1, c2, c0, 2 @ TTBCR
  75. and r1, r1, #(HTCR_MASK & ~TTBCR_T0SZ)
  76. orr r0, r0, r1
  77. mcr p15, 4, r0, c2, c0, 2 @ HTCR
  78. mrc p15, 4, r1, c2, c1, 2 @ VTCR
  79. ldr r2, =VTCR_MASK
  80. bic r1, r1, r2
  81. bic r0, r0, #(~VTCR_HTCR_SH) @ clear non-reusable HTCR bits
  82. orr r1, r0, r1
  83. orr r1, r1, #(KVM_VTCR_SL0 | KVM_VTCR_T0SZ | KVM_VTCR_S)
  84. mcr p15, 4, r1, c2, c1, 2 @ VTCR
  85. @ Use the same memory attributes for hyp. accesses as the kernel
  86. @ (copy MAIRx ro HMAIRx).
  87. mrc p15, 0, r0, c10, c2, 0
  88. mcr p15, 4, r0, c10, c2, 0
  89. mrc p15, 0, r0, c10, c2, 1
  90. mcr p15, 4, r0, c10, c2, 1
  91. @ Set the HSCTLR to:
  92. @ - ARM/THUMB exceptions: Kernel config (Thumb-2 kernel)
  93. @ - Endianness: Kernel config
  94. @ - Fast Interrupt Features: Kernel config
  95. @ - Write permission implies XN: disabled
  96. @ - Instruction cache: enabled
  97. @ - Data/Unified cache: enabled
  98. @ - Memory alignment checks: enabled
  99. @ - MMU: enabled (this code must be run from an identity mapping)
  100. mrc p15, 4, r0, c1, c0, 0 @ HSCR
  101. ldr r2, =HSCTLR_MASK
  102. bic r0, r0, r2
  103. mrc p15, 0, r1, c1, c0, 0 @ SCTLR
  104. ldr r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
  105. and r1, r1, r2
  106. ARM( ldr r2, =(HSCTLR_M | HSCTLR_A) )
  107. THUMB( ldr r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE) )
  108. orr r1, r1, r2
  109. orr r0, r0, r1
  110. isb
  111. mcr p15, 4, r0, c1, c0, 0 @ HSCR
  112. @ End of init phase-1
  113. eret
  114. phase2:
  115. @ Set stack pointer
  116. mov sp, r0
  117. @ Set HVBAR to point to the HYP vectors
  118. mcr p15, 4, r1, c12, c0, 0 @ HVBAR
  119. @ Jump to the trampoline page
  120. ldr r0, =TRAMPOLINE_VA
  121. adr r1, target
  122. bfi r0, r1, #0, #PAGE_SHIFT
  123. mov pc, r0
  124. target: @ We're now in the trampoline code, switch page tables
  125. mcrr p15, 4, r2, r3, c2
  126. isb
  127. @ Invalidate the old TLBs
  128. mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
  129. dsb
  130. eret
  131. .ltorg
  132. .globl __kvm_hyp_init_end
  133. __kvm_hyp_init_end:
  134. .popsection