coproc.c 29 KB

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  1. /*
  2. * Copyright (C) 2012 - Virtual Open Systems and Columbia University
  3. * Authors: Rusty Russell <rusty@rustcorp.com.au>
  4. * Christoffer Dall <c.dall@virtualopensystems.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License, version 2, as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  18. */
  19. #include <linux/mm.h>
  20. #include <linux/kvm_host.h>
  21. #include <linux/uaccess.h>
  22. #include <asm/kvm_arm.h>
  23. #include <asm/kvm_host.h>
  24. #include <asm/kvm_emulate.h>
  25. #include <asm/kvm_coproc.h>
  26. #include <asm/cacheflush.h>
  27. #include <asm/cputype.h>
  28. #include <trace/events/kvm.h>
  29. #include <asm/vfp.h>
  30. #include "../vfp/vfpinstr.h"
  31. #include "trace.h"
  32. #include "coproc.h"
  33. /******************************************************************************
  34. * Co-processor emulation
  35. *****************************************************************************/
  36. /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
  37. static u32 cache_levels;
  38. /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
  39. #define CSSELR_MAX 12
  40. int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
  41. {
  42. kvm_inject_undefined(vcpu);
  43. return 1;
  44. }
  45. int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  46. {
  47. /*
  48. * We can get here, if the host has been built without VFPv3 support,
  49. * but the guest attempted a floating point operation.
  50. */
  51. kvm_inject_undefined(vcpu);
  52. return 1;
  53. }
  54. int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
  55. {
  56. kvm_inject_undefined(vcpu);
  57. return 1;
  58. }
  59. int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
  60. {
  61. kvm_inject_undefined(vcpu);
  62. return 1;
  63. }
  64. /* See note at ARM ARM B1.14.4 */
  65. static bool access_dcsw(struct kvm_vcpu *vcpu,
  66. const struct coproc_params *p,
  67. const struct coproc_reg *r)
  68. {
  69. unsigned long val;
  70. int cpu;
  71. if (!p->is_write)
  72. return read_from_write_only(vcpu, p);
  73. cpu = get_cpu();
  74. cpumask_setall(&vcpu->arch.require_dcache_flush);
  75. cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
  76. /* If we were already preempted, take the long way around */
  77. if (cpu != vcpu->arch.last_pcpu) {
  78. flush_cache_all();
  79. goto done;
  80. }
  81. val = *vcpu_reg(vcpu, p->Rt1);
  82. switch (p->CRm) {
  83. case 6: /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
  84. case 14: /* DCCISW */
  85. asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (val));
  86. break;
  87. case 10: /* DCCSW */
  88. asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (val));
  89. break;
  90. }
  91. done:
  92. put_cpu();
  93. return true;
  94. }
  95. /*
  96. * We could trap ID_DFR0 and tell the guest we don't support performance
  97. * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
  98. * NAKed, so it will read the PMCR anyway.
  99. *
  100. * Therefore we tell the guest we have 0 counters. Unfortunately, we
  101. * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
  102. * all PM registers, which doesn't crash the guest kernel at least.
  103. */
  104. static bool pm_fake(struct kvm_vcpu *vcpu,
  105. const struct coproc_params *p,
  106. const struct coproc_reg *r)
  107. {
  108. if (p->is_write)
  109. return ignore_write(vcpu, p);
  110. else
  111. return read_zero(vcpu, p);
  112. }
  113. #define access_pmcr pm_fake
  114. #define access_pmcntenset pm_fake
  115. #define access_pmcntenclr pm_fake
  116. #define access_pmovsr pm_fake
  117. #define access_pmselr pm_fake
  118. #define access_pmceid0 pm_fake
  119. #define access_pmceid1 pm_fake
  120. #define access_pmccntr pm_fake
  121. #define access_pmxevtyper pm_fake
  122. #define access_pmxevcntr pm_fake
  123. #define access_pmuserenr pm_fake
  124. #define access_pmintenset pm_fake
  125. #define access_pmintenclr pm_fake
  126. /* Architected CP15 registers.
  127. * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
  128. */
  129. static const struct coproc_reg cp15_regs[] = {
  130. /* CSSELR: swapped by interrupt.S. */
  131. { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
  132. NULL, reset_unknown, c0_CSSELR },
  133. /* TTBR0/TTBR1: swapped by interrupt.S. */
  134. { CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
  135. { CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
  136. /* TTBCR: swapped by interrupt.S. */
  137. { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
  138. NULL, reset_val, c2_TTBCR, 0x00000000 },
  139. /* DACR: swapped by interrupt.S. */
  140. { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
  141. NULL, reset_unknown, c3_DACR },
  142. /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
  143. { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
  144. NULL, reset_unknown, c5_DFSR },
  145. { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
  146. NULL, reset_unknown, c5_IFSR },
  147. { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
  148. NULL, reset_unknown, c5_ADFSR },
  149. { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
  150. NULL, reset_unknown, c5_AIFSR },
  151. /* DFAR/IFAR: swapped by interrupt.S. */
  152. { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
  153. NULL, reset_unknown, c6_DFAR },
  154. { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
  155. NULL, reset_unknown, c6_IFAR },
  156. /* PAR swapped by interrupt.S */
  157. { CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
  158. /*
  159. * DC{C,I,CI}SW operations:
  160. */
  161. { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
  162. { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
  163. { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
  164. /*
  165. * Dummy performance monitor implementation.
  166. */
  167. { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
  168. { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
  169. { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
  170. { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
  171. { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
  172. { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
  173. { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
  174. { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
  175. { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
  176. { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
  177. { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
  178. { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
  179. { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
  180. /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
  181. { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
  182. NULL, reset_unknown, c10_PRRR},
  183. { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
  184. NULL, reset_unknown, c10_NMRR},
  185. /* VBAR: swapped by interrupt.S. */
  186. { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
  187. NULL, reset_val, c12_VBAR, 0x00000000 },
  188. /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
  189. { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
  190. NULL, reset_val, c13_CID, 0x00000000 },
  191. { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
  192. NULL, reset_unknown, c13_TID_URW },
  193. { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
  194. NULL, reset_unknown, c13_TID_URO },
  195. { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
  196. NULL, reset_unknown, c13_TID_PRIV },
  197. /* CNTKCTL: swapped by interrupt.S. */
  198. { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
  199. NULL, reset_val, c14_CNTKCTL, 0x00000000 },
  200. };
  201. /* Target specific emulation tables */
  202. static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
  203. void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
  204. {
  205. target_tables[table->target] = table;
  206. }
  207. /* Get specific register table for this target. */
  208. static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
  209. {
  210. struct kvm_coproc_target_table *table;
  211. table = target_tables[target];
  212. *num = table->num;
  213. return table->table;
  214. }
  215. static const struct coproc_reg *find_reg(const struct coproc_params *params,
  216. const struct coproc_reg table[],
  217. unsigned int num)
  218. {
  219. unsigned int i;
  220. for (i = 0; i < num; i++) {
  221. const struct coproc_reg *r = &table[i];
  222. if (params->is_64bit != r->is_64)
  223. continue;
  224. if (params->CRn != r->CRn)
  225. continue;
  226. if (params->CRm != r->CRm)
  227. continue;
  228. if (params->Op1 != r->Op1)
  229. continue;
  230. if (params->Op2 != r->Op2)
  231. continue;
  232. return r;
  233. }
  234. return NULL;
  235. }
  236. static int emulate_cp15(struct kvm_vcpu *vcpu,
  237. const struct coproc_params *params)
  238. {
  239. size_t num;
  240. const struct coproc_reg *table, *r;
  241. trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
  242. params->CRm, params->Op2, params->is_write);
  243. table = get_target_table(vcpu->arch.target, &num);
  244. /* Search target-specific then generic table. */
  245. r = find_reg(params, table, num);
  246. if (!r)
  247. r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
  248. if (likely(r)) {
  249. /* If we don't have an accessor, we should never get here! */
  250. BUG_ON(!r->access);
  251. if (likely(r->access(vcpu, params, r))) {
  252. /* Skip instruction, since it was emulated */
  253. kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
  254. return 1;
  255. }
  256. /* If access function fails, it should complain. */
  257. } else {
  258. kvm_err("Unsupported guest CP15 access at: %08lx\n",
  259. *vcpu_pc(vcpu));
  260. print_cp_instr(params);
  261. }
  262. kvm_inject_undefined(vcpu);
  263. return 1;
  264. }
  265. /**
  266. * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
  267. * @vcpu: The VCPU pointer
  268. * @run: The kvm_run struct
  269. */
  270. int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
  271. {
  272. struct coproc_params params;
  273. params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
  274. params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
  275. params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
  276. params.is_64bit = true;
  277. params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
  278. params.Op2 = 0;
  279. params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
  280. params.CRn = 0;
  281. return emulate_cp15(vcpu, &params);
  282. }
  283. static void reset_coproc_regs(struct kvm_vcpu *vcpu,
  284. const struct coproc_reg *table, size_t num)
  285. {
  286. unsigned long i;
  287. for (i = 0; i < num; i++)
  288. if (table[i].reset)
  289. table[i].reset(vcpu, &table[i]);
  290. }
  291. /**
  292. * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
  293. * @vcpu: The VCPU pointer
  294. * @run: The kvm_run struct
  295. */
  296. int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
  297. {
  298. struct coproc_params params;
  299. params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
  300. params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
  301. params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
  302. params.is_64bit = false;
  303. params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
  304. params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
  305. params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
  306. params.Rt2 = 0;
  307. return emulate_cp15(vcpu, &params);
  308. }
  309. /******************************************************************************
  310. * Userspace API
  311. *****************************************************************************/
  312. static bool index_to_params(u64 id, struct coproc_params *params)
  313. {
  314. switch (id & KVM_REG_SIZE_MASK) {
  315. case KVM_REG_SIZE_U32:
  316. /* Any unused index bits means it's not valid. */
  317. if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
  318. | KVM_REG_ARM_COPROC_MASK
  319. | KVM_REG_ARM_32_CRN_MASK
  320. | KVM_REG_ARM_CRM_MASK
  321. | KVM_REG_ARM_OPC1_MASK
  322. | KVM_REG_ARM_32_OPC2_MASK))
  323. return false;
  324. params->is_64bit = false;
  325. params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
  326. >> KVM_REG_ARM_32_CRN_SHIFT);
  327. params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
  328. >> KVM_REG_ARM_CRM_SHIFT);
  329. params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
  330. >> KVM_REG_ARM_OPC1_SHIFT);
  331. params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
  332. >> KVM_REG_ARM_32_OPC2_SHIFT);
  333. return true;
  334. case KVM_REG_SIZE_U64:
  335. /* Any unused index bits means it's not valid. */
  336. if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
  337. | KVM_REG_ARM_COPROC_MASK
  338. | KVM_REG_ARM_CRM_MASK
  339. | KVM_REG_ARM_OPC1_MASK))
  340. return false;
  341. params->is_64bit = true;
  342. params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
  343. >> KVM_REG_ARM_CRM_SHIFT);
  344. params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
  345. >> KVM_REG_ARM_OPC1_SHIFT);
  346. params->Op2 = 0;
  347. params->CRn = 0;
  348. return true;
  349. default:
  350. return false;
  351. }
  352. }
  353. /* Decode an index value, and find the cp15 coproc_reg entry. */
  354. static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
  355. u64 id)
  356. {
  357. size_t num;
  358. const struct coproc_reg *table, *r;
  359. struct coproc_params params;
  360. /* We only do cp15 for now. */
  361. if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
  362. return NULL;
  363. if (!index_to_params(id, &params))
  364. return NULL;
  365. table = get_target_table(vcpu->arch.target, &num);
  366. r = find_reg(&params, table, num);
  367. if (!r)
  368. r = find_reg(&params, cp15_regs, ARRAY_SIZE(cp15_regs));
  369. /* Not saved in the cp15 array? */
  370. if (r && !r->reg)
  371. r = NULL;
  372. return r;
  373. }
  374. /*
  375. * These are the invariant cp15 registers: we let the guest see the host
  376. * versions of these, so they're part of the guest state.
  377. *
  378. * A future CPU may provide a mechanism to present different values to
  379. * the guest, or a future kvm may trap them.
  380. */
  381. /* Unfortunately, there's no register-argument for mrc, so generate. */
  382. #define FUNCTION_FOR32(crn, crm, op1, op2, name) \
  383. static void get_##name(struct kvm_vcpu *v, \
  384. const struct coproc_reg *r) \
  385. { \
  386. u32 val; \
  387. \
  388. asm volatile("mrc p15, " __stringify(op1) \
  389. ", %0, c" __stringify(crn) \
  390. ", c" __stringify(crm) \
  391. ", " __stringify(op2) "\n" : "=r" (val)); \
  392. ((struct coproc_reg *)r)->val = val; \
  393. }
  394. FUNCTION_FOR32(0, 0, 0, 0, MIDR)
  395. FUNCTION_FOR32(0, 0, 0, 1, CTR)
  396. FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
  397. FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
  398. FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
  399. FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
  400. FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
  401. FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
  402. FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
  403. FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
  404. FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
  405. FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
  406. FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
  407. FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
  408. FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
  409. FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
  410. FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
  411. FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
  412. FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
  413. FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
  414. FUNCTION_FOR32(0, 0, 1, 7, AIDR)
  415. /* ->val is filled in by kvm_invariant_coproc_table_init() */
  416. static struct coproc_reg invariant_cp15[] = {
  417. { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
  418. { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
  419. { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
  420. { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
  421. { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
  422. { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
  423. { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
  424. { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
  425. { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
  426. { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
  427. { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
  428. { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
  429. { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
  430. { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
  431. { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
  432. { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
  433. { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
  434. { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
  435. { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
  436. { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
  437. { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
  438. };
  439. static int reg_from_user(void *val, const void __user *uaddr, u64 id)
  440. {
  441. /* This Just Works because we are little endian. */
  442. if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
  443. return -EFAULT;
  444. return 0;
  445. }
  446. static int reg_to_user(void __user *uaddr, const void *val, u64 id)
  447. {
  448. /* This Just Works because we are little endian. */
  449. if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
  450. return -EFAULT;
  451. return 0;
  452. }
  453. static int get_invariant_cp15(u64 id, void __user *uaddr)
  454. {
  455. struct coproc_params params;
  456. const struct coproc_reg *r;
  457. if (!index_to_params(id, &params))
  458. return -ENOENT;
  459. r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
  460. if (!r)
  461. return -ENOENT;
  462. return reg_to_user(uaddr, &r->val, id);
  463. }
  464. static int set_invariant_cp15(u64 id, void __user *uaddr)
  465. {
  466. struct coproc_params params;
  467. const struct coproc_reg *r;
  468. int err;
  469. u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
  470. if (!index_to_params(id, &params))
  471. return -ENOENT;
  472. r = find_reg(&params, invariant_cp15, ARRAY_SIZE(invariant_cp15));
  473. if (!r)
  474. return -ENOENT;
  475. err = reg_from_user(&val, uaddr, id);
  476. if (err)
  477. return err;
  478. /* This is what we mean by invariant: you can't change it. */
  479. if (r->val != val)
  480. return -EINVAL;
  481. return 0;
  482. }
  483. static bool is_valid_cache(u32 val)
  484. {
  485. u32 level, ctype;
  486. if (val >= CSSELR_MAX)
  487. return -ENOENT;
  488. /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
  489. level = (val >> 1);
  490. ctype = (cache_levels >> (level * 3)) & 7;
  491. switch (ctype) {
  492. case 0: /* No cache */
  493. return false;
  494. case 1: /* Instruction cache only */
  495. return (val & 1);
  496. case 2: /* Data cache only */
  497. case 4: /* Unified cache */
  498. return !(val & 1);
  499. case 3: /* Separate instruction and data caches */
  500. return true;
  501. default: /* Reserved: we can't know instruction or data. */
  502. return false;
  503. }
  504. }
  505. /* Which cache CCSIDR represents depends on CSSELR value. */
  506. static u32 get_ccsidr(u32 csselr)
  507. {
  508. u32 ccsidr;
  509. /* Make sure noone else changes CSSELR during this! */
  510. local_irq_disable();
  511. /* Put value into CSSELR */
  512. asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
  513. isb();
  514. /* Read result out of CCSIDR */
  515. asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
  516. local_irq_enable();
  517. return ccsidr;
  518. }
  519. static int demux_c15_get(u64 id, void __user *uaddr)
  520. {
  521. u32 val;
  522. u32 __user *uval = uaddr;
  523. /* Fail if we have unknown bits set. */
  524. if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
  525. | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
  526. return -ENOENT;
  527. switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
  528. case KVM_REG_ARM_DEMUX_ID_CCSIDR:
  529. if (KVM_REG_SIZE(id) != 4)
  530. return -ENOENT;
  531. val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
  532. >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
  533. if (!is_valid_cache(val))
  534. return -ENOENT;
  535. return put_user(get_ccsidr(val), uval);
  536. default:
  537. return -ENOENT;
  538. }
  539. }
  540. static int demux_c15_set(u64 id, void __user *uaddr)
  541. {
  542. u32 val, newval;
  543. u32 __user *uval = uaddr;
  544. /* Fail if we have unknown bits set. */
  545. if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
  546. | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
  547. return -ENOENT;
  548. switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
  549. case KVM_REG_ARM_DEMUX_ID_CCSIDR:
  550. if (KVM_REG_SIZE(id) != 4)
  551. return -ENOENT;
  552. val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
  553. >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
  554. if (!is_valid_cache(val))
  555. return -ENOENT;
  556. if (get_user(newval, uval))
  557. return -EFAULT;
  558. /* This is also invariant: you can't change it. */
  559. if (newval != get_ccsidr(val))
  560. return -EINVAL;
  561. return 0;
  562. default:
  563. return -ENOENT;
  564. }
  565. }
  566. #ifdef CONFIG_VFPv3
  567. static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
  568. KVM_REG_ARM_VFP_FPSCR,
  569. KVM_REG_ARM_VFP_FPINST,
  570. KVM_REG_ARM_VFP_FPINST2,
  571. KVM_REG_ARM_VFP_MVFR0,
  572. KVM_REG_ARM_VFP_MVFR1,
  573. KVM_REG_ARM_VFP_FPSID };
  574. static unsigned int num_fp_regs(void)
  575. {
  576. if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
  577. return 32;
  578. else
  579. return 16;
  580. }
  581. static unsigned int num_vfp_regs(void)
  582. {
  583. /* Normal FP regs + control regs. */
  584. return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
  585. }
  586. static int copy_vfp_regids(u64 __user *uindices)
  587. {
  588. unsigned int i;
  589. const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
  590. const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
  591. for (i = 0; i < num_fp_regs(); i++) {
  592. if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
  593. uindices))
  594. return -EFAULT;
  595. uindices++;
  596. }
  597. for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
  598. if (put_user(u32reg | vfp_sysregs[i], uindices))
  599. return -EFAULT;
  600. uindices++;
  601. }
  602. return num_vfp_regs();
  603. }
  604. static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
  605. {
  606. u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
  607. u32 val;
  608. /* Fail if we have unknown bits set. */
  609. if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
  610. | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
  611. return -ENOENT;
  612. if (vfpid < num_fp_regs()) {
  613. if (KVM_REG_SIZE(id) != 8)
  614. return -ENOENT;
  615. return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpregs[vfpid],
  616. id);
  617. }
  618. /* FP control registers are all 32 bit. */
  619. if (KVM_REG_SIZE(id) != 4)
  620. return -ENOENT;
  621. switch (vfpid) {
  622. case KVM_REG_ARM_VFP_FPEXC:
  623. return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpexc, id);
  624. case KVM_REG_ARM_VFP_FPSCR:
  625. return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpscr, id);
  626. case KVM_REG_ARM_VFP_FPINST:
  627. return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst, id);
  628. case KVM_REG_ARM_VFP_FPINST2:
  629. return reg_to_user(uaddr, &vcpu->arch.vfp_guest.fpinst2, id);
  630. case KVM_REG_ARM_VFP_MVFR0:
  631. val = fmrx(MVFR0);
  632. return reg_to_user(uaddr, &val, id);
  633. case KVM_REG_ARM_VFP_MVFR1:
  634. val = fmrx(MVFR1);
  635. return reg_to_user(uaddr, &val, id);
  636. case KVM_REG_ARM_VFP_FPSID:
  637. val = fmrx(FPSID);
  638. return reg_to_user(uaddr, &val, id);
  639. default:
  640. return -ENOENT;
  641. }
  642. }
  643. static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
  644. {
  645. u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
  646. u32 val;
  647. /* Fail if we have unknown bits set. */
  648. if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
  649. | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
  650. return -ENOENT;
  651. if (vfpid < num_fp_regs()) {
  652. if (KVM_REG_SIZE(id) != 8)
  653. return -ENOENT;
  654. return reg_from_user(&vcpu->arch.vfp_guest.fpregs[vfpid],
  655. uaddr, id);
  656. }
  657. /* FP control registers are all 32 bit. */
  658. if (KVM_REG_SIZE(id) != 4)
  659. return -ENOENT;
  660. switch (vfpid) {
  661. case KVM_REG_ARM_VFP_FPEXC:
  662. return reg_from_user(&vcpu->arch.vfp_guest.fpexc, uaddr, id);
  663. case KVM_REG_ARM_VFP_FPSCR:
  664. return reg_from_user(&vcpu->arch.vfp_guest.fpscr, uaddr, id);
  665. case KVM_REG_ARM_VFP_FPINST:
  666. return reg_from_user(&vcpu->arch.vfp_guest.fpinst, uaddr, id);
  667. case KVM_REG_ARM_VFP_FPINST2:
  668. return reg_from_user(&vcpu->arch.vfp_guest.fpinst2, uaddr, id);
  669. /* These are invariant. */
  670. case KVM_REG_ARM_VFP_MVFR0:
  671. if (reg_from_user(&val, uaddr, id))
  672. return -EFAULT;
  673. if (val != fmrx(MVFR0))
  674. return -EINVAL;
  675. return 0;
  676. case KVM_REG_ARM_VFP_MVFR1:
  677. if (reg_from_user(&val, uaddr, id))
  678. return -EFAULT;
  679. if (val != fmrx(MVFR1))
  680. return -EINVAL;
  681. return 0;
  682. case KVM_REG_ARM_VFP_FPSID:
  683. if (reg_from_user(&val, uaddr, id))
  684. return -EFAULT;
  685. if (val != fmrx(FPSID))
  686. return -EINVAL;
  687. return 0;
  688. default:
  689. return -ENOENT;
  690. }
  691. }
  692. #else /* !CONFIG_VFPv3 */
  693. static unsigned int num_vfp_regs(void)
  694. {
  695. return 0;
  696. }
  697. static int copy_vfp_regids(u64 __user *uindices)
  698. {
  699. return 0;
  700. }
  701. static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
  702. {
  703. return -ENOENT;
  704. }
  705. static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
  706. {
  707. return -ENOENT;
  708. }
  709. #endif /* !CONFIG_VFPv3 */
  710. int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
  711. {
  712. const struct coproc_reg *r;
  713. void __user *uaddr = (void __user *)(long)reg->addr;
  714. if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
  715. return demux_c15_get(reg->id, uaddr);
  716. if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
  717. return vfp_get_reg(vcpu, reg->id, uaddr);
  718. r = index_to_coproc_reg(vcpu, reg->id);
  719. if (!r)
  720. return get_invariant_cp15(reg->id, uaddr);
  721. /* Note: copies two regs if size is 64 bit. */
  722. return reg_to_user(uaddr, &vcpu->arch.cp15[r->reg], reg->id);
  723. }
  724. int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
  725. {
  726. const struct coproc_reg *r;
  727. void __user *uaddr = (void __user *)(long)reg->addr;
  728. if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
  729. return demux_c15_set(reg->id, uaddr);
  730. if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
  731. return vfp_set_reg(vcpu, reg->id, uaddr);
  732. r = index_to_coproc_reg(vcpu, reg->id);
  733. if (!r)
  734. return set_invariant_cp15(reg->id, uaddr);
  735. /* Note: copies two regs if size is 64 bit */
  736. return reg_from_user(&vcpu->arch.cp15[r->reg], uaddr, reg->id);
  737. }
  738. static unsigned int num_demux_regs(void)
  739. {
  740. unsigned int i, count = 0;
  741. for (i = 0; i < CSSELR_MAX; i++)
  742. if (is_valid_cache(i))
  743. count++;
  744. return count;
  745. }
  746. static int write_demux_regids(u64 __user *uindices)
  747. {
  748. u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
  749. unsigned int i;
  750. val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
  751. for (i = 0; i < CSSELR_MAX; i++) {
  752. if (!is_valid_cache(i))
  753. continue;
  754. if (put_user(val | i, uindices))
  755. return -EFAULT;
  756. uindices++;
  757. }
  758. return 0;
  759. }
  760. static u64 cp15_to_index(const struct coproc_reg *reg)
  761. {
  762. u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
  763. if (reg->is_64) {
  764. val |= KVM_REG_SIZE_U64;
  765. val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
  766. val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
  767. } else {
  768. val |= KVM_REG_SIZE_U32;
  769. val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
  770. val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
  771. val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
  772. val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
  773. }
  774. return val;
  775. }
  776. static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
  777. {
  778. if (!*uind)
  779. return true;
  780. if (put_user(cp15_to_index(reg), *uind))
  781. return false;
  782. (*uind)++;
  783. return true;
  784. }
  785. /* Assumed ordered tables, see kvm_coproc_table_init. */
  786. static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
  787. {
  788. const struct coproc_reg *i1, *i2, *end1, *end2;
  789. unsigned int total = 0;
  790. size_t num;
  791. /* We check for duplicates here, to allow arch-specific overrides. */
  792. i1 = get_target_table(vcpu->arch.target, &num);
  793. end1 = i1 + num;
  794. i2 = cp15_regs;
  795. end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
  796. BUG_ON(i1 == end1 || i2 == end2);
  797. /* Walk carefully, as both tables may refer to the same register. */
  798. while (i1 || i2) {
  799. int cmp = cmp_reg(i1, i2);
  800. /* target-specific overrides generic entry. */
  801. if (cmp <= 0) {
  802. /* Ignore registers we trap but don't save. */
  803. if (i1->reg) {
  804. if (!copy_reg_to_user(i1, &uind))
  805. return -EFAULT;
  806. total++;
  807. }
  808. } else {
  809. /* Ignore registers we trap but don't save. */
  810. if (i2->reg) {
  811. if (!copy_reg_to_user(i2, &uind))
  812. return -EFAULT;
  813. total++;
  814. }
  815. }
  816. if (cmp <= 0 && ++i1 == end1)
  817. i1 = NULL;
  818. if (cmp >= 0 && ++i2 == end2)
  819. i2 = NULL;
  820. }
  821. return total;
  822. }
  823. unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
  824. {
  825. return ARRAY_SIZE(invariant_cp15)
  826. + num_demux_regs()
  827. + num_vfp_regs()
  828. + walk_cp15(vcpu, (u64 __user *)NULL);
  829. }
  830. int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
  831. {
  832. unsigned int i;
  833. int err;
  834. /* Then give them all the invariant registers' indices. */
  835. for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
  836. if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
  837. return -EFAULT;
  838. uindices++;
  839. }
  840. err = walk_cp15(vcpu, uindices);
  841. if (err < 0)
  842. return err;
  843. uindices += err;
  844. err = copy_vfp_regids(uindices);
  845. if (err < 0)
  846. return err;
  847. uindices += err;
  848. return write_demux_regids(uindices);
  849. }
  850. void kvm_coproc_table_init(void)
  851. {
  852. unsigned int i;
  853. /* Make sure tables are unique and in order. */
  854. for (i = 1; i < ARRAY_SIZE(cp15_regs); i++)
  855. BUG_ON(cmp_reg(&cp15_regs[i-1], &cp15_regs[i]) >= 0);
  856. /* We abuse the reset function to overwrite the table itself. */
  857. for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
  858. invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
  859. /*
  860. * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
  861. *
  862. * If software reads the Cache Type fields from Ctype1
  863. * upwards, once it has seen a value of 0b000, no caches
  864. * exist at further-out levels of the hierarchy. So, for
  865. * example, if Ctype3 is the first Cache Type field with a
  866. * value of 0b000, the values of Ctype4 to Ctype7 must be
  867. * ignored.
  868. */
  869. asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
  870. for (i = 0; i < 7; i++)
  871. if (((cache_levels >> (i*3)) & 7) == 0)
  872. break;
  873. /* Clear all higher bits. */
  874. cache_levels &= (1 << (i*3))-1;
  875. }
  876. /**
  877. * kvm_reset_coprocs - sets cp15 registers to reset value
  878. * @vcpu: The VCPU pointer
  879. *
  880. * This function finds the right table above and sets the registers on the
  881. * virtual CPU struct to their architecturally defined reset values.
  882. */
  883. void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
  884. {
  885. size_t num;
  886. const struct coproc_reg *table;
  887. /* Catch someone adding a register without putting in reset entry. */
  888. memset(vcpu->arch.cp15, 0x42, sizeof(vcpu->arch.cp15));
  889. /* Generic chip reset first (so target could override). */
  890. reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
  891. table = get_target_table(vcpu->arch.target, &num);
  892. reset_coproc_regs(vcpu, table, num);
  893. for (num = 1; num < NR_CP15_REGS; num++)
  894. if (vcpu->arch.cp15[num] == 0x42424242)
  895. panic("Didn't reset vcpu->arch.cp15[%zi]", num);
  896. }