edma.c 48 KB

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  1. /*
  2. * EDMA3 support for DaVinci
  3. *
  4. * Copyright (C) 2006-2009 Texas Instruments.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/err.h>
  21. #include <linux/kernel.h>
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/io.h>
  27. #include <linux/slab.h>
  28. #include <linux/edma.h>
  29. #include <linux/of_address.h>
  30. #include <linux/of_device.h>
  31. #include <linux/of_dma.h>
  32. #include <linux/of_irq.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/platform_data/edma.h>
  35. /* Offsets matching "struct edmacc_param" */
  36. #define PARM_OPT 0x00
  37. #define PARM_SRC 0x04
  38. #define PARM_A_B_CNT 0x08
  39. #define PARM_DST 0x0c
  40. #define PARM_SRC_DST_BIDX 0x10
  41. #define PARM_LINK_BCNTRLD 0x14
  42. #define PARM_SRC_DST_CIDX 0x18
  43. #define PARM_CCNT 0x1c
  44. #define PARM_SIZE 0x20
  45. /* Offsets for EDMA CC global channel registers and their shadows */
  46. #define SH_ER 0x00 /* 64 bits */
  47. #define SH_ECR 0x08 /* 64 bits */
  48. #define SH_ESR 0x10 /* 64 bits */
  49. #define SH_CER 0x18 /* 64 bits */
  50. #define SH_EER 0x20 /* 64 bits */
  51. #define SH_EECR 0x28 /* 64 bits */
  52. #define SH_EESR 0x30 /* 64 bits */
  53. #define SH_SER 0x38 /* 64 bits */
  54. #define SH_SECR 0x40 /* 64 bits */
  55. #define SH_IER 0x50 /* 64 bits */
  56. #define SH_IECR 0x58 /* 64 bits */
  57. #define SH_IESR 0x60 /* 64 bits */
  58. #define SH_IPR 0x68 /* 64 bits */
  59. #define SH_ICR 0x70 /* 64 bits */
  60. #define SH_IEVAL 0x78
  61. #define SH_QER 0x80
  62. #define SH_QEER 0x84
  63. #define SH_QEECR 0x88
  64. #define SH_QEESR 0x8c
  65. #define SH_QSER 0x90
  66. #define SH_QSECR 0x94
  67. #define SH_SIZE 0x200
  68. /* Offsets for EDMA CC global registers */
  69. #define EDMA_REV 0x0000
  70. #define EDMA_CCCFG 0x0004
  71. #define EDMA_QCHMAP 0x0200 /* 8 registers */
  72. #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
  73. #define EDMA_QDMAQNUM 0x0260
  74. #define EDMA_QUETCMAP 0x0280
  75. #define EDMA_QUEPRI 0x0284
  76. #define EDMA_EMR 0x0300 /* 64 bits */
  77. #define EDMA_EMCR 0x0308 /* 64 bits */
  78. #define EDMA_QEMR 0x0310
  79. #define EDMA_QEMCR 0x0314
  80. #define EDMA_CCERR 0x0318
  81. #define EDMA_CCERRCLR 0x031c
  82. #define EDMA_EEVAL 0x0320
  83. #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
  84. #define EDMA_QRAE 0x0380 /* 4 registers */
  85. #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
  86. #define EDMA_QSTAT 0x0600 /* 2 registers */
  87. #define EDMA_QWMTHRA 0x0620
  88. #define EDMA_QWMTHRB 0x0624
  89. #define EDMA_CCSTAT 0x0640
  90. #define EDMA_M 0x1000 /* global channel registers */
  91. #define EDMA_ECR 0x1008
  92. #define EDMA_ECRH 0x100C
  93. #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */
  94. #define EDMA_PARM 0x4000 /* 128 param entries */
  95. #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
  96. #define EDMA_DCHMAP 0x0100 /* 64 registers */
  97. #define CHMAP_EXIST BIT(24)
  98. #define EDMA_MAX_DMACH 64
  99. #define EDMA_MAX_PARAMENTRY 512
  100. /*****************************************************************************/
  101. static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
  102. static inline unsigned int edma_read(unsigned ctlr, int offset)
  103. {
  104. return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
  105. }
  106. static inline void edma_write(unsigned ctlr, int offset, int val)
  107. {
  108. __raw_writel(val, edmacc_regs_base[ctlr] + offset);
  109. }
  110. static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
  111. unsigned or)
  112. {
  113. unsigned val = edma_read(ctlr, offset);
  114. val &= and;
  115. val |= or;
  116. edma_write(ctlr, offset, val);
  117. }
  118. static inline void edma_and(unsigned ctlr, int offset, unsigned and)
  119. {
  120. unsigned val = edma_read(ctlr, offset);
  121. val &= and;
  122. edma_write(ctlr, offset, val);
  123. }
  124. static inline void edma_or(unsigned ctlr, int offset, unsigned or)
  125. {
  126. unsigned val = edma_read(ctlr, offset);
  127. val |= or;
  128. edma_write(ctlr, offset, val);
  129. }
  130. static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
  131. {
  132. return edma_read(ctlr, offset + (i << 2));
  133. }
  134. static inline void edma_write_array(unsigned ctlr, int offset, int i,
  135. unsigned val)
  136. {
  137. edma_write(ctlr, offset + (i << 2), val);
  138. }
  139. static inline void edma_modify_array(unsigned ctlr, int offset, int i,
  140. unsigned and, unsigned or)
  141. {
  142. edma_modify(ctlr, offset + (i << 2), and, or);
  143. }
  144. static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
  145. {
  146. edma_or(ctlr, offset + (i << 2), or);
  147. }
  148. static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
  149. unsigned or)
  150. {
  151. edma_or(ctlr, offset + ((i*2 + j) << 2), or);
  152. }
  153. static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
  154. unsigned val)
  155. {
  156. edma_write(ctlr, offset + ((i*2 + j) << 2), val);
  157. }
  158. static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
  159. {
  160. return edma_read(ctlr, EDMA_SHADOW0 + offset);
  161. }
  162. static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
  163. int i)
  164. {
  165. return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
  166. }
  167. static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
  168. {
  169. edma_write(ctlr, EDMA_SHADOW0 + offset, val);
  170. }
  171. static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
  172. unsigned val)
  173. {
  174. edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
  175. }
  176. static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
  177. int param_no)
  178. {
  179. return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
  180. }
  181. static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
  182. unsigned val)
  183. {
  184. edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
  185. }
  186. static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
  187. unsigned and, unsigned or)
  188. {
  189. edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
  190. }
  191. static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
  192. unsigned and)
  193. {
  194. edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
  195. }
  196. static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
  197. unsigned or)
  198. {
  199. edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
  200. }
  201. static inline void set_bits(int offset, int len, unsigned long *p)
  202. {
  203. for (; len > 0; len--)
  204. set_bit(offset + (len - 1), p);
  205. }
  206. static inline void clear_bits(int offset, int len, unsigned long *p)
  207. {
  208. for (; len > 0; len--)
  209. clear_bit(offset + (len - 1), p);
  210. }
  211. /*****************************************************************************/
  212. /* actual number of DMA channels and slots on this silicon */
  213. struct edma {
  214. /* how many dma resources of each type */
  215. unsigned num_channels;
  216. unsigned num_region;
  217. unsigned num_slots;
  218. unsigned num_tc;
  219. unsigned num_cc;
  220. enum dma_event_q default_queue;
  221. /* list of channels with no even trigger; terminated by "-1" */
  222. const s8 *noevent;
  223. /* The edma_inuse bit for each PaRAM slot is clear unless the
  224. * channel is in use ... by ARM or DSP, for QDMA, or whatever.
  225. */
  226. DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
  227. /* The edma_unused bit for each channel is clear unless
  228. * it is not being used on this platform. It uses a bit
  229. * of SOC-specific initialization code.
  230. */
  231. DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
  232. unsigned irq_res_start;
  233. unsigned irq_res_end;
  234. struct dma_interrupt_data {
  235. void (*callback)(unsigned channel, unsigned short ch_status,
  236. void *data);
  237. void *data;
  238. } intr_data[EDMA_MAX_DMACH];
  239. };
  240. static struct edma *edma_cc[EDMA_MAX_CC];
  241. static int arch_num_cc;
  242. /* dummy param set used to (re)initialize parameter RAM slots */
  243. static const struct edmacc_param dummy_paramset = {
  244. .link_bcntrld = 0xffff,
  245. .ccnt = 1,
  246. };
  247. /*****************************************************************************/
  248. static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
  249. enum dma_event_q queue_no)
  250. {
  251. int bit = (ch_no & 0x7) * 4;
  252. /* default to low priority queue */
  253. if (queue_no == EVENTQ_DEFAULT)
  254. queue_no = edma_cc[ctlr]->default_queue;
  255. queue_no &= 7;
  256. edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
  257. ~(0x7 << bit), queue_no << bit);
  258. }
  259. static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
  260. {
  261. int bit = queue_no * 4;
  262. edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
  263. }
  264. static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
  265. int priority)
  266. {
  267. int bit = queue_no * 4;
  268. edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
  269. ((priority & 0x7) << bit));
  270. }
  271. /**
  272. * map_dmach_param - Maps channel number to param entry number
  273. *
  274. * This maps the dma channel number to param entry numberter. In
  275. * other words using the DMA channel mapping registers a param entry
  276. * can be mapped to any channel
  277. *
  278. * Callers are responsible for ensuring the channel mapping logic is
  279. * included in that particular EDMA variant (Eg : dm646x)
  280. *
  281. */
  282. static void __init map_dmach_param(unsigned ctlr)
  283. {
  284. int i;
  285. for (i = 0; i < EDMA_MAX_DMACH; i++)
  286. edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
  287. }
  288. static inline void
  289. setup_dma_interrupt(unsigned lch,
  290. void (*callback)(unsigned channel, u16 ch_status, void *data),
  291. void *data)
  292. {
  293. unsigned ctlr;
  294. ctlr = EDMA_CTLR(lch);
  295. lch = EDMA_CHAN_SLOT(lch);
  296. if (!callback)
  297. edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
  298. BIT(lch & 0x1f));
  299. edma_cc[ctlr]->intr_data[lch].callback = callback;
  300. edma_cc[ctlr]->intr_data[lch].data = data;
  301. if (callback) {
  302. edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
  303. BIT(lch & 0x1f));
  304. edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
  305. BIT(lch & 0x1f));
  306. }
  307. }
  308. static int irq2ctlr(int irq)
  309. {
  310. if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end)
  311. return 0;
  312. else if (irq >= edma_cc[1]->irq_res_start &&
  313. irq <= edma_cc[1]->irq_res_end)
  314. return 1;
  315. return -1;
  316. }
  317. /******************************************************************************
  318. *
  319. * DMA interrupt handler
  320. *
  321. *****************************************************************************/
  322. static irqreturn_t dma_irq_handler(int irq, void *data)
  323. {
  324. int ctlr;
  325. u32 sh_ier;
  326. u32 sh_ipr;
  327. u32 bank;
  328. ctlr = irq2ctlr(irq);
  329. if (ctlr < 0)
  330. return IRQ_NONE;
  331. dev_dbg(data, "dma_irq_handler\n");
  332. sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0);
  333. if (!sh_ipr) {
  334. sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1);
  335. if (!sh_ipr)
  336. return IRQ_NONE;
  337. sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1);
  338. bank = 1;
  339. } else {
  340. sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0);
  341. bank = 0;
  342. }
  343. do {
  344. u32 slot;
  345. u32 channel;
  346. dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr);
  347. slot = __ffs(sh_ipr);
  348. sh_ipr &= ~(BIT(slot));
  349. if (sh_ier & BIT(slot)) {
  350. channel = (bank << 5) | slot;
  351. /* Clear the corresponding IPR bits */
  352. edma_shadow0_write_array(ctlr, SH_ICR, bank,
  353. BIT(slot));
  354. if (edma_cc[ctlr]->intr_data[channel].callback)
  355. edma_cc[ctlr]->intr_data[channel].callback(
  356. channel, DMA_COMPLETE,
  357. edma_cc[ctlr]->intr_data[channel].data);
  358. }
  359. } while (sh_ipr);
  360. edma_shadow0_write(ctlr, SH_IEVAL, 1);
  361. return IRQ_HANDLED;
  362. }
  363. /******************************************************************************
  364. *
  365. * DMA error interrupt handler
  366. *
  367. *****************************************************************************/
  368. static irqreturn_t dma_ccerr_handler(int irq, void *data)
  369. {
  370. int i;
  371. int ctlr;
  372. unsigned int cnt = 0;
  373. ctlr = irq2ctlr(irq);
  374. if (ctlr < 0)
  375. return IRQ_NONE;
  376. dev_dbg(data, "dma_ccerr_handler\n");
  377. if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
  378. (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
  379. (edma_read(ctlr, EDMA_QEMR) == 0) &&
  380. (edma_read(ctlr, EDMA_CCERR) == 0))
  381. return IRQ_NONE;
  382. while (1) {
  383. int j = -1;
  384. if (edma_read_array(ctlr, EDMA_EMR, 0))
  385. j = 0;
  386. else if (edma_read_array(ctlr, EDMA_EMR, 1))
  387. j = 1;
  388. if (j >= 0) {
  389. dev_dbg(data, "EMR%d %08x\n", j,
  390. edma_read_array(ctlr, EDMA_EMR, j));
  391. for (i = 0; i < 32; i++) {
  392. int k = (j << 5) + i;
  393. if (edma_read_array(ctlr, EDMA_EMR, j) &
  394. BIT(i)) {
  395. /* Clear the corresponding EMR bits */
  396. edma_write_array(ctlr, EDMA_EMCR, j,
  397. BIT(i));
  398. /* Clear any SER */
  399. edma_shadow0_write_array(ctlr, SH_SECR,
  400. j, BIT(i));
  401. if (edma_cc[ctlr]->intr_data[k].
  402. callback) {
  403. edma_cc[ctlr]->intr_data[k].
  404. callback(k,
  405. DMA_CC_ERROR,
  406. edma_cc[ctlr]->intr_data
  407. [k].data);
  408. }
  409. }
  410. }
  411. } else if (edma_read(ctlr, EDMA_QEMR)) {
  412. dev_dbg(data, "QEMR %02x\n",
  413. edma_read(ctlr, EDMA_QEMR));
  414. for (i = 0; i < 8; i++) {
  415. if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) {
  416. /* Clear the corresponding IPR bits */
  417. edma_write(ctlr, EDMA_QEMCR, BIT(i));
  418. edma_shadow0_write(ctlr, SH_QSECR,
  419. BIT(i));
  420. /* NOTE: not reported!! */
  421. }
  422. }
  423. } else if (edma_read(ctlr, EDMA_CCERR)) {
  424. dev_dbg(data, "CCERR %08x\n",
  425. edma_read(ctlr, EDMA_CCERR));
  426. /* FIXME: CCERR.BIT(16) ignored! much better
  427. * to just write CCERRCLR with CCERR value...
  428. */
  429. for (i = 0; i < 8; i++) {
  430. if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) {
  431. /* Clear the corresponding IPR bits */
  432. edma_write(ctlr, EDMA_CCERRCLR, BIT(i));
  433. /* NOTE: not reported!! */
  434. }
  435. }
  436. }
  437. if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
  438. (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
  439. (edma_read(ctlr, EDMA_QEMR) == 0) &&
  440. (edma_read(ctlr, EDMA_CCERR) == 0))
  441. break;
  442. cnt++;
  443. if (cnt > 10)
  444. break;
  445. }
  446. edma_write(ctlr, EDMA_EEVAL, 1);
  447. return IRQ_HANDLED;
  448. }
  449. static int reserve_contiguous_slots(int ctlr, unsigned int id,
  450. unsigned int num_slots,
  451. unsigned int start_slot)
  452. {
  453. int i, j;
  454. unsigned int count = num_slots;
  455. int stop_slot = start_slot;
  456. DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY);
  457. for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) {
  458. j = EDMA_CHAN_SLOT(i);
  459. if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) {
  460. /* Record our current beginning slot */
  461. if (count == num_slots)
  462. stop_slot = i;
  463. count--;
  464. set_bit(j, tmp_inuse);
  465. if (count == 0)
  466. break;
  467. } else {
  468. clear_bit(j, tmp_inuse);
  469. if (id == EDMA_CONT_PARAMS_FIXED_EXACT) {
  470. stop_slot = i;
  471. break;
  472. } else {
  473. count = num_slots;
  474. }
  475. }
  476. }
  477. /*
  478. * We have to clear any bits that we set
  479. * if we run out parameter RAM slots, i.e we do find a set
  480. * of contiguous parameter RAM slots but do not find the exact number
  481. * requested as we may reach the total number of parameter RAM slots
  482. */
  483. if (i == edma_cc[ctlr]->num_slots)
  484. stop_slot = i;
  485. j = start_slot;
  486. for_each_set_bit_from(j, tmp_inuse, stop_slot)
  487. clear_bit(j, edma_cc[ctlr]->edma_inuse);
  488. if (count)
  489. return -EBUSY;
  490. for (j = i - num_slots + 1; j <= i; ++j)
  491. memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j),
  492. &dummy_paramset, PARM_SIZE);
  493. return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
  494. }
  495. static int prepare_unused_channel_list(struct device *dev, void *data)
  496. {
  497. struct platform_device *pdev = to_platform_device(dev);
  498. int i, ctlr;
  499. for (i = 0; i < pdev->num_resources; i++) {
  500. if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
  501. (int)pdev->resource[i].start >= 0) {
  502. ctlr = EDMA_CTLR(pdev->resource[i].start);
  503. clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
  504. edma_cc[ctlr]->edma_unused);
  505. }
  506. }
  507. return 0;
  508. }
  509. /*-----------------------------------------------------------------------*/
  510. static bool unused_chan_list_done;
  511. /* Resource alloc/free: dma channels, parameter RAM slots */
  512. /**
  513. * edma_alloc_channel - allocate DMA channel and paired parameter RAM
  514. * @channel: specific channel to allocate; negative for "any unmapped channel"
  515. * @callback: optional; to be issued on DMA completion or errors
  516. * @data: passed to callback
  517. * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
  518. * Controller (TC) executes requests using this channel. Use
  519. * EVENTQ_DEFAULT unless you really need a high priority queue.
  520. *
  521. * This allocates a DMA channel and its associated parameter RAM slot.
  522. * The parameter RAM is initialized to hold a dummy transfer.
  523. *
  524. * Normal use is to pass a specific channel number as @channel, to make
  525. * use of hardware events mapped to that channel. When the channel will
  526. * be used only for software triggering or event chaining, channels not
  527. * mapped to hardware events (or mapped to unused events) are preferable.
  528. *
  529. * DMA transfers start from a channel using edma_start(), or by
  530. * chaining. When the transfer described in that channel's parameter RAM
  531. * slot completes, that slot's data may be reloaded through a link.
  532. *
  533. * DMA errors are only reported to the @callback associated with the
  534. * channel driving that transfer, but transfer completion callbacks can
  535. * be sent to another channel under control of the TCC field in
  536. * the option word of the transfer's parameter RAM set. Drivers must not
  537. * use DMA transfer completion callbacks for channels they did not allocate.
  538. * (The same applies to TCC codes used in transfer chaining.)
  539. *
  540. * Returns the number of the channel, else negative errno.
  541. */
  542. int edma_alloc_channel(int channel,
  543. void (*callback)(unsigned channel, u16 ch_status, void *data),
  544. void *data,
  545. enum dma_event_q eventq_no)
  546. {
  547. unsigned i, done = 0, ctlr = 0;
  548. int ret = 0;
  549. if (!unused_chan_list_done) {
  550. /*
  551. * Scan all the platform devices to find out the EDMA channels
  552. * used and clear them in the unused list, making the rest
  553. * available for ARM usage.
  554. */
  555. ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
  556. prepare_unused_channel_list);
  557. if (ret < 0)
  558. return ret;
  559. unused_chan_list_done = true;
  560. }
  561. if (channel >= 0) {
  562. ctlr = EDMA_CTLR(channel);
  563. channel = EDMA_CHAN_SLOT(channel);
  564. }
  565. if (channel < 0) {
  566. for (i = 0; i < arch_num_cc; i++) {
  567. channel = 0;
  568. for (;;) {
  569. channel = find_next_bit(edma_cc[i]->edma_unused,
  570. edma_cc[i]->num_channels,
  571. channel);
  572. if (channel == edma_cc[i]->num_channels)
  573. break;
  574. if (!test_and_set_bit(channel,
  575. edma_cc[i]->edma_inuse)) {
  576. done = 1;
  577. ctlr = i;
  578. break;
  579. }
  580. channel++;
  581. }
  582. if (done)
  583. break;
  584. }
  585. if (!done)
  586. return -ENOMEM;
  587. } else if (channel >= edma_cc[ctlr]->num_channels) {
  588. return -EINVAL;
  589. } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) {
  590. return -EBUSY;
  591. }
  592. /* ensure access through shadow region 0 */
  593. edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
  594. /* ensure no events are pending */
  595. edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
  596. memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
  597. &dummy_paramset, PARM_SIZE);
  598. if (callback)
  599. setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
  600. callback, data);
  601. map_dmach_queue(ctlr, channel, eventq_no);
  602. return EDMA_CTLR_CHAN(ctlr, channel);
  603. }
  604. EXPORT_SYMBOL(edma_alloc_channel);
  605. /**
  606. * edma_free_channel - deallocate DMA channel
  607. * @channel: dma channel returned from edma_alloc_channel()
  608. *
  609. * This deallocates the DMA channel and associated parameter RAM slot
  610. * allocated by edma_alloc_channel().
  611. *
  612. * Callers are responsible for ensuring the channel is inactive, and
  613. * will not be reactivated by linking, chaining, or software calls to
  614. * edma_start().
  615. */
  616. void edma_free_channel(unsigned channel)
  617. {
  618. unsigned ctlr;
  619. ctlr = EDMA_CTLR(channel);
  620. channel = EDMA_CHAN_SLOT(channel);
  621. if (channel >= edma_cc[ctlr]->num_channels)
  622. return;
  623. setup_dma_interrupt(channel, NULL, NULL);
  624. /* REVISIT should probably take out of shadow region 0 */
  625. memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
  626. &dummy_paramset, PARM_SIZE);
  627. clear_bit(channel, edma_cc[ctlr]->edma_inuse);
  628. }
  629. EXPORT_SYMBOL(edma_free_channel);
  630. /**
  631. * edma_alloc_slot - allocate DMA parameter RAM
  632. * @slot: specific slot to allocate; negative for "any unused slot"
  633. *
  634. * This allocates a parameter RAM slot, initializing it to hold a
  635. * dummy transfer. Slots allocated using this routine have not been
  636. * mapped to a hardware DMA channel, and will normally be used by
  637. * linking to them from a slot associated with a DMA channel.
  638. *
  639. * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
  640. * slots may be allocated on behalf of DSP firmware.
  641. *
  642. * Returns the number of the slot, else negative errno.
  643. */
  644. int edma_alloc_slot(unsigned ctlr, int slot)
  645. {
  646. if (!edma_cc[ctlr])
  647. return -EINVAL;
  648. if (slot >= 0)
  649. slot = EDMA_CHAN_SLOT(slot);
  650. if (slot < 0) {
  651. slot = edma_cc[ctlr]->num_channels;
  652. for (;;) {
  653. slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse,
  654. edma_cc[ctlr]->num_slots, slot);
  655. if (slot == edma_cc[ctlr]->num_slots)
  656. return -ENOMEM;
  657. if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse))
  658. break;
  659. }
  660. } else if (slot < edma_cc[ctlr]->num_channels ||
  661. slot >= edma_cc[ctlr]->num_slots) {
  662. return -EINVAL;
  663. } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) {
  664. return -EBUSY;
  665. }
  666. memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
  667. &dummy_paramset, PARM_SIZE);
  668. return EDMA_CTLR_CHAN(ctlr, slot);
  669. }
  670. EXPORT_SYMBOL(edma_alloc_slot);
  671. /**
  672. * edma_free_slot - deallocate DMA parameter RAM
  673. * @slot: parameter RAM slot returned from edma_alloc_slot()
  674. *
  675. * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
  676. * Callers are responsible for ensuring the slot is inactive, and will
  677. * not be activated.
  678. */
  679. void edma_free_slot(unsigned slot)
  680. {
  681. unsigned ctlr;
  682. ctlr = EDMA_CTLR(slot);
  683. slot = EDMA_CHAN_SLOT(slot);
  684. if (slot < edma_cc[ctlr]->num_channels ||
  685. slot >= edma_cc[ctlr]->num_slots)
  686. return;
  687. memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
  688. &dummy_paramset, PARM_SIZE);
  689. clear_bit(slot, edma_cc[ctlr]->edma_inuse);
  690. }
  691. EXPORT_SYMBOL(edma_free_slot);
  692. /**
  693. * edma_alloc_cont_slots- alloc contiguous parameter RAM slots
  694. * The API will return the starting point of a set of
  695. * contiguous parameter RAM slots that have been requested
  696. *
  697. * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT
  698. * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
  699. * @count: number of contiguous Paramter RAM slots
  700. * @slot - the start value of Parameter RAM slot that should be passed if id
  701. * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT
  702. *
  703. * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of
  704. * contiguous Parameter RAM slots from parameter RAM 64 in the case of
  705. * DaVinci SOCs and 32 in the case of DA8xx SOCs.
  706. *
  707. * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a
  708. * set of contiguous parameter RAM slots from the "slot" that is passed as an
  709. * argument to the API.
  710. *
  711. * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries
  712. * starts looking for a set of contiguous parameter RAMs from the "slot"
  713. * that is passed as an argument to the API. On failure the API will try to
  714. * find a set of contiguous Parameter RAM slots from the remaining Parameter
  715. * RAM slots
  716. */
  717. int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count)
  718. {
  719. /*
  720. * The start slot requested should be greater than
  721. * the number of channels and lesser than the total number
  722. * of slots
  723. */
  724. if ((id != EDMA_CONT_PARAMS_ANY) &&
  725. (slot < edma_cc[ctlr]->num_channels ||
  726. slot >= edma_cc[ctlr]->num_slots))
  727. return -EINVAL;
  728. /*
  729. * The number of parameter RAM slots requested cannot be less than 1
  730. * and cannot be more than the number of slots minus the number of
  731. * channels
  732. */
  733. if (count < 1 || count >
  734. (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels))
  735. return -EINVAL;
  736. switch (id) {
  737. case EDMA_CONT_PARAMS_ANY:
  738. return reserve_contiguous_slots(ctlr, id, count,
  739. edma_cc[ctlr]->num_channels);
  740. case EDMA_CONT_PARAMS_FIXED_EXACT:
  741. case EDMA_CONT_PARAMS_FIXED_NOT_EXACT:
  742. return reserve_contiguous_slots(ctlr, id, count, slot);
  743. default:
  744. return -EINVAL;
  745. }
  746. }
  747. EXPORT_SYMBOL(edma_alloc_cont_slots);
  748. /**
  749. * edma_free_cont_slots - deallocate DMA parameter RAM slots
  750. * @slot: first parameter RAM of a set of parameter RAM slots to be freed
  751. * @count: the number of contiguous parameter RAM slots to be freed
  752. *
  753. * This deallocates the parameter RAM slots allocated by
  754. * edma_alloc_cont_slots.
  755. * Callers/applications need to keep track of sets of contiguous
  756. * parameter RAM slots that have been allocated using the edma_alloc_cont_slots
  757. * API.
  758. * Callers are responsible for ensuring the slots are inactive, and will
  759. * not be activated.
  760. */
  761. int edma_free_cont_slots(unsigned slot, int count)
  762. {
  763. unsigned ctlr, slot_to_free;
  764. int i;
  765. ctlr = EDMA_CTLR(slot);
  766. slot = EDMA_CHAN_SLOT(slot);
  767. if (slot < edma_cc[ctlr]->num_channels ||
  768. slot >= edma_cc[ctlr]->num_slots ||
  769. count < 1)
  770. return -EINVAL;
  771. for (i = slot; i < slot + count; ++i) {
  772. ctlr = EDMA_CTLR(i);
  773. slot_to_free = EDMA_CHAN_SLOT(i);
  774. memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free),
  775. &dummy_paramset, PARM_SIZE);
  776. clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse);
  777. }
  778. return 0;
  779. }
  780. EXPORT_SYMBOL(edma_free_cont_slots);
  781. /*-----------------------------------------------------------------------*/
  782. /* Parameter RAM operations (i) -- read/write partial slots */
  783. /**
  784. * edma_set_src - set initial DMA source address in parameter RAM slot
  785. * @slot: parameter RAM slot being configured
  786. * @src_port: physical address of source (memory, controller FIFO, etc)
  787. * @addressMode: INCR, except in very rare cases
  788. * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
  789. * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
  790. *
  791. * Note that the source address is modified during the DMA transfer
  792. * according to edma_set_src_index().
  793. */
  794. void edma_set_src(unsigned slot, dma_addr_t src_port,
  795. enum address_mode mode, enum fifo_width width)
  796. {
  797. unsigned ctlr;
  798. ctlr = EDMA_CTLR(slot);
  799. slot = EDMA_CHAN_SLOT(slot);
  800. if (slot < edma_cc[ctlr]->num_slots) {
  801. unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
  802. if (mode) {
  803. /* set SAM and program FWID */
  804. i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
  805. } else {
  806. /* clear SAM */
  807. i &= ~SAM;
  808. }
  809. edma_parm_write(ctlr, PARM_OPT, slot, i);
  810. /* set the source port address
  811. in source register of param structure */
  812. edma_parm_write(ctlr, PARM_SRC, slot, src_port);
  813. }
  814. }
  815. EXPORT_SYMBOL(edma_set_src);
  816. /**
  817. * edma_set_dest - set initial DMA destination address in parameter RAM slot
  818. * @slot: parameter RAM slot being configured
  819. * @dest_port: physical address of destination (memory, controller FIFO, etc)
  820. * @addressMode: INCR, except in very rare cases
  821. * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
  822. * width to use when addressing the fifo (e.g. W8BIT, W32BIT)
  823. *
  824. * Note that the destination address is modified during the DMA transfer
  825. * according to edma_set_dest_index().
  826. */
  827. void edma_set_dest(unsigned slot, dma_addr_t dest_port,
  828. enum address_mode mode, enum fifo_width width)
  829. {
  830. unsigned ctlr;
  831. ctlr = EDMA_CTLR(slot);
  832. slot = EDMA_CHAN_SLOT(slot);
  833. if (slot < edma_cc[ctlr]->num_slots) {
  834. unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
  835. if (mode) {
  836. /* set DAM and program FWID */
  837. i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
  838. } else {
  839. /* clear DAM */
  840. i &= ~DAM;
  841. }
  842. edma_parm_write(ctlr, PARM_OPT, slot, i);
  843. /* set the destination port address
  844. in dest register of param structure */
  845. edma_parm_write(ctlr, PARM_DST, slot, dest_port);
  846. }
  847. }
  848. EXPORT_SYMBOL(edma_set_dest);
  849. /**
  850. * edma_get_position - returns the current transfer points
  851. * @slot: parameter RAM slot being examined
  852. * @src: pointer to source port position
  853. * @dst: pointer to destination port position
  854. *
  855. * Returns current source and destination addresses for a particular
  856. * parameter RAM slot. Its channel should not be active when this is called.
  857. */
  858. void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
  859. {
  860. struct edmacc_param temp;
  861. unsigned ctlr;
  862. ctlr = EDMA_CTLR(slot);
  863. slot = EDMA_CHAN_SLOT(slot);
  864. edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
  865. if (src != NULL)
  866. *src = temp.src;
  867. if (dst != NULL)
  868. *dst = temp.dst;
  869. }
  870. EXPORT_SYMBOL(edma_get_position);
  871. /**
  872. * edma_set_src_index - configure DMA source address indexing
  873. * @slot: parameter RAM slot being configured
  874. * @src_bidx: byte offset between source arrays in a frame
  875. * @src_cidx: byte offset between source frames in a block
  876. *
  877. * Offsets are specified to support either contiguous or discontiguous
  878. * memory transfers, or repeated access to a hardware register, as needed.
  879. * When accessing hardware registers, both offsets are normally zero.
  880. */
  881. void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
  882. {
  883. unsigned ctlr;
  884. ctlr = EDMA_CTLR(slot);
  885. slot = EDMA_CHAN_SLOT(slot);
  886. if (slot < edma_cc[ctlr]->num_slots) {
  887. edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
  888. 0xffff0000, src_bidx);
  889. edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
  890. 0xffff0000, src_cidx);
  891. }
  892. }
  893. EXPORT_SYMBOL(edma_set_src_index);
  894. /**
  895. * edma_set_dest_index - configure DMA destination address indexing
  896. * @slot: parameter RAM slot being configured
  897. * @dest_bidx: byte offset between destination arrays in a frame
  898. * @dest_cidx: byte offset between destination frames in a block
  899. *
  900. * Offsets are specified to support either contiguous or discontiguous
  901. * memory transfers, or repeated access to a hardware register, as needed.
  902. * When accessing hardware registers, both offsets are normally zero.
  903. */
  904. void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
  905. {
  906. unsigned ctlr;
  907. ctlr = EDMA_CTLR(slot);
  908. slot = EDMA_CHAN_SLOT(slot);
  909. if (slot < edma_cc[ctlr]->num_slots) {
  910. edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
  911. 0x0000ffff, dest_bidx << 16);
  912. edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
  913. 0x0000ffff, dest_cidx << 16);
  914. }
  915. }
  916. EXPORT_SYMBOL(edma_set_dest_index);
  917. /**
  918. * edma_set_transfer_params - configure DMA transfer parameters
  919. * @slot: parameter RAM slot being configured
  920. * @acnt: how many bytes per array (at least one)
  921. * @bcnt: how many arrays per frame (at least one)
  922. * @ccnt: how many frames per block (at least one)
  923. * @bcnt_rld: used only for A-Synchronized transfers; this specifies
  924. * the value to reload into bcnt when it decrements to zero
  925. * @sync_mode: ASYNC or ABSYNC
  926. *
  927. * See the EDMA3 documentation to understand how to configure and link
  928. * transfers using the fields in PaRAM slots. If you are not doing it
  929. * all at once with edma_write_slot(), you will use this routine
  930. * plus two calls each for source and destination, setting the initial
  931. * address and saying how to index that address.
  932. *
  933. * An example of an A-Synchronized transfer is a serial link using a
  934. * single word shift register. In that case, @acnt would be equal to
  935. * that word size; the serial controller issues a DMA synchronization
  936. * event to transfer each word, and memory access by the DMA transfer
  937. * controller will be word-at-a-time.
  938. *
  939. * An example of an AB-Synchronized transfer is a device using a FIFO.
  940. * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
  941. * The controller with the FIFO issues DMA synchronization events when
  942. * the FIFO threshold is reached, and the DMA transfer controller will
  943. * transfer one frame to (or from) the FIFO. It will probably use
  944. * efficient burst modes to access memory.
  945. */
  946. void edma_set_transfer_params(unsigned slot,
  947. u16 acnt, u16 bcnt, u16 ccnt,
  948. u16 bcnt_rld, enum sync_dimension sync_mode)
  949. {
  950. unsigned ctlr;
  951. ctlr = EDMA_CTLR(slot);
  952. slot = EDMA_CHAN_SLOT(slot);
  953. if (slot < edma_cc[ctlr]->num_slots) {
  954. edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
  955. 0x0000ffff, bcnt_rld << 16);
  956. if (sync_mode == ASYNC)
  957. edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
  958. else
  959. edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
  960. /* Set the acount, bcount, ccount registers */
  961. edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
  962. edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
  963. }
  964. }
  965. EXPORT_SYMBOL(edma_set_transfer_params);
  966. /**
  967. * edma_link - link one parameter RAM slot to another
  968. * @from: parameter RAM slot originating the link
  969. * @to: parameter RAM slot which is the link target
  970. *
  971. * The originating slot should not be part of any active DMA transfer.
  972. */
  973. void edma_link(unsigned from, unsigned to)
  974. {
  975. unsigned ctlr_from, ctlr_to;
  976. ctlr_from = EDMA_CTLR(from);
  977. from = EDMA_CHAN_SLOT(from);
  978. ctlr_to = EDMA_CTLR(to);
  979. to = EDMA_CHAN_SLOT(to);
  980. if (from >= edma_cc[ctlr_from]->num_slots)
  981. return;
  982. if (to >= edma_cc[ctlr_to]->num_slots)
  983. return;
  984. edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
  985. PARM_OFFSET(to));
  986. }
  987. EXPORT_SYMBOL(edma_link);
  988. /**
  989. * edma_unlink - cut link from one parameter RAM slot
  990. * @from: parameter RAM slot originating the link
  991. *
  992. * The originating slot should not be part of any active DMA transfer.
  993. * Its link is set to 0xffff.
  994. */
  995. void edma_unlink(unsigned from)
  996. {
  997. unsigned ctlr;
  998. ctlr = EDMA_CTLR(from);
  999. from = EDMA_CHAN_SLOT(from);
  1000. if (from >= edma_cc[ctlr]->num_slots)
  1001. return;
  1002. edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
  1003. }
  1004. EXPORT_SYMBOL(edma_unlink);
  1005. /*-----------------------------------------------------------------------*/
  1006. /* Parameter RAM operations (ii) -- read/write whole parameter sets */
  1007. /**
  1008. * edma_write_slot - write parameter RAM data for slot
  1009. * @slot: number of parameter RAM slot being modified
  1010. * @param: data to be written into parameter RAM slot
  1011. *
  1012. * Use this to assign all parameters of a transfer at once. This
  1013. * allows more efficient setup of transfers than issuing multiple
  1014. * calls to set up those parameters in small pieces, and provides
  1015. * complete control over all transfer options.
  1016. */
  1017. void edma_write_slot(unsigned slot, const struct edmacc_param *param)
  1018. {
  1019. unsigned ctlr;
  1020. ctlr = EDMA_CTLR(slot);
  1021. slot = EDMA_CHAN_SLOT(slot);
  1022. if (slot >= edma_cc[ctlr]->num_slots)
  1023. return;
  1024. memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
  1025. PARM_SIZE);
  1026. }
  1027. EXPORT_SYMBOL(edma_write_slot);
  1028. /**
  1029. * edma_read_slot - read parameter RAM data from slot
  1030. * @slot: number of parameter RAM slot being copied
  1031. * @param: where to store copy of parameter RAM data
  1032. *
  1033. * Use this to read data from a parameter RAM slot, perhaps to
  1034. * save them as a template for later reuse.
  1035. */
  1036. void edma_read_slot(unsigned slot, struct edmacc_param *param)
  1037. {
  1038. unsigned ctlr;
  1039. ctlr = EDMA_CTLR(slot);
  1040. slot = EDMA_CHAN_SLOT(slot);
  1041. if (slot >= edma_cc[ctlr]->num_slots)
  1042. return;
  1043. memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
  1044. PARM_SIZE);
  1045. }
  1046. EXPORT_SYMBOL(edma_read_slot);
  1047. /*-----------------------------------------------------------------------*/
  1048. /* Various EDMA channel control operations */
  1049. /**
  1050. * edma_pause - pause dma on a channel
  1051. * @channel: on which edma_start() has been called
  1052. *
  1053. * This temporarily disables EDMA hardware events on the specified channel,
  1054. * preventing them from triggering new transfers on its behalf
  1055. */
  1056. void edma_pause(unsigned channel)
  1057. {
  1058. unsigned ctlr;
  1059. ctlr = EDMA_CTLR(channel);
  1060. channel = EDMA_CHAN_SLOT(channel);
  1061. if (channel < edma_cc[ctlr]->num_channels) {
  1062. unsigned int mask = BIT(channel & 0x1f);
  1063. edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
  1064. }
  1065. }
  1066. EXPORT_SYMBOL(edma_pause);
  1067. /**
  1068. * edma_resume - resumes dma on a paused channel
  1069. * @channel: on which edma_pause() has been called
  1070. *
  1071. * This re-enables EDMA hardware events on the specified channel.
  1072. */
  1073. void edma_resume(unsigned channel)
  1074. {
  1075. unsigned ctlr;
  1076. ctlr = EDMA_CTLR(channel);
  1077. channel = EDMA_CHAN_SLOT(channel);
  1078. if (channel < edma_cc[ctlr]->num_channels) {
  1079. unsigned int mask = BIT(channel & 0x1f);
  1080. edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
  1081. }
  1082. }
  1083. EXPORT_SYMBOL(edma_resume);
  1084. /**
  1085. * edma_start - start dma on a channel
  1086. * @channel: channel being activated
  1087. *
  1088. * Channels with event associations will be triggered by their hardware
  1089. * events, and channels without such associations will be triggered by
  1090. * software. (At this writing there is no interface for using software
  1091. * triggers except with channels that don't support hardware triggers.)
  1092. *
  1093. * Returns zero on success, else negative errno.
  1094. */
  1095. int edma_start(unsigned channel)
  1096. {
  1097. unsigned ctlr;
  1098. ctlr = EDMA_CTLR(channel);
  1099. channel = EDMA_CHAN_SLOT(channel);
  1100. if (channel < edma_cc[ctlr]->num_channels) {
  1101. int j = channel >> 5;
  1102. unsigned int mask = BIT(channel & 0x1f);
  1103. /* EDMA channels without event association */
  1104. if (test_bit(channel, edma_cc[ctlr]->edma_unused)) {
  1105. pr_debug("EDMA: ESR%d %08x\n", j,
  1106. edma_shadow0_read_array(ctlr, SH_ESR, j));
  1107. edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
  1108. return 0;
  1109. }
  1110. /* EDMA channel with event association */
  1111. pr_debug("EDMA: ER%d %08x\n", j,
  1112. edma_shadow0_read_array(ctlr, SH_ER, j));
  1113. /* Clear any pending event or error */
  1114. edma_write_array(ctlr, EDMA_ECR, j, mask);
  1115. edma_write_array(ctlr, EDMA_EMCR, j, mask);
  1116. /* Clear any SER */
  1117. edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
  1118. edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
  1119. pr_debug("EDMA: EER%d %08x\n", j,
  1120. edma_shadow0_read_array(ctlr, SH_EER, j));
  1121. return 0;
  1122. }
  1123. return -EINVAL;
  1124. }
  1125. EXPORT_SYMBOL(edma_start);
  1126. /**
  1127. * edma_stop - stops dma on the channel passed
  1128. * @channel: channel being deactivated
  1129. *
  1130. * When @lch is a channel, any active transfer is paused and
  1131. * all pending hardware events are cleared. The current transfer
  1132. * may not be resumed, and the channel's Parameter RAM should be
  1133. * reinitialized before being reused.
  1134. */
  1135. void edma_stop(unsigned channel)
  1136. {
  1137. unsigned ctlr;
  1138. ctlr = EDMA_CTLR(channel);
  1139. channel = EDMA_CHAN_SLOT(channel);
  1140. if (channel < edma_cc[ctlr]->num_channels) {
  1141. int j = channel >> 5;
  1142. unsigned int mask = BIT(channel & 0x1f);
  1143. edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
  1144. edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
  1145. edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
  1146. edma_write_array(ctlr, EDMA_EMCR, j, mask);
  1147. pr_debug("EDMA: EER%d %08x\n", j,
  1148. edma_shadow0_read_array(ctlr, SH_EER, j));
  1149. /* REVISIT: consider guarding against inappropriate event
  1150. * chaining by overwriting with dummy_paramset.
  1151. */
  1152. }
  1153. }
  1154. EXPORT_SYMBOL(edma_stop);
  1155. /******************************************************************************
  1156. *
  1157. * It cleans ParamEntry qand bring back EDMA to initial state if media has
  1158. * been removed before EDMA has finished.It is usedful for removable media.
  1159. * Arguments:
  1160. * ch_no - channel no
  1161. *
  1162. * Return: zero on success, or corresponding error no on failure
  1163. *
  1164. * FIXME this should not be needed ... edma_stop() should suffice.
  1165. *
  1166. *****************************************************************************/
  1167. void edma_clean_channel(unsigned channel)
  1168. {
  1169. unsigned ctlr;
  1170. ctlr = EDMA_CTLR(channel);
  1171. channel = EDMA_CHAN_SLOT(channel);
  1172. if (channel < edma_cc[ctlr]->num_channels) {
  1173. int j = (channel >> 5);
  1174. unsigned int mask = BIT(channel & 0x1f);
  1175. pr_debug("EDMA: EMR%d %08x\n", j,
  1176. edma_read_array(ctlr, EDMA_EMR, j));
  1177. edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
  1178. /* Clear the corresponding EMR bits */
  1179. edma_write_array(ctlr, EDMA_EMCR, j, mask);
  1180. /* Clear any SER */
  1181. edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
  1182. edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
  1183. }
  1184. }
  1185. EXPORT_SYMBOL(edma_clean_channel);
  1186. /*
  1187. * edma_clear_event - clear an outstanding event on the DMA channel
  1188. * Arguments:
  1189. * channel - channel number
  1190. */
  1191. void edma_clear_event(unsigned channel)
  1192. {
  1193. unsigned ctlr;
  1194. ctlr = EDMA_CTLR(channel);
  1195. channel = EDMA_CHAN_SLOT(channel);
  1196. if (channel >= edma_cc[ctlr]->num_channels)
  1197. return;
  1198. if (channel < 32)
  1199. edma_write(ctlr, EDMA_ECR, BIT(channel));
  1200. else
  1201. edma_write(ctlr, EDMA_ECRH, BIT(channel - 32));
  1202. }
  1203. EXPORT_SYMBOL(edma_clear_event);
  1204. #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
  1205. static int edma_of_read_u32_to_s16_array(const struct device_node *np,
  1206. const char *propname, s16 *out_values,
  1207. size_t sz)
  1208. {
  1209. int ret;
  1210. ret = of_property_read_u16_array(np, propname, out_values, sz);
  1211. if (ret)
  1212. return ret;
  1213. /* Terminate it */
  1214. *out_values++ = -1;
  1215. *out_values++ = -1;
  1216. return 0;
  1217. }
  1218. static int edma_xbar_event_map(struct device *dev,
  1219. struct device_node *node,
  1220. struct edma_soc_info *pdata, int len)
  1221. {
  1222. int ret, i;
  1223. struct resource res;
  1224. void __iomem *xbar;
  1225. const s16 (*xbar_chans)[2];
  1226. u32 shift, offset, mux;
  1227. xbar_chans = devm_kzalloc(dev,
  1228. len/sizeof(s16) + 2*sizeof(s16),
  1229. GFP_KERNEL);
  1230. if (!xbar_chans)
  1231. return -ENOMEM;
  1232. ret = of_address_to_resource(node, 1, &res);
  1233. if (ret)
  1234. return -EIO;
  1235. xbar = devm_ioremap(dev, res.start, resource_size(&res));
  1236. if (!xbar)
  1237. return -ENOMEM;
  1238. ret = edma_of_read_u32_to_s16_array(node,
  1239. "ti,edma-xbar-event-map",
  1240. (s16 *)xbar_chans,
  1241. len/sizeof(u32));
  1242. if (ret)
  1243. return -EIO;
  1244. for (i = 0; xbar_chans[i][0] != -1; i++) {
  1245. shift = (xbar_chans[i][1] & 0x03) << 3;
  1246. offset = xbar_chans[i][1] & 0xfffffffc;
  1247. mux = readl(xbar + offset);
  1248. mux &= ~(0xff << shift);
  1249. mux |= xbar_chans[i][0] << shift;
  1250. writel(mux, (xbar + offset));
  1251. }
  1252. pdata->xbar_chans = xbar_chans;
  1253. return 0;
  1254. }
  1255. static int edma_of_parse_dt(struct device *dev,
  1256. struct device_node *node,
  1257. struct edma_soc_info *pdata)
  1258. {
  1259. int ret = 0, i;
  1260. u32 value;
  1261. struct property *prop;
  1262. size_t sz;
  1263. struct edma_rsv_info *rsv_info;
  1264. s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
  1265. memset(pdata, 0, sizeof(struct edma_soc_info));
  1266. ret = of_property_read_u32(node, "dma-channels", &value);
  1267. if (ret < 0)
  1268. return ret;
  1269. pdata->n_channel = value;
  1270. ret = of_property_read_u32(node, "ti,edma-regions", &value);
  1271. if (ret < 0)
  1272. return ret;
  1273. pdata->n_region = value;
  1274. ret = of_property_read_u32(node, "ti,edma-slots", &value);
  1275. if (ret < 0)
  1276. return ret;
  1277. pdata->n_slot = value;
  1278. pdata->n_cc = 1;
  1279. rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
  1280. if (!rsv_info)
  1281. return -ENOMEM;
  1282. pdata->rsv = rsv_info;
  1283. queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
  1284. if (!queue_tc_map)
  1285. return -ENOMEM;
  1286. for (i = 0; i < 3; i++) {
  1287. queue_tc_map[i][0] = i;
  1288. queue_tc_map[i][1] = i;
  1289. }
  1290. queue_tc_map[i][0] = -1;
  1291. queue_tc_map[i][1] = -1;
  1292. pdata->queue_tc_mapping = queue_tc_map;
  1293. queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
  1294. if (!queue_priority_map)
  1295. return -ENOMEM;
  1296. for (i = 0; i < 3; i++) {
  1297. queue_priority_map[i][0] = i;
  1298. queue_priority_map[i][1] = i;
  1299. }
  1300. queue_priority_map[i][0] = -1;
  1301. queue_priority_map[i][1] = -1;
  1302. pdata->queue_priority_mapping = queue_priority_map;
  1303. pdata->default_queue = 0;
  1304. prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
  1305. if (prop)
  1306. ret = edma_xbar_event_map(dev, node, pdata, sz);
  1307. return ret;
  1308. }
  1309. static struct of_dma_filter_info edma_filter_info = {
  1310. .filter_fn = edma_filter_fn,
  1311. };
  1312. static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
  1313. struct device_node *node)
  1314. {
  1315. struct edma_soc_info *info;
  1316. int ret;
  1317. info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
  1318. if (!info)
  1319. return ERR_PTR(-ENOMEM);
  1320. ret = edma_of_parse_dt(dev, node, info);
  1321. if (ret)
  1322. return ERR_PTR(ret);
  1323. dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
  1324. of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
  1325. &edma_filter_info);
  1326. return info;
  1327. }
  1328. #else
  1329. static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
  1330. struct device_node *node)
  1331. {
  1332. return ERR_PTR(-ENOSYS);
  1333. }
  1334. #endif
  1335. static int edma_probe(struct platform_device *pdev)
  1336. {
  1337. struct edma_soc_info **info = pdev->dev.platform_data;
  1338. struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL};
  1339. s8 (*queue_priority_mapping)[2];
  1340. s8 (*queue_tc_mapping)[2];
  1341. int i, j, off, ln, found = 0;
  1342. int status = -1;
  1343. const s16 (*rsv_chans)[2];
  1344. const s16 (*rsv_slots)[2];
  1345. const s16 (*xbar_chans)[2];
  1346. int irq[EDMA_MAX_CC] = {0, 0};
  1347. int err_irq[EDMA_MAX_CC] = {0, 0};
  1348. struct resource *r[EDMA_MAX_CC] = {NULL};
  1349. struct resource res[EDMA_MAX_CC];
  1350. char res_name[10];
  1351. char irq_name[10];
  1352. struct device_node *node = pdev->dev.of_node;
  1353. struct device *dev = &pdev->dev;
  1354. int ret;
  1355. if (node) {
  1356. /* Check if this is a second instance registered */
  1357. if (arch_num_cc) {
  1358. dev_err(dev, "only one EDMA instance is supported via DT\n");
  1359. return -ENODEV;
  1360. }
  1361. ninfo[0] = edma_setup_info_from_dt(dev, node);
  1362. if (IS_ERR(ninfo[0])) {
  1363. dev_err(dev, "failed to get DT data\n");
  1364. return PTR_ERR(ninfo[0]);
  1365. }
  1366. info = ninfo;
  1367. }
  1368. if (!info)
  1369. return -ENODEV;
  1370. pm_runtime_enable(dev);
  1371. ret = pm_runtime_get_sync(dev);
  1372. if (ret < 0) {
  1373. dev_err(dev, "pm_runtime_get_sync() failed\n");
  1374. return ret;
  1375. }
  1376. for (j = 0; j < EDMA_MAX_CC; j++) {
  1377. if (!info[j]) {
  1378. if (!found)
  1379. return -ENODEV;
  1380. break;
  1381. }
  1382. if (node) {
  1383. ret = of_address_to_resource(node, j, &res[j]);
  1384. if (!ret)
  1385. r[j] = &res[j];
  1386. } else {
  1387. sprintf(res_name, "edma_cc%d", j);
  1388. r[j] = platform_get_resource_byname(pdev,
  1389. IORESOURCE_MEM,
  1390. res_name);
  1391. }
  1392. if (!r[j]) {
  1393. if (found)
  1394. break;
  1395. else
  1396. return -ENODEV;
  1397. } else {
  1398. found = 1;
  1399. }
  1400. edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
  1401. if (IS_ERR(edmacc_regs_base[j]))
  1402. return PTR_ERR(edmacc_regs_base[j]);
  1403. edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
  1404. GFP_KERNEL);
  1405. if (!edma_cc[j])
  1406. return -ENOMEM;
  1407. edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
  1408. EDMA_MAX_DMACH);
  1409. edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
  1410. EDMA_MAX_PARAMENTRY);
  1411. edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
  1412. EDMA_MAX_CC);
  1413. edma_cc[j]->default_queue = info[j]->default_queue;
  1414. dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
  1415. edmacc_regs_base[j]);
  1416. for (i = 0; i < edma_cc[j]->num_slots; i++)
  1417. memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
  1418. &dummy_paramset, PARM_SIZE);
  1419. /* Mark all channels as unused */
  1420. memset(edma_cc[j]->edma_unused, 0xff,
  1421. sizeof(edma_cc[j]->edma_unused));
  1422. if (info[j]->rsv) {
  1423. /* Clear the reserved channels in unused list */
  1424. rsv_chans = info[j]->rsv->rsv_chans;
  1425. if (rsv_chans) {
  1426. for (i = 0; rsv_chans[i][0] != -1; i++) {
  1427. off = rsv_chans[i][0];
  1428. ln = rsv_chans[i][1];
  1429. clear_bits(off, ln,
  1430. edma_cc[j]->edma_unused);
  1431. }
  1432. }
  1433. /* Set the reserved slots in inuse list */
  1434. rsv_slots = info[j]->rsv->rsv_slots;
  1435. if (rsv_slots) {
  1436. for (i = 0; rsv_slots[i][0] != -1; i++) {
  1437. off = rsv_slots[i][0];
  1438. ln = rsv_slots[i][1];
  1439. set_bits(off, ln,
  1440. edma_cc[j]->edma_inuse);
  1441. }
  1442. }
  1443. }
  1444. /* Clear the xbar mapped channels in unused list */
  1445. xbar_chans = info[j]->xbar_chans;
  1446. if (xbar_chans) {
  1447. for (i = 0; xbar_chans[i][1] != -1; i++) {
  1448. off = xbar_chans[i][1];
  1449. clear_bits(off, 1,
  1450. edma_cc[j]->edma_unused);
  1451. }
  1452. }
  1453. if (node) {
  1454. irq[j] = irq_of_parse_and_map(node, 0);
  1455. } else {
  1456. sprintf(irq_name, "edma%d", j);
  1457. irq[j] = platform_get_irq_byname(pdev, irq_name);
  1458. }
  1459. edma_cc[j]->irq_res_start = irq[j];
  1460. status = devm_request_irq(&pdev->dev, irq[j],
  1461. dma_irq_handler, 0, "edma",
  1462. &pdev->dev);
  1463. if (status < 0) {
  1464. dev_dbg(&pdev->dev,
  1465. "devm_request_irq %d failed --> %d\n",
  1466. irq[j], status);
  1467. return status;
  1468. }
  1469. if (node) {
  1470. err_irq[j] = irq_of_parse_and_map(node, 2);
  1471. } else {
  1472. sprintf(irq_name, "edma%d_err", j);
  1473. err_irq[j] = platform_get_irq_byname(pdev, irq_name);
  1474. }
  1475. edma_cc[j]->irq_res_end = err_irq[j];
  1476. status = devm_request_irq(&pdev->dev, err_irq[j],
  1477. dma_ccerr_handler, 0,
  1478. "edma_error", &pdev->dev);
  1479. if (status < 0) {
  1480. dev_dbg(&pdev->dev,
  1481. "devm_request_irq %d failed --> %d\n",
  1482. err_irq[j], status);
  1483. return status;
  1484. }
  1485. for (i = 0; i < edma_cc[j]->num_channels; i++)
  1486. map_dmach_queue(j, i, info[j]->default_queue);
  1487. queue_tc_mapping = info[j]->queue_tc_mapping;
  1488. queue_priority_mapping = info[j]->queue_priority_mapping;
  1489. /* Event queue to TC mapping */
  1490. for (i = 0; queue_tc_mapping[i][0] != -1; i++)
  1491. map_queue_tc(j, queue_tc_mapping[i][0],
  1492. queue_tc_mapping[i][1]);
  1493. /* Event queue priority mapping */
  1494. for (i = 0; queue_priority_mapping[i][0] != -1; i++)
  1495. assign_priority_to_queue(j,
  1496. queue_priority_mapping[i][0],
  1497. queue_priority_mapping[i][1]);
  1498. /* Map the channel to param entry if channel mapping logic
  1499. * exist
  1500. */
  1501. if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
  1502. map_dmach_param(j);
  1503. for (i = 0; i < info[j]->n_region; i++) {
  1504. edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
  1505. edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
  1506. edma_write_array(j, EDMA_QRAE, i, 0x0);
  1507. }
  1508. arch_num_cc++;
  1509. }
  1510. return 0;
  1511. }
  1512. static const struct of_device_id edma_of_ids[] = {
  1513. { .compatible = "ti,edma3", },
  1514. {}
  1515. };
  1516. static struct platform_driver edma_driver = {
  1517. .driver = {
  1518. .name = "edma",
  1519. .of_match_table = edma_of_ids,
  1520. },
  1521. .probe = edma_probe,
  1522. };
  1523. static int __init edma_init(void)
  1524. {
  1525. return platform_driver_probe(&edma_driver, edma_probe);
  1526. }
  1527. arch_initcall(edma_init);