tegra30-beaver.dts 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436
  1. /dts-v1/;
  2. #include "tegra30.dtsi"
  3. / {
  4. model = "NVIDIA Tegra30 Beaver evaluation board";
  5. compatible = "nvidia,beaver", "nvidia,tegra30";
  6. memory {
  7. reg = <0x80000000 0x7ff00000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. sdmmc1_clk_pz0 {
  14. nvidia,pins = "sdmmc1_clk_pz0";
  15. nvidia,function = "sdmmc1";
  16. nvidia,pull = <0>;
  17. nvidia,tristate = <0>;
  18. };
  19. sdmmc1_cmd_pz1 {
  20. nvidia,pins = "sdmmc1_cmd_pz1",
  21. "sdmmc1_dat0_py7",
  22. "sdmmc1_dat1_py6",
  23. "sdmmc1_dat2_py5",
  24. "sdmmc1_dat3_py4";
  25. nvidia,function = "sdmmc1";
  26. nvidia,pull = <2>;
  27. nvidia,tristate = <0>;
  28. };
  29. sdmmc3_clk_pa6 {
  30. nvidia,pins = "sdmmc3_clk_pa6";
  31. nvidia,function = "sdmmc3";
  32. nvidia,pull = <0>;
  33. nvidia,tristate = <0>;
  34. };
  35. sdmmc3_cmd_pa7 {
  36. nvidia,pins = "sdmmc3_cmd_pa7",
  37. "sdmmc3_dat0_pb7",
  38. "sdmmc3_dat1_pb6",
  39. "sdmmc3_dat2_pb5",
  40. "sdmmc3_dat3_pb4";
  41. nvidia,function = "sdmmc3";
  42. nvidia,pull = <2>;
  43. nvidia,tristate = <0>;
  44. };
  45. sdmmc4_clk_pcc4 {
  46. nvidia,pins = "sdmmc4_clk_pcc4",
  47. "sdmmc4_rst_n_pcc3";
  48. nvidia,function = "sdmmc4";
  49. nvidia,pull = <0>;
  50. nvidia,tristate = <0>;
  51. };
  52. sdmmc4_dat0_paa0 {
  53. nvidia,pins = "sdmmc4_dat0_paa0",
  54. "sdmmc4_dat1_paa1",
  55. "sdmmc4_dat2_paa2",
  56. "sdmmc4_dat3_paa3",
  57. "sdmmc4_dat4_paa4",
  58. "sdmmc4_dat5_paa5",
  59. "sdmmc4_dat6_paa6",
  60. "sdmmc4_dat7_paa7";
  61. nvidia,function = "sdmmc4";
  62. nvidia,pull = <2>;
  63. nvidia,tristate = <0>;
  64. };
  65. dap2_fs_pa2 {
  66. nvidia,pins = "dap2_fs_pa2",
  67. "dap2_sclk_pa3",
  68. "dap2_din_pa4",
  69. "dap2_dout_pa5";
  70. nvidia,function = "i2s1";
  71. nvidia,pull = <0>;
  72. nvidia,tristate = <0>;
  73. };
  74. sdio3 {
  75. nvidia,pins = "drive_sdio3";
  76. nvidia,high-speed-mode = <0>;
  77. nvidia,schmitt = <0>;
  78. nvidia,pull-down-strength = <46>;
  79. nvidia,pull-up-strength = <42>;
  80. nvidia,slew-rate-rising = <1>;
  81. nvidia,slew-rate-falling = <1>;
  82. };
  83. };
  84. };
  85. serial@70006000 {
  86. status = "okay";
  87. };
  88. i2c@7000c000 {
  89. status = "okay";
  90. clock-frequency = <100000>;
  91. };
  92. i2c@7000c400 {
  93. status = "okay";
  94. clock-frequency = <100000>;
  95. };
  96. i2c@7000c500 {
  97. status = "okay";
  98. clock-frequency = <100000>;
  99. };
  100. i2c@7000c700 {
  101. status = "okay";
  102. clock-frequency = <100000>;
  103. };
  104. i2c@7000d000 {
  105. status = "okay";
  106. clock-frequency = <100000>;
  107. rt5640: rt5640 {
  108. compatible = "realtek,rt5640";
  109. reg = <0x1c>;
  110. interrupt-parent = <&gpio>;
  111. interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
  112. realtek,ldo1-en-gpios =
  113. <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
  114. };
  115. tps62361 {
  116. compatible = "ti,tps62361";
  117. reg = <0x60>;
  118. regulator-name = "tps62361-vout";
  119. regulator-min-microvolt = <500000>;
  120. regulator-max-microvolt = <1500000>;
  121. regulator-boot-on;
  122. regulator-always-on;
  123. ti,vsel0-state-high;
  124. ti,vsel1-state-high;
  125. };
  126. pmic: tps65911@2d {
  127. compatible = "ti,tps65911";
  128. reg = <0x2d>;
  129. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  130. #interrupt-cells = <2>;
  131. interrupt-controller;
  132. ti,system-power-controller;
  133. #gpio-cells = <2>;
  134. gpio-controller;
  135. vcc1-supply = <&vdd_5v_in_reg>;
  136. vcc2-supply = <&vdd_5v_in_reg>;
  137. vcc3-supply = <&vio_reg>;
  138. vcc4-supply = <&vdd_5v_in_reg>;
  139. vcc5-supply = <&vdd_5v_in_reg>;
  140. vcc6-supply = <&vdd2_reg>;
  141. vcc7-supply = <&vdd_5v_in_reg>;
  142. vccio-supply = <&vdd_5v_in_reg>;
  143. regulators {
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. vdd1_reg: vdd1 {
  147. regulator-name = "vddio_ddr_1v2";
  148. regulator-min-microvolt = <1200000>;
  149. regulator-max-microvolt = <1200000>;
  150. regulator-always-on;
  151. };
  152. vdd2_reg: vdd2 {
  153. regulator-name = "vdd_1v5_gen";
  154. regulator-min-microvolt = <1500000>;
  155. regulator-max-microvolt = <1500000>;
  156. regulator-always-on;
  157. };
  158. vddctrl_reg: vddctrl {
  159. regulator-name = "vdd_cpu,vdd_sys";
  160. regulator-min-microvolt = <1000000>;
  161. regulator-max-microvolt = <1000000>;
  162. regulator-always-on;
  163. };
  164. vio_reg: vio {
  165. regulator-name = "vdd_1v8_gen";
  166. regulator-min-microvolt = <1800000>;
  167. regulator-max-microvolt = <1800000>;
  168. regulator-always-on;
  169. };
  170. ldo1_reg: ldo1 {
  171. regulator-name = "vdd_pexa,vdd_pexb";
  172. regulator-min-microvolt = <1050000>;
  173. regulator-max-microvolt = <1050000>;
  174. };
  175. ldo2_reg: ldo2 {
  176. regulator-name = "vdd_sata,avdd_plle";
  177. regulator-min-microvolt = <1050000>;
  178. regulator-max-microvolt = <1050000>;
  179. };
  180. /* LDO3 is not connected to anything */
  181. ldo4_reg: ldo4 {
  182. regulator-name = "vdd_rtc";
  183. regulator-min-microvolt = <1200000>;
  184. regulator-max-microvolt = <1200000>;
  185. regulator-always-on;
  186. };
  187. ldo5_reg: ldo5 {
  188. regulator-name = "vddio_sdmmc,avdd_vdac";
  189. regulator-min-microvolt = <3300000>;
  190. regulator-max-microvolt = <3300000>;
  191. regulator-always-on;
  192. };
  193. ldo6_reg: ldo6 {
  194. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  195. regulator-min-microvolt = <1200000>;
  196. regulator-max-microvolt = <1200000>;
  197. };
  198. ldo7_reg: ldo7 {
  199. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  200. regulator-min-microvolt = <1200000>;
  201. regulator-max-microvolt = <1200000>;
  202. regulator-always-on;
  203. };
  204. ldo8_reg: ldo8 {
  205. regulator-name = "vdd_ddr_hs";
  206. regulator-min-microvolt = <1000000>;
  207. regulator-max-microvolt = <1000000>;
  208. regulator-always-on;
  209. };
  210. };
  211. };
  212. };
  213. spi@7000da00 {
  214. status = "okay";
  215. spi-max-frequency = <25000000>;
  216. spi-flash@1 {
  217. compatible = "winbond,w25q32";
  218. reg = <1>;
  219. spi-max-frequency = <20000000>;
  220. };
  221. };
  222. ahub {
  223. i2s@70080400 {
  224. status = "okay";
  225. };
  226. };
  227. pmc {
  228. status = "okay";
  229. nvidia,invert-interrupt;
  230. nvidia,suspend-mode = <2>;
  231. nvidia,cpu-pwr-good-time = <2000>;
  232. nvidia,cpu-pwr-off-time = <200>;
  233. nvidia,core-pwr-good-time = <3845 3845>;
  234. nvidia,core-pwr-off-time = <0>;
  235. nvidia,core-power-req-active-high;
  236. nvidia,sys-clock-req-active-high;
  237. };
  238. sdhci@78000000 {
  239. status = "okay";
  240. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  241. wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  242. power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
  243. bus-width = <4>;
  244. };
  245. sdhci@78000600 {
  246. status = "okay";
  247. bus-width = <8>;
  248. non-removable;
  249. };
  250. clocks {
  251. compatible = "simple-bus";
  252. #address-cells = <1>;
  253. #size-cells = <0>;
  254. clk32k_in: clock {
  255. compatible = "fixed-clock";
  256. reg=<0>;
  257. #clock-cells = <0>;
  258. clock-frequency = <32768>;
  259. };
  260. };
  261. regulators {
  262. compatible = "simple-bus";
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. vdd_5v_in_reg: regulator@0 {
  266. compatible = "regulator-fixed";
  267. reg = <0>;
  268. regulator-name = "vdd_5v_in";
  269. regulator-min-microvolt = <5000000>;
  270. regulator-max-microvolt = <5000000>;
  271. regulator-always-on;
  272. };
  273. chargepump_5v_reg: regulator@1 {
  274. compatible = "regulator-fixed";
  275. reg = <1>;
  276. regulator-name = "chargepump_5v";
  277. regulator-min-microvolt = <5000000>;
  278. regulator-max-microvolt = <5000000>;
  279. regulator-boot-on;
  280. regulator-always-on;
  281. enable-active-high;
  282. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  283. };
  284. ddr_reg: regulator@2 {
  285. compatible = "regulator-fixed";
  286. reg = <2>;
  287. regulator-name = "vdd_ddr";
  288. regulator-min-microvolt = <1500000>;
  289. regulator-max-microvolt = <1500000>;
  290. regulator-always-on;
  291. regulator-boot-on;
  292. enable-active-high;
  293. gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
  294. vin-supply = <&vdd_5v_in_reg>;
  295. };
  296. vdd_5v_sata_reg: regulator@3 {
  297. compatible = "regulator-fixed";
  298. reg = <3>;
  299. regulator-name = "vdd_5v_sata";
  300. regulator-min-microvolt = <5000000>;
  301. regulator-max-microvolt = <5000000>;
  302. regulator-always-on;
  303. regulator-boot-on;
  304. enable-active-high;
  305. gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
  306. vin-supply = <&vdd_5v_in_reg>;
  307. };
  308. usb1_vbus_reg: regulator@4 {
  309. compatible = "regulator-fixed";
  310. reg = <4>;
  311. regulator-name = "usb1_vbus";
  312. regulator-min-microvolt = <5000000>;
  313. regulator-max-microvolt = <5000000>;
  314. enable-active-high;
  315. gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
  316. gpio-open-drain;
  317. vin-supply = <&vdd_5v_in_reg>;
  318. };
  319. usb3_vbus_reg: regulator@5 {
  320. compatible = "regulator-fixed";
  321. reg = <5>;
  322. regulator-name = "usb3_vbus";
  323. regulator-min-microvolt = <5000000>;
  324. regulator-max-microvolt = <5000000>;
  325. enable-active-high;
  326. gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
  327. gpio-open-drain;
  328. vin-supply = <&vdd_5v_in_reg>;
  329. };
  330. sys_3v3_reg: regulator@6 {
  331. compatible = "regulator-fixed";
  332. reg = <6>;
  333. regulator-name = "sys_3v3,vdd_3v3_alw";
  334. regulator-min-microvolt = <3300000>;
  335. regulator-max-microvolt = <3300000>;
  336. regulator-always-on;
  337. regulator-boot-on;
  338. enable-active-high;
  339. gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
  340. vin-supply = <&vdd_5v_in_reg>;
  341. };
  342. sys_3v3_pexs_reg: regulator@7 {
  343. compatible = "regulator-fixed";
  344. reg = <7>;
  345. regulator-name = "sys_3v3_pexs";
  346. regulator-min-microvolt = <3300000>;
  347. regulator-max-microvolt = <3300000>;
  348. regulator-always-on;
  349. regulator-boot-on;
  350. enable-active-high;
  351. gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
  352. vin-supply = <&sys_3v3_reg>;
  353. };
  354. };
  355. gpio-leds {
  356. compatible = "gpio-leds";
  357. gpled1 {
  358. label = "LED1"; /* CR5A1 (blue) */
  359. gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
  360. };
  361. gpled2 {
  362. label = "LED2"; /* CR4A2 (green) */
  363. gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
  364. };
  365. };
  366. sound {
  367. compatible = "nvidia,tegra-audio-rt5640-beaver",
  368. "nvidia,tegra-audio-rt5640";
  369. nvidia,model = "NVIDIA Tegra Beaver";
  370. nvidia,audio-routing =
  371. "Headphones", "HPOR",
  372. "Headphones", "HPOL";
  373. nvidia,i2s-controller = <&tegra_i2s1>;
  374. nvidia,audio-codec = <&rt5640>;
  375. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
  376. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  377. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  378. <&tegra_car TEGRA30_CLK_EXTERN1>;
  379. clock-names = "pll_a", "pll_a_out0", "mclk";
  380. };
  381. };