tegra20-ventana.dts 14 KB

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  1. /dts-v1/;
  2. #include "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra20 Ventana evaluation board";
  5. compatible = "nvidia,ventana", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  16. GPIO_ACTIVE_HIGH>;
  17. };
  18. };
  19. pinmux {
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&state_default>;
  22. state_default: pinmux {
  23. ata {
  24. nvidia,pins = "ata";
  25. nvidia,function = "ide";
  26. };
  27. atb {
  28. nvidia,pins = "atb", "gma", "gme";
  29. nvidia,function = "sdio4";
  30. };
  31. atc {
  32. nvidia,pins = "atc";
  33. nvidia,function = "nand";
  34. };
  35. atd {
  36. nvidia,pins = "atd", "ate", "gmb", "spia",
  37. "spib", "spic";
  38. nvidia,function = "gmi";
  39. };
  40. cdev1 {
  41. nvidia,pins = "cdev1";
  42. nvidia,function = "plla_out";
  43. };
  44. cdev2 {
  45. nvidia,pins = "cdev2";
  46. nvidia,function = "pllp_out4";
  47. };
  48. crtp {
  49. nvidia,pins = "crtp", "lm1";
  50. nvidia,function = "crt";
  51. };
  52. csus {
  53. nvidia,pins = "csus";
  54. nvidia,function = "vi_sensor_clk";
  55. };
  56. dap1 {
  57. nvidia,pins = "dap1";
  58. nvidia,function = "dap1";
  59. };
  60. dap2 {
  61. nvidia,pins = "dap2";
  62. nvidia,function = "dap2";
  63. };
  64. dap3 {
  65. nvidia,pins = "dap3";
  66. nvidia,function = "dap3";
  67. };
  68. dap4 {
  69. nvidia,pins = "dap4";
  70. nvidia,function = "dap4";
  71. };
  72. dta {
  73. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  74. nvidia,function = "vi";
  75. };
  76. dtf {
  77. nvidia,pins = "dtf";
  78. nvidia,function = "i2c3";
  79. };
  80. gmc {
  81. nvidia,pins = "gmc";
  82. nvidia,function = "uartd";
  83. };
  84. gmd {
  85. nvidia,pins = "gmd";
  86. nvidia,function = "sflash";
  87. };
  88. gpu {
  89. nvidia,pins = "gpu";
  90. nvidia,function = "pwm";
  91. };
  92. gpu7 {
  93. nvidia,pins = "gpu7";
  94. nvidia,function = "rtck";
  95. };
  96. gpv {
  97. nvidia,pins = "gpv", "slxa", "slxk";
  98. nvidia,function = "pcie";
  99. };
  100. hdint {
  101. nvidia,pins = "hdint";
  102. nvidia,function = "hdmi";
  103. };
  104. i2cp {
  105. nvidia,pins = "i2cp";
  106. nvidia,function = "i2cp";
  107. };
  108. irrx {
  109. nvidia,pins = "irrx", "irtx";
  110. nvidia,function = "uartb";
  111. };
  112. kbca {
  113. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  114. "kbce", "kbcf";
  115. nvidia,function = "kbc";
  116. };
  117. lcsn {
  118. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  119. "lsdi", "lvp0";
  120. nvidia,function = "rsvd4";
  121. };
  122. ld0 {
  123. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  124. "ld5", "ld6", "ld7", "ld8", "ld9",
  125. "ld10", "ld11", "ld12", "ld13", "ld14",
  126. "ld15", "ld16", "ld17", "ldi", "lhp0",
  127. "lhp1", "lhp2", "lhs", "lpp", "lpw0",
  128. "lpw2", "lsc0", "lsc1", "lsck", "lsda",
  129. "lspi", "lvp1", "lvs";
  130. nvidia,function = "displaya";
  131. };
  132. owc {
  133. nvidia,pins = "owc", "spdi", "spdo", "uac";
  134. nvidia,function = "rsvd2";
  135. };
  136. pmc {
  137. nvidia,pins = "pmc";
  138. nvidia,function = "pwr_on";
  139. };
  140. rm {
  141. nvidia,pins = "rm";
  142. nvidia,function = "i2c1";
  143. };
  144. sdb {
  145. nvidia,pins = "sdb", "sdc", "sdd", "slxc";
  146. nvidia,function = "sdio3";
  147. };
  148. sdio1 {
  149. nvidia,pins = "sdio1";
  150. nvidia,function = "sdio1";
  151. };
  152. slxd {
  153. nvidia,pins = "slxd";
  154. nvidia,function = "spdif";
  155. };
  156. spid {
  157. nvidia,pins = "spid", "spie", "spif";
  158. nvidia,function = "spi1";
  159. };
  160. spig {
  161. nvidia,pins = "spig", "spih";
  162. nvidia,function = "spi2_alt";
  163. };
  164. uaa {
  165. nvidia,pins = "uaa", "uab", "uda";
  166. nvidia,function = "ulpi";
  167. };
  168. uad {
  169. nvidia,pins = "uad";
  170. nvidia,function = "irda";
  171. };
  172. uca {
  173. nvidia,pins = "uca", "ucb";
  174. nvidia,function = "uartc";
  175. };
  176. conf_ata {
  177. nvidia,pins = "ata", "atb", "atc", "atd",
  178. "cdev1", "cdev2", "dap1", "dap2",
  179. "dap4", "ddc", "dtf", "gma", "gmc",
  180. "gme", "gpu", "gpu7", "i2cp", "irrx",
  181. "irtx", "pta", "rm", "sdc", "sdd",
  182. "slxc", "slxd", "slxk", "spdi", "spdo",
  183. "uac", "uad", "uca", "ucb", "uda";
  184. nvidia,pull = <0>;
  185. nvidia,tristate = <0>;
  186. };
  187. conf_ate {
  188. nvidia,pins = "ate", "csus", "dap3", "gmd",
  189. "gpv", "owc", "spia", "spib", "spic",
  190. "spid", "spie", "spig";
  191. nvidia,pull = <0>;
  192. nvidia,tristate = <1>;
  193. };
  194. conf_ck32 {
  195. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  196. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  197. nvidia,pull = <0>;
  198. };
  199. conf_crtp {
  200. nvidia,pins = "crtp", "gmb", "slxa", "spih";
  201. nvidia,pull = <2>;
  202. nvidia,tristate = <1>;
  203. };
  204. conf_dta {
  205. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  206. nvidia,pull = <1>;
  207. nvidia,tristate = <0>;
  208. };
  209. conf_dte {
  210. nvidia,pins = "dte", "spif";
  211. nvidia,pull = <1>;
  212. nvidia,tristate = <1>;
  213. };
  214. conf_hdint {
  215. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  216. "lpw1", "lsck", "lsda", "lsdi", "lvp0";
  217. nvidia,tristate = <1>;
  218. };
  219. conf_kbca {
  220. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  221. "kbce", "kbcf", "sdio1", "uaa", "uab";
  222. nvidia,pull = <2>;
  223. nvidia,tristate = <0>;
  224. };
  225. conf_lc {
  226. nvidia,pins = "lc", "ls";
  227. nvidia,pull = <2>;
  228. };
  229. conf_ld0 {
  230. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  231. "ld5", "ld6", "ld7", "ld8", "ld9",
  232. "ld10", "ld11", "ld12", "ld13", "ld14",
  233. "ld15", "ld16", "ld17", "ldi", "lhp0",
  234. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  235. "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
  236. "lvp1", "lvs", "pmc", "sdb";
  237. nvidia,tristate = <0>;
  238. };
  239. conf_ld17_0 {
  240. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  241. "ld23_22";
  242. nvidia,pull = <1>;
  243. };
  244. drive_sdio1 {
  245. nvidia,pins = "drive_sdio1";
  246. nvidia,high-speed-mode = <0>;
  247. nvidia,schmitt = <1>;
  248. nvidia,low-power-mode = <3>;
  249. nvidia,pull-down-strength = <31>;
  250. nvidia,pull-up-strength = <31>;
  251. nvidia,slew-rate-rising = <3>;
  252. nvidia,slew-rate-falling = <3>;
  253. };
  254. };
  255. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  256. ddc {
  257. nvidia,pins = "ddc";
  258. nvidia,function = "i2c2";
  259. };
  260. pta {
  261. nvidia,pins = "pta";
  262. nvidia,function = "rsvd4";
  263. };
  264. };
  265. state_i2cmux_pta: pinmux_i2cmux_pta {
  266. ddc {
  267. nvidia,pins = "ddc";
  268. nvidia,function = "rsvd4";
  269. };
  270. pta {
  271. nvidia,pins = "pta";
  272. nvidia,function = "i2c2";
  273. };
  274. };
  275. state_i2cmux_idle: pinmux_i2cmux_idle {
  276. ddc {
  277. nvidia,pins = "ddc";
  278. nvidia,function = "rsvd4";
  279. };
  280. pta {
  281. nvidia,pins = "pta";
  282. nvidia,function = "rsvd4";
  283. };
  284. };
  285. };
  286. i2s@70002800 {
  287. status = "okay";
  288. };
  289. serial@70006300 {
  290. status = "okay";
  291. };
  292. i2c@7000c000 {
  293. status = "okay";
  294. clock-frequency = <400000>;
  295. wm8903: wm8903@1a {
  296. compatible = "wlf,wm8903";
  297. reg = <0x1a>;
  298. interrupt-parent = <&gpio>;
  299. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  300. gpio-controller;
  301. #gpio-cells = <2>;
  302. micdet-cfg = <0>;
  303. micdet-delay = <100>;
  304. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  305. };
  306. /* ALS and proximity sensor */
  307. isl29018@44 {
  308. compatible = "isil,isl29018";
  309. reg = <0x44>;
  310. interrupt-parent = <&gpio>;
  311. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  312. };
  313. };
  314. i2c@7000c400 {
  315. status = "okay";
  316. clock-frequency = <100000>;
  317. };
  318. i2cmux {
  319. compatible = "i2c-mux-pinctrl";
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. i2c-parent = <&{/i2c@7000c400}>;
  323. pinctrl-names = "ddc", "pta", "idle";
  324. pinctrl-0 = <&state_i2cmux_ddc>;
  325. pinctrl-1 = <&state_i2cmux_pta>;
  326. pinctrl-2 = <&state_i2cmux_idle>;
  327. hdmi_ddc: i2c@0 {
  328. reg = <0>;
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. };
  332. i2c@1 {
  333. reg = <1>;
  334. #address-cells = <1>;
  335. #size-cells = <0>;
  336. };
  337. };
  338. i2c@7000c500 {
  339. status = "okay";
  340. clock-frequency = <400000>;
  341. };
  342. i2c@7000d000 {
  343. status = "okay";
  344. clock-frequency = <400000>;
  345. pmic: tps6586x@34 {
  346. compatible = "ti,tps6586x";
  347. reg = <0x34>;
  348. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  349. ti,system-power-controller;
  350. #gpio-cells = <2>;
  351. gpio-controller;
  352. sys-supply = <&vdd_5v0_reg>;
  353. vin-sm0-supply = <&sys_reg>;
  354. vin-sm1-supply = <&sys_reg>;
  355. vin-sm2-supply = <&sys_reg>;
  356. vinldo01-supply = <&sm2_reg>;
  357. vinldo23-supply = <&sm2_reg>;
  358. vinldo4-supply = <&sm2_reg>;
  359. vinldo678-supply = <&sm2_reg>;
  360. vinldo9-supply = <&sm2_reg>;
  361. regulators {
  362. sys_reg: sys {
  363. regulator-name = "vdd_sys";
  364. regulator-always-on;
  365. };
  366. sm0 {
  367. regulator-name = "vdd_sm0,vdd_core";
  368. regulator-min-microvolt = <1200000>;
  369. regulator-max-microvolt = <1200000>;
  370. regulator-always-on;
  371. };
  372. sm1 {
  373. regulator-name = "vdd_sm1,vdd_cpu";
  374. regulator-min-microvolt = <1000000>;
  375. regulator-max-microvolt = <1000000>;
  376. regulator-always-on;
  377. };
  378. sm2_reg: sm2 {
  379. regulator-name = "vdd_sm2,vin_ldo*";
  380. regulator-min-microvolt = <3700000>;
  381. regulator-max-microvolt = <3700000>;
  382. regulator-always-on;
  383. };
  384. /* LDO0 is not connected to anything */
  385. ldo1 {
  386. regulator-name = "vdd_ldo1,avdd_pll*";
  387. regulator-min-microvolt = <1100000>;
  388. regulator-max-microvolt = <1100000>;
  389. regulator-always-on;
  390. };
  391. ldo2 {
  392. regulator-name = "vdd_ldo2,vdd_rtc";
  393. regulator-min-microvolt = <1200000>;
  394. regulator-max-microvolt = <1200000>;
  395. };
  396. ldo3 {
  397. regulator-name = "vdd_ldo3,avdd_usb*";
  398. regulator-min-microvolt = <3300000>;
  399. regulator-max-microvolt = <3300000>;
  400. regulator-always-on;
  401. };
  402. ldo4 {
  403. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  404. regulator-min-microvolt = <1800000>;
  405. regulator-max-microvolt = <1800000>;
  406. regulator-always-on;
  407. };
  408. ldo5 {
  409. regulator-name = "vdd_ldo5,vcore_mmc";
  410. regulator-min-microvolt = <2850000>;
  411. regulator-max-microvolt = <2850000>;
  412. regulator-always-on;
  413. };
  414. ldo6 {
  415. regulator-name = "vdd_ldo6,avdd_vdac";
  416. regulator-min-microvolt = <1800000>;
  417. regulator-max-microvolt = <1800000>;
  418. };
  419. hdmi_vdd_reg: ldo7 {
  420. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  421. regulator-min-microvolt = <3300000>;
  422. regulator-max-microvolt = <3300000>;
  423. };
  424. hdmi_pll_reg: ldo8 {
  425. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  426. regulator-min-microvolt = <1800000>;
  427. regulator-max-microvolt = <1800000>;
  428. };
  429. ldo9 {
  430. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  431. regulator-min-microvolt = <2850000>;
  432. regulator-max-microvolt = <2850000>;
  433. regulator-always-on;
  434. };
  435. ldo_rtc {
  436. regulator-name = "vdd_rtc_out,vdd_cell";
  437. regulator-min-microvolt = <3300000>;
  438. regulator-max-microvolt = <3300000>;
  439. regulator-always-on;
  440. };
  441. };
  442. };
  443. temperature-sensor@4c {
  444. compatible = "onnn,nct1008";
  445. reg = <0x4c>;
  446. };
  447. };
  448. pmc {
  449. nvidia,invert-interrupt;
  450. nvidia,suspend-mode = <2>;
  451. nvidia,cpu-pwr-good-time = <2000>;
  452. nvidia,cpu-pwr-off-time = <100>;
  453. nvidia,core-pwr-good-time = <3845 3845>;
  454. nvidia,core-pwr-off-time = <458>;
  455. nvidia,sys-clock-req-active-high;
  456. };
  457. usb@c5000000 {
  458. status = "okay";
  459. };
  460. usb-phy@c5000000 {
  461. status = "okay";
  462. };
  463. usb@c5004000 {
  464. status = "okay";
  465. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  466. GPIO_ACTIVE_LOW>;
  467. };
  468. usb-phy@c5004000 {
  469. status = "okay";
  470. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  471. GPIO_ACTIVE_LOW>;
  472. };
  473. usb@c5008000 {
  474. status = "okay";
  475. };
  476. usb-phy@c5008000 {
  477. status = "okay";
  478. };
  479. sdhci@c8000000 {
  480. status = "okay";
  481. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  482. bus-width = <4>;
  483. keep-power-in-suspend;
  484. };
  485. sdhci@c8000400 {
  486. status = "okay";
  487. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  488. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  489. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  490. bus-width = <4>;
  491. };
  492. sdhci@c8000600 {
  493. status = "okay";
  494. bus-width = <8>;
  495. non-removable;
  496. };
  497. clocks {
  498. compatible = "simple-bus";
  499. #address-cells = <1>;
  500. #size-cells = <0>;
  501. clk32k_in: clock {
  502. compatible = "fixed-clock";
  503. reg=<0>;
  504. #clock-cells = <0>;
  505. clock-frequency = <32768>;
  506. };
  507. };
  508. gpio-keys {
  509. compatible = "gpio-keys";
  510. power {
  511. label = "Power";
  512. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  513. linux,code = <116>; /* KEY_POWER */
  514. gpio-key,wakeup;
  515. };
  516. };
  517. regulators {
  518. compatible = "simple-bus";
  519. #address-cells = <1>;
  520. #size-cells = <0>;
  521. vdd_5v0_reg: regulator@0 {
  522. compatible = "regulator-fixed";
  523. reg = <0>;
  524. regulator-name = "vdd_5v0";
  525. regulator-min-microvolt = <5000000>;
  526. regulator-max-microvolt = <5000000>;
  527. regulator-always-on;
  528. };
  529. regulator@1 {
  530. compatible = "regulator-fixed";
  531. reg = <1>;
  532. regulator-name = "vdd_1v5";
  533. regulator-min-microvolt = <1500000>;
  534. regulator-max-microvolt = <1500000>;
  535. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  536. };
  537. regulator@2 {
  538. compatible = "regulator-fixed";
  539. reg = <2>;
  540. regulator-name = "vdd_1v2";
  541. regulator-min-microvolt = <1200000>;
  542. regulator-max-microvolt = <1200000>;
  543. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  544. enable-active-high;
  545. };
  546. regulator@3 {
  547. compatible = "regulator-fixed";
  548. reg = <3>;
  549. regulator-name = "vdd_pnl";
  550. regulator-min-microvolt = <2800000>;
  551. regulator-max-microvolt = <2800000>;
  552. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  553. enable-active-high;
  554. };
  555. regulator@4 {
  556. compatible = "regulator-fixed";
  557. reg = <4>;
  558. regulator-name = "vdd_bl";
  559. regulator-min-microvolt = <2800000>;
  560. regulator-max-microvolt = <2800000>;
  561. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  562. enable-active-high;
  563. };
  564. };
  565. sound {
  566. compatible = "nvidia,tegra-audio-wm8903-ventana",
  567. "nvidia,tegra-audio-wm8903";
  568. nvidia,model = "NVIDIA Tegra Ventana";
  569. nvidia,audio-routing =
  570. "Headphone Jack", "HPOUTR",
  571. "Headphone Jack", "HPOUTL",
  572. "Int Spk", "ROP",
  573. "Int Spk", "RON",
  574. "Int Spk", "LOP",
  575. "Int Spk", "LON",
  576. "Mic Jack", "MICBIAS",
  577. "IN1L", "Mic Jack";
  578. nvidia,i2s-controller = <&tegra_i2s1>;
  579. nvidia,audio-codec = <&wm8903>;
  580. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  581. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
  582. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  583. GPIO_ACTIVE_HIGH>;
  584. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  585. GPIO_ACTIVE_HIGH>;
  586. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  587. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  588. <&tegra_car TEGRA20_CLK_CDEV1>;
  589. clock-names = "pll_a", "pll_a_out0", "mclk";
  590. };
  591. };