tegra20-trimslice.dts 8.6 KB

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  1. /dts-v1/;
  2. #include "tegra20.dtsi"
  3. / {
  4. model = "Compulab TrimSlice board";
  5. compatible = "compulab,trimslice", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  16. GPIO_ACTIVE_HIGH>;
  17. };
  18. };
  19. pinmux {
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&state_default>;
  22. state_default: pinmux {
  23. ata {
  24. nvidia,pins = "ata";
  25. nvidia,function = "ide";
  26. };
  27. atb {
  28. nvidia,pins = "atb", "gma";
  29. nvidia,function = "sdio4";
  30. };
  31. atc {
  32. nvidia,pins = "atc", "gmb";
  33. nvidia,function = "nand";
  34. };
  35. atd {
  36. nvidia,pins = "atd", "ate", "gme", "pta";
  37. nvidia,function = "gmi";
  38. };
  39. cdev1 {
  40. nvidia,pins = "cdev1";
  41. nvidia,function = "plla_out";
  42. };
  43. cdev2 {
  44. nvidia,pins = "cdev2";
  45. nvidia,function = "pllp_out4";
  46. };
  47. crtp {
  48. nvidia,pins = "crtp";
  49. nvidia,function = "crt";
  50. };
  51. csus {
  52. nvidia,pins = "csus";
  53. nvidia,function = "vi_sensor_clk";
  54. };
  55. dap1 {
  56. nvidia,pins = "dap1";
  57. nvidia,function = "dap1";
  58. };
  59. dap2 {
  60. nvidia,pins = "dap2";
  61. nvidia,function = "dap2";
  62. };
  63. dap3 {
  64. nvidia,pins = "dap3";
  65. nvidia,function = "dap3";
  66. };
  67. dap4 {
  68. nvidia,pins = "dap4";
  69. nvidia,function = "dap4";
  70. };
  71. ddc {
  72. nvidia,pins = "ddc";
  73. nvidia,function = "i2c2";
  74. };
  75. dta {
  76. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  77. nvidia,function = "vi";
  78. };
  79. dtf {
  80. nvidia,pins = "dtf";
  81. nvidia,function = "i2c3";
  82. };
  83. gmc {
  84. nvidia,pins = "gmc", "gmd";
  85. nvidia,function = "sflash";
  86. };
  87. gpu {
  88. nvidia,pins = "gpu";
  89. nvidia,function = "uarta";
  90. };
  91. gpu7 {
  92. nvidia,pins = "gpu7";
  93. nvidia,function = "rtck";
  94. };
  95. gpv {
  96. nvidia,pins = "gpv", "slxa", "slxk";
  97. nvidia,function = "pcie";
  98. };
  99. hdint {
  100. nvidia,pins = "hdint";
  101. nvidia,function = "hdmi";
  102. };
  103. i2cp {
  104. nvidia,pins = "i2cp";
  105. nvidia,function = "i2cp";
  106. };
  107. irrx {
  108. nvidia,pins = "irrx", "irtx";
  109. nvidia,function = "uartb";
  110. };
  111. kbca {
  112. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  113. "kbce", "kbcf";
  114. nvidia,function = "kbc";
  115. };
  116. lcsn {
  117. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  118. "ld3", "ld4", "ld5", "ld6", "ld7",
  119. "ld8", "ld9", "ld10", "ld11", "ld12",
  120. "ld13", "ld14", "ld15", "ld16", "ld17",
  121. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  122. "lhs", "lm0", "lm1", "lpp", "lpw0",
  123. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  124. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  125. "lvs";
  126. nvidia,function = "displaya";
  127. };
  128. owc {
  129. nvidia,pins = "owc", "uac";
  130. nvidia,function = "rsvd2";
  131. };
  132. pmc {
  133. nvidia,pins = "pmc";
  134. nvidia,function = "pwr_on";
  135. };
  136. rm {
  137. nvidia,pins = "rm";
  138. nvidia,function = "i2c1";
  139. };
  140. sdb {
  141. nvidia,pins = "sdb", "sdc", "sdd";
  142. nvidia,function = "pwm";
  143. };
  144. sdio1 {
  145. nvidia,pins = "sdio1";
  146. nvidia,function = "sdio1";
  147. };
  148. slxc {
  149. nvidia,pins = "slxc", "slxd";
  150. nvidia,function = "sdio3";
  151. };
  152. spdi {
  153. nvidia,pins = "spdi", "spdo";
  154. nvidia,function = "spdif";
  155. };
  156. spia {
  157. nvidia,pins = "spia", "spib", "spic";
  158. nvidia,function = "spi2";
  159. };
  160. spid {
  161. nvidia,pins = "spid", "spie", "spif";
  162. nvidia,function = "spi1";
  163. };
  164. spig {
  165. nvidia,pins = "spig", "spih";
  166. nvidia,function = "spi2_alt";
  167. };
  168. uaa {
  169. nvidia,pins = "uaa", "uab", "uda";
  170. nvidia,function = "ulpi";
  171. };
  172. uad {
  173. nvidia,pins = "uad";
  174. nvidia,function = "irda";
  175. };
  176. uca {
  177. nvidia,pins = "uca", "ucb";
  178. nvidia,function = "uartc";
  179. };
  180. conf_ata {
  181. nvidia,pins = "ata", "atc", "atd", "ate",
  182. "crtp", "dap2", "dap3", "dap4", "dta",
  183. "dtb", "dtc", "dtd", "dte", "gmb",
  184. "gme", "i2cp", "pta", "slxc", "slxd",
  185. "spdi", "spdo", "uda";
  186. nvidia,pull = <0>;
  187. nvidia,tristate = <1>;
  188. };
  189. conf_atb {
  190. nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
  191. "gma", "gmc", "gmd", "gpu", "gpu7",
  192. "gpv", "sdio1", "slxa", "slxk", "uac";
  193. nvidia,pull = <0>;
  194. nvidia,tristate = <0>;
  195. };
  196. conf_ck32 {
  197. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  198. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  199. nvidia,pull = <0>;
  200. };
  201. conf_csus {
  202. nvidia,pins = "csus", "spia", "spib",
  203. "spid", "spif";
  204. nvidia,pull = <1>;
  205. nvidia,tristate = <1>;
  206. };
  207. conf_ddc {
  208. nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
  209. nvidia,pull = <2>;
  210. nvidia,tristate = <0>;
  211. };
  212. conf_hdint {
  213. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  214. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  215. "lvp0", "pmc";
  216. nvidia,tristate = <1>;
  217. };
  218. conf_irrx {
  219. nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
  220. "kbcc", "kbcd", "kbce", "kbcf", "owc",
  221. "spic", "spie", "spig", "spih", "uaa",
  222. "uab", "uad", "uca", "ucb";
  223. nvidia,pull = <2>;
  224. nvidia,tristate = <1>;
  225. };
  226. conf_lc {
  227. nvidia,pins = "lc", "ls";
  228. nvidia,pull = <2>;
  229. };
  230. conf_ld0 {
  231. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  232. "ld5", "ld6", "ld7", "ld8", "ld9",
  233. "ld10", "ld11", "ld12", "ld13", "ld14",
  234. "ld15", "ld16", "ld17", "ldi", "lhp0",
  235. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  236. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  237. "lvs", "sdb";
  238. nvidia,tristate = <0>;
  239. };
  240. conf_ld17_0 {
  241. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  242. "ld23_22";
  243. nvidia,pull = <1>;
  244. };
  245. conf_spif {
  246. nvidia,pins = "spif";
  247. nvidia,pull = <1>;
  248. nvidia,tristate = <0>;
  249. };
  250. };
  251. };
  252. i2s@70002800 {
  253. status = "okay";
  254. };
  255. serial@70006000 {
  256. status = "okay";
  257. };
  258. dvi_ddc: i2c@7000c000 {
  259. status = "okay";
  260. clock-frequency = <100000>;
  261. };
  262. spi@7000c380 {
  263. status = "okay";
  264. spi-max-frequency = <48000000>;
  265. spi-flash@0 {
  266. compatible = "winbond,w25q80bl";
  267. reg = <0>;
  268. spi-max-frequency = <48000000>;
  269. };
  270. };
  271. hdmi_ddc: i2c@7000c400 {
  272. status = "okay";
  273. clock-frequency = <100000>;
  274. };
  275. i2c@7000c500 {
  276. status = "okay";
  277. clock-frequency = <400000>;
  278. codec: codec@1a {
  279. compatible = "ti,tlv320aic23";
  280. reg = <0x1a>;
  281. };
  282. rtc@56 {
  283. compatible = "emmicro,em3027";
  284. reg = <0x56>;
  285. };
  286. };
  287. pmc {
  288. nvidia,suspend-mode = <2>;
  289. nvidia,cpu-pwr-good-time = <5000>;
  290. nvidia,cpu-pwr-off-time = <5000>;
  291. nvidia,core-pwr-good-time = <3845 3845>;
  292. nvidia,core-pwr-off-time = <3875>;
  293. nvidia,sys-clock-req-active-high;
  294. };
  295. usb@c5000000 {
  296. status = "okay";
  297. nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  298. };
  299. usb-phy@c5000000 {
  300. status = "okay";
  301. vbus-supply = <&vbus_reg>;
  302. };
  303. usb@c5004000 {
  304. status = "okay";
  305. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  306. GPIO_ACTIVE_LOW>;
  307. };
  308. usb-phy@c5004000 {
  309. status = "okay";
  310. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  311. GPIO_ACTIVE_LOW>;
  312. };
  313. usb@c5008000 {
  314. status = "okay";
  315. };
  316. usb-phy@c5008000 {
  317. status = "okay";
  318. };
  319. sdhci@c8000000 {
  320. status = "okay";
  321. bus-width = <4>;
  322. };
  323. sdhci@c8000600 {
  324. status = "okay";
  325. cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
  326. wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
  327. bus-width = <4>;
  328. };
  329. clocks {
  330. compatible = "simple-bus";
  331. #address-cells = <1>;
  332. #size-cells = <0>;
  333. clk32k_in: clock {
  334. compatible = "fixed-clock";
  335. reg=<0>;
  336. #clock-cells = <0>;
  337. clock-frequency = <32768>;
  338. };
  339. };
  340. gpio-keys {
  341. compatible = "gpio-keys";
  342. power {
  343. label = "Power";
  344. gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
  345. linux,code = <116>; /* KEY_POWER */
  346. gpio-key,wakeup;
  347. };
  348. };
  349. poweroff {
  350. compatible = "gpio-poweroff";
  351. gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
  352. };
  353. regulators {
  354. compatible = "simple-bus";
  355. #address-cells = <1>;
  356. #size-cells = <0>;
  357. hdmi_vdd_reg: regulator@0 {
  358. compatible = "regulator-fixed";
  359. reg = <0>;
  360. regulator-name = "avdd_hdmi";
  361. regulator-min-microvolt = <3300000>;
  362. regulator-max-microvolt = <3300000>;
  363. regulator-always-on;
  364. };
  365. hdmi_pll_reg: regulator@1 {
  366. compatible = "regulator-fixed";
  367. reg = <1>;
  368. regulator-name = "avdd_hdmi_pll";
  369. regulator-min-microvolt = <1800000>;
  370. regulator-max-microvolt = <1800000>;
  371. regulator-always-on;
  372. };
  373. vbus_reg: regulator@2 {
  374. compatible = "regulator-fixed";
  375. reg = <2>;
  376. regulator-name = "usb1_vbus";
  377. regulator-min-microvolt = <5000000>;
  378. regulator-max-microvolt = <5000000>;
  379. enable-active-high;
  380. gpio = <&gpio 170 0>; /* PV2 */
  381. };
  382. };
  383. sound {
  384. compatible = "nvidia,tegra-audio-trimslice";
  385. nvidia,i2s-controller = <&tegra_i2s1>;
  386. nvidia,audio-codec = <&codec>;
  387. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  388. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  389. <&tegra_car TEGRA20_CLK_CDEV1>;
  390. clock-names = "pll_a", "pll_a_out0", "mclk";
  391. };
  392. };