tegra20-seaboard.dts 19 KB

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  1. /dts-v1/;
  2. #include "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Seaboard";
  5. compatible = "nvidia,seaboard", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  16. GPIO_ACTIVE_HIGH>;
  17. };
  18. };
  19. pinmux {
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&state_default>;
  22. state_default: pinmux {
  23. ata {
  24. nvidia,pins = "ata";
  25. nvidia,function = "ide";
  26. };
  27. atb {
  28. nvidia,pins = "atb", "gma", "gme";
  29. nvidia,function = "sdio4";
  30. };
  31. atc {
  32. nvidia,pins = "atc";
  33. nvidia,function = "nand";
  34. };
  35. atd {
  36. nvidia,pins = "atd", "ate", "gmb", "spia",
  37. "spib", "spic";
  38. nvidia,function = "gmi";
  39. };
  40. cdev1 {
  41. nvidia,pins = "cdev1";
  42. nvidia,function = "plla_out";
  43. };
  44. cdev2 {
  45. nvidia,pins = "cdev2";
  46. nvidia,function = "pllp_out4";
  47. };
  48. crtp {
  49. nvidia,pins = "crtp", "lm1";
  50. nvidia,function = "crt";
  51. };
  52. csus {
  53. nvidia,pins = "csus";
  54. nvidia,function = "vi_sensor_clk";
  55. };
  56. dap1 {
  57. nvidia,pins = "dap1";
  58. nvidia,function = "dap1";
  59. };
  60. dap2 {
  61. nvidia,pins = "dap2";
  62. nvidia,function = "dap2";
  63. };
  64. dap3 {
  65. nvidia,pins = "dap3";
  66. nvidia,function = "dap3";
  67. };
  68. dap4 {
  69. nvidia,pins = "dap4";
  70. nvidia,function = "dap4";
  71. };
  72. dta {
  73. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  74. nvidia,function = "vi";
  75. };
  76. dtf {
  77. nvidia,pins = "dtf";
  78. nvidia,function = "i2c3";
  79. };
  80. gmc {
  81. nvidia,pins = "gmc";
  82. nvidia,function = "uartd";
  83. };
  84. gmd {
  85. nvidia,pins = "gmd";
  86. nvidia,function = "sflash";
  87. };
  88. gpu {
  89. nvidia,pins = "gpu";
  90. nvidia,function = "pwm";
  91. };
  92. gpu7 {
  93. nvidia,pins = "gpu7";
  94. nvidia,function = "rtck";
  95. };
  96. gpv {
  97. nvidia,pins = "gpv", "slxa", "slxk";
  98. nvidia,function = "pcie";
  99. };
  100. hdint {
  101. nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1",
  102. "lsck", "lsda";
  103. nvidia,function = "hdmi";
  104. };
  105. i2cp {
  106. nvidia,pins = "i2cp";
  107. nvidia,function = "i2cp";
  108. };
  109. irrx {
  110. nvidia,pins = "irrx", "irtx";
  111. nvidia,function = "uartb";
  112. };
  113. kbca {
  114. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  115. "kbce", "kbcf";
  116. nvidia,function = "kbc";
  117. };
  118. lcsn {
  119. nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
  120. "lsdi", "lvp0";
  121. nvidia,function = "rsvd4";
  122. };
  123. ld0 {
  124. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  125. "ld5", "ld6", "ld7", "ld8", "ld9",
  126. "ld10", "ld11", "ld12", "ld13", "ld14",
  127. "ld15", "ld16", "ld17", "ldi", "lhp0",
  128. "lhp1", "lhp2", "lhs", "lpp", "lsc0",
  129. "lspi", "lvp1", "lvs";
  130. nvidia,function = "displaya";
  131. };
  132. owc {
  133. nvidia,pins = "owc", "spdi", "spdo", "uac";
  134. nvidia,function = "rsvd2";
  135. };
  136. pmc {
  137. nvidia,pins = "pmc";
  138. nvidia,function = "pwr_on";
  139. };
  140. rm {
  141. nvidia,pins = "rm";
  142. nvidia,function = "i2c1";
  143. };
  144. sdb {
  145. nvidia,pins = "sdb", "sdc", "sdd";
  146. nvidia,function = "sdio3";
  147. };
  148. sdio1 {
  149. nvidia,pins = "sdio1";
  150. nvidia,function = "sdio1";
  151. };
  152. slxc {
  153. nvidia,pins = "slxc", "slxd";
  154. nvidia,function = "spdif";
  155. };
  156. spid {
  157. nvidia,pins = "spid", "spie", "spif";
  158. nvidia,function = "spi1";
  159. };
  160. spig {
  161. nvidia,pins = "spig", "spih";
  162. nvidia,function = "spi2_alt";
  163. };
  164. uaa {
  165. nvidia,pins = "uaa", "uab", "uda";
  166. nvidia,function = "ulpi";
  167. };
  168. uad {
  169. nvidia,pins = "uad";
  170. nvidia,function = "irda";
  171. };
  172. uca {
  173. nvidia,pins = "uca", "ucb";
  174. nvidia,function = "uartc";
  175. };
  176. conf_ata {
  177. nvidia,pins = "ata", "atb", "atc", "atd",
  178. "cdev1", "cdev2", "dap1", "dap2",
  179. "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
  180. "gme", "gpu", "gpu7", "i2cp", "irrx",
  181. "irtx", "pta", "rm", "sdc", "sdd",
  182. "slxd", "slxk", "spdi", "spdo", "uac",
  183. "uad", "uca", "ucb", "uda";
  184. nvidia,pull = <0>;
  185. nvidia,tristate = <0>;
  186. };
  187. conf_ate {
  188. nvidia,pins = "ate", "csus", "dap3",
  189. "gpv", "owc", "slxc", "spib", "spid",
  190. "spie";
  191. nvidia,pull = <0>;
  192. nvidia,tristate = <1>;
  193. };
  194. conf_ck32 {
  195. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  196. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  197. nvidia,pull = <0>;
  198. };
  199. conf_crtp {
  200. nvidia,pins = "crtp", "gmb", "slxa", "spia",
  201. "spig", "spih";
  202. nvidia,pull = <2>;
  203. nvidia,tristate = <1>;
  204. };
  205. conf_dta {
  206. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  207. nvidia,pull = <1>;
  208. nvidia,tristate = <0>;
  209. };
  210. conf_dte {
  211. nvidia,pins = "dte", "spif";
  212. nvidia,pull = <1>;
  213. nvidia,tristate = <1>;
  214. };
  215. conf_hdint {
  216. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  217. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  218. "lvp0";
  219. nvidia,tristate = <1>;
  220. };
  221. conf_kbca {
  222. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  223. "kbce", "kbcf", "sdio1", "spic", "uaa",
  224. "uab";
  225. nvidia,pull = <2>;
  226. nvidia,tristate = <0>;
  227. };
  228. conf_lc {
  229. nvidia,pins = "lc", "ls";
  230. nvidia,pull = <2>;
  231. };
  232. conf_ld0 {
  233. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  234. "ld5", "ld6", "ld7", "ld8", "ld9",
  235. "ld10", "ld11", "ld12", "ld13", "ld14",
  236. "ld15", "ld16", "ld17", "ldi", "lhp0",
  237. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  238. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  239. "lvs", "pmc", "sdb";
  240. nvidia,tristate = <0>;
  241. };
  242. conf_ld17_0 {
  243. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  244. "ld23_22";
  245. nvidia,pull = <1>;
  246. };
  247. drive_sdio1 {
  248. nvidia,pins = "drive_sdio1";
  249. nvidia,high-speed-mode = <0>;
  250. nvidia,schmitt = <0>;
  251. nvidia,low-power-mode = <3>;
  252. nvidia,pull-down-strength = <31>;
  253. nvidia,pull-up-strength = <31>;
  254. nvidia,slew-rate-rising = <3>;
  255. nvidia,slew-rate-falling = <3>;
  256. };
  257. };
  258. state_i2cmux_ddc: pinmux_i2cmux_ddc {
  259. ddc {
  260. nvidia,pins = "ddc";
  261. nvidia,function = "i2c2";
  262. };
  263. pta {
  264. nvidia,pins = "pta";
  265. nvidia,function = "rsvd4";
  266. };
  267. };
  268. state_i2cmux_pta: pinmux_i2cmux_pta {
  269. ddc {
  270. nvidia,pins = "ddc";
  271. nvidia,function = "rsvd4";
  272. };
  273. pta {
  274. nvidia,pins = "pta";
  275. nvidia,function = "i2c2";
  276. };
  277. };
  278. state_i2cmux_idle: pinmux_i2cmux_idle {
  279. ddc {
  280. nvidia,pins = "ddc";
  281. nvidia,function = "rsvd4";
  282. };
  283. pta {
  284. nvidia,pins = "pta";
  285. nvidia,function = "rsvd4";
  286. };
  287. };
  288. };
  289. i2s@70002800 {
  290. status = "okay";
  291. };
  292. serial@70006300 {
  293. status = "okay";
  294. };
  295. i2c@7000c000 {
  296. status = "okay";
  297. clock-frequency = <400000>;
  298. wm8903: wm8903@1a {
  299. compatible = "wlf,wm8903";
  300. reg = <0x1a>;
  301. interrupt-parent = <&gpio>;
  302. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  303. gpio-controller;
  304. #gpio-cells = <2>;
  305. micdet-cfg = <0>;
  306. micdet-delay = <100>;
  307. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  308. };
  309. /* ALS and proximity sensor */
  310. isl29018@44 {
  311. compatible = "isil,isl29018";
  312. reg = <0x44>;
  313. interrupt-parent = <&gpio>;
  314. interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
  315. };
  316. gyrometer@68 {
  317. compatible = "invn,mpu3050";
  318. reg = <0x68>;
  319. interrupt-parent = <&gpio>;
  320. interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
  321. };
  322. };
  323. i2c@7000c400 {
  324. status = "okay";
  325. clock-frequency = <100000>;
  326. };
  327. i2cmux {
  328. compatible = "i2c-mux-pinctrl";
  329. #address-cells = <1>;
  330. #size-cells = <0>;
  331. i2c-parent = <&{/i2c@7000c400}>;
  332. pinctrl-names = "ddc", "pta", "idle";
  333. pinctrl-0 = <&state_i2cmux_ddc>;
  334. pinctrl-1 = <&state_i2cmux_pta>;
  335. pinctrl-2 = <&state_i2cmux_idle>;
  336. hdmi_ddc: i2c@0 {
  337. reg = <0>;
  338. #address-cells = <1>;
  339. #size-cells = <0>;
  340. };
  341. i2c@1 {
  342. reg = <1>;
  343. #address-cells = <1>;
  344. #size-cells = <0>;
  345. smart-battery@b {
  346. compatible = "ti,bq20z75", "smart-battery-1.1";
  347. reg = <0xb>;
  348. ti,i2c-retry-count = <2>;
  349. ti,poll-retry-count = <10>;
  350. };
  351. };
  352. };
  353. i2c@7000c500 {
  354. status = "okay";
  355. clock-frequency = <400000>;
  356. };
  357. i2c@7000d000 {
  358. status = "okay";
  359. clock-frequency = <400000>;
  360. pmic: tps6586x@34 {
  361. compatible = "ti,tps6586x";
  362. reg = <0x34>;
  363. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  364. ti,system-power-controller;
  365. #gpio-cells = <2>;
  366. gpio-controller;
  367. sys-supply = <&vdd_5v0_reg>;
  368. vin-sm0-supply = <&sys_reg>;
  369. vin-sm1-supply = <&sys_reg>;
  370. vin-sm2-supply = <&sys_reg>;
  371. vinldo01-supply = <&sm2_reg>;
  372. vinldo23-supply = <&sm2_reg>;
  373. vinldo4-supply = <&sm2_reg>;
  374. vinldo678-supply = <&sm2_reg>;
  375. vinldo9-supply = <&sm2_reg>;
  376. regulators {
  377. sys_reg: sys {
  378. regulator-name = "vdd_sys";
  379. regulator-always-on;
  380. };
  381. sm0 {
  382. regulator-name = "vdd_sm0,vdd_core";
  383. regulator-min-microvolt = <1300000>;
  384. regulator-max-microvolt = <1300000>;
  385. regulator-always-on;
  386. };
  387. sm1 {
  388. regulator-name = "vdd_sm1,vdd_cpu";
  389. regulator-min-microvolt = <1125000>;
  390. regulator-max-microvolt = <1125000>;
  391. regulator-always-on;
  392. };
  393. sm2_reg: sm2 {
  394. regulator-name = "vdd_sm2,vin_ldo*";
  395. regulator-min-microvolt = <3700000>;
  396. regulator-max-microvolt = <3700000>;
  397. regulator-always-on;
  398. };
  399. /* LDO0 is not connected to anything */
  400. ldo1 {
  401. regulator-name = "vdd_ldo1,avdd_pll*";
  402. regulator-min-microvolt = <1100000>;
  403. regulator-max-microvolt = <1100000>;
  404. regulator-always-on;
  405. };
  406. ldo2 {
  407. regulator-name = "vdd_ldo2,vdd_rtc";
  408. regulator-min-microvolt = <1200000>;
  409. regulator-max-microvolt = <1200000>;
  410. };
  411. ldo3 {
  412. regulator-name = "vdd_ldo3,avdd_usb*";
  413. regulator-min-microvolt = <3300000>;
  414. regulator-max-microvolt = <3300000>;
  415. regulator-always-on;
  416. };
  417. ldo4 {
  418. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  419. regulator-min-microvolt = <1800000>;
  420. regulator-max-microvolt = <1800000>;
  421. regulator-always-on;
  422. };
  423. ldo5 {
  424. regulator-name = "vdd_ldo5,vcore_mmc";
  425. regulator-min-microvolt = <2850000>;
  426. regulator-max-microvolt = <2850000>;
  427. regulator-always-on;
  428. };
  429. ldo6 {
  430. regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
  431. regulator-min-microvolt = <1800000>;
  432. regulator-max-microvolt = <1800000>;
  433. };
  434. hdmi_vdd_reg: ldo7 {
  435. regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
  436. regulator-min-microvolt = <3300000>;
  437. regulator-max-microvolt = <3300000>;
  438. };
  439. hdmi_pll_reg: ldo8 {
  440. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  441. regulator-min-microvolt = <1800000>;
  442. regulator-max-microvolt = <1800000>;
  443. };
  444. ldo9 {
  445. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  446. regulator-min-microvolt = <2850000>;
  447. regulator-max-microvolt = <2850000>;
  448. regulator-always-on;
  449. };
  450. ldo_rtc {
  451. regulator-name = "vdd_rtc_out,vdd_cell";
  452. regulator-min-microvolt = <3300000>;
  453. regulator-max-microvolt = <3300000>;
  454. regulator-always-on;
  455. };
  456. };
  457. };
  458. temperature-sensor@4c {
  459. compatible = "onnn,nct1008";
  460. reg = <0x4c>;
  461. };
  462. magnetometer@c {
  463. compatible = "ak,ak8975";
  464. reg = <0xc>;
  465. interrupt-parent = <&gpio>;
  466. interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
  467. };
  468. };
  469. pmc {
  470. nvidia,invert-interrupt;
  471. nvidia,suspend-mode = <2>;
  472. nvidia,cpu-pwr-good-time = <5000>;
  473. nvidia,cpu-pwr-off-time = <5000>;
  474. nvidia,core-pwr-good-time = <3845 3845>;
  475. nvidia,core-pwr-off-time = <3875>;
  476. nvidia,sys-clock-req-active-high;
  477. };
  478. memory-controller@7000f400 {
  479. emc-table@190000 {
  480. reg = <190000>;
  481. compatible = "nvidia,tegra20-emc-table";
  482. clock-frequency = <190000>;
  483. nvidia,emc-registers = <0x0000000c 0x00000026
  484. 0x00000009 0x00000003 0x00000004 0x00000004
  485. 0x00000002 0x0000000c 0x00000003 0x00000003
  486. 0x00000002 0x00000001 0x00000004 0x00000005
  487. 0x00000004 0x00000009 0x0000000d 0x0000059f
  488. 0x00000000 0x00000003 0x00000003 0x00000003
  489. 0x00000003 0x00000001 0x0000000b 0x000000c8
  490. 0x00000003 0x00000007 0x00000004 0x0000000f
  491. 0x00000002 0x00000000 0x00000000 0x00000002
  492. 0x00000000 0x00000000 0x00000083 0xa06204ae
  493. 0x007dc010 0x00000000 0x00000000 0x00000000
  494. 0x00000000 0x00000000 0x00000000 0x00000000>;
  495. };
  496. emc-table@380000 {
  497. reg = <380000>;
  498. compatible = "nvidia,tegra20-emc-table";
  499. clock-frequency = <380000>;
  500. nvidia,emc-registers = <0x00000017 0x0000004b
  501. 0x00000012 0x00000006 0x00000004 0x00000005
  502. 0x00000003 0x0000000c 0x00000006 0x00000006
  503. 0x00000003 0x00000001 0x00000004 0x00000005
  504. 0x00000004 0x00000009 0x0000000d 0x00000b5f
  505. 0x00000000 0x00000003 0x00000003 0x00000006
  506. 0x00000006 0x00000001 0x00000011 0x000000c8
  507. 0x00000003 0x0000000e 0x00000007 0x0000000f
  508. 0x00000002 0x00000000 0x00000000 0x00000002
  509. 0x00000000 0x00000000 0x00000083 0xe044048b
  510. 0x007d8010 0x00000000 0x00000000 0x00000000
  511. 0x00000000 0x00000000 0x00000000 0x00000000>;
  512. };
  513. };
  514. usb@c5000000 {
  515. status = "okay";
  516. nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  517. dr_mode = "otg";
  518. };
  519. usb-phy@c5000000 {
  520. status = "okay";
  521. vbus-supply = <&vbus_reg>;
  522. dr_mode = "otg";
  523. };
  524. usb@c5004000 {
  525. status = "okay";
  526. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  527. GPIO_ACTIVE_LOW>;
  528. };
  529. usb-phy@c5004000 {
  530. status = "okay";
  531. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  532. GPIO_ACTIVE_LOW>;
  533. };
  534. usb@c5008000 {
  535. status = "okay";
  536. };
  537. usb-phy@c5008000 {
  538. status = "okay";
  539. };
  540. sdhci@c8000000 {
  541. status = "okay";
  542. power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  543. bus-width = <4>;
  544. keep-power-in-suspend;
  545. };
  546. sdhci@c8000400 {
  547. status = "okay";
  548. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  549. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  550. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  551. bus-width = <4>;
  552. };
  553. sdhci@c8000600 {
  554. status = "okay";
  555. bus-width = <8>;
  556. non-removable;
  557. };
  558. clocks {
  559. compatible = "simple-bus";
  560. #address-cells = <1>;
  561. #size-cells = <0>;
  562. clk32k_in: clock {
  563. compatible = "fixed-clock";
  564. reg=<0>;
  565. #clock-cells = <0>;
  566. clock-frequency = <32768>;
  567. };
  568. };
  569. gpio-keys {
  570. compatible = "gpio-keys";
  571. power {
  572. label = "Power";
  573. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  574. linux,code = <116>; /* KEY_POWER */
  575. gpio-key,wakeup;
  576. };
  577. lid {
  578. label = "Lid";
  579. gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
  580. linux,input-type = <5>; /* EV_SW */
  581. linux,code = <0>; /* SW_LID */
  582. debounce-interval = <1>;
  583. gpio-key,wakeup;
  584. };
  585. };
  586. kbc {
  587. status = "okay";
  588. nvidia,debounce-delay-ms = <32>;
  589. nvidia,repeat-delay-ms = <160>;
  590. nvidia,ghost-filter;
  591. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  592. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  593. linux,keymap = <0x00020011 /* KEY_W */
  594. 0x0003001F /* KEY_S */
  595. 0x0004001E /* KEY_A */
  596. 0x0005002C /* KEY_Z */
  597. 0x000701d0 /* KEY_FN */
  598. 0x0107007D /* KEY_LEFTMETA */
  599. 0x02060064 /* KEY_RIGHTALT */
  600. 0x02070038 /* KEY_LEFTALT */
  601. 0x03000006 /* KEY_5 */
  602. 0x03010005 /* KEY_4 */
  603. 0x03020013 /* KEY_R */
  604. 0x03030012 /* KEY_E */
  605. 0x03040021 /* KEY_F */
  606. 0x03050020 /* KEY_D */
  607. 0x0306002D /* KEY_X */
  608. 0x04000008 /* KEY_7 */
  609. 0x04010007 /* KEY_6 */
  610. 0x04020014 /* KEY_T */
  611. 0x04030023 /* KEY_H */
  612. 0x04040022 /* KEY_G */
  613. 0x0405002F /* KEY_V */
  614. 0x0406002E /* KEY_C */
  615. 0x04070039 /* KEY_SPACE */
  616. 0x0500000A /* KEY_9 */
  617. 0x05010009 /* KEY_8 */
  618. 0x05020016 /* KEY_U */
  619. 0x05030015 /* KEY_Y */
  620. 0x05040024 /* KEY_J */
  621. 0x05050031 /* KEY_N */
  622. 0x05060030 /* KEY_B */
  623. 0x0507002B /* KEY_BACKSLASH */
  624. 0x0600000C /* KEY_MINUS */
  625. 0x0601000B /* KEY_0 */
  626. 0x06020018 /* KEY_O */
  627. 0x06030017 /* KEY_I */
  628. 0x06040026 /* KEY_L */
  629. 0x06050025 /* KEY_K */
  630. 0x06060033 /* KEY_COMMA */
  631. 0x06070032 /* KEY_M */
  632. 0x0701000D /* KEY_EQUAL */
  633. 0x0702001B /* KEY_RIGHTBRACE */
  634. 0x0703001C /* KEY_ENTER */
  635. 0x0707008B /* KEY_MENU */
  636. 0x08040036 /* KEY_RIGHTSHIFT */
  637. 0x0805002A /* KEY_LEFTSHIFT */
  638. 0x09050061 /* KEY_RIGHTCTRL */
  639. 0x0907001D /* KEY_LEFTCTRL */
  640. 0x0B00001A /* KEY_LEFTBRACE */
  641. 0x0B010019 /* KEY_P */
  642. 0x0B020028 /* KEY_APOSTROPHE */
  643. 0x0B030027 /* KEY_SEMICOLON */
  644. 0x0B040035 /* KEY_SLASH */
  645. 0x0B050034 /* KEY_DOT */
  646. 0x0C000044 /* KEY_F10 */
  647. 0x0C010043 /* KEY_F9 */
  648. 0x0C02000E /* KEY_BACKSPACE */
  649. 0x0C030004 /* KEY_3 */
  650. 0x0C040003 /* KEY_2 */
  651. 0x0C050067 /* KEY_UP */
  652. 0x0C0600D2 /* KEY_PRINT */
  653. 0x0C070077 /* KEY_PAUSE */
  654. 0x0D00006E /* KEY_INSERT */
  655. 0x0D01006F /* KEY_DELETE */
  656. 0x0D030068 /* KEY_PAGEUP */
  657. 0x0D04006D /* KEY_PAGEDOWN */
  658. 0x0D05006A /* KEY_RIGHT */
  659. 0x0D06006C /* KEY_DOWN */
  660. 0x0D070069 /* KEY_LEFT */
  661. 0x0E000057 /* KEY_F11 */
  662. 0x0E010058 /* KEY_F12 */
  663. 0x0E020042 /* KEY_F8 */
  664. 0x0E030010 /* KEY_Q */
  665. 0x0E04003E /* KEY_F4 */
  666. 0x0E05003D /* KEY_F3 */
  667. 0x0E060002 /* KEY_1 */
  668. 0x0E070041 /* KEY_F7 */
  669. 0x0F000001 /* KEY_ESC */
  670. 0x0F010029 /* KEY_GRAVE */
  671. 0x0F02003F /* KEY_F5 */
  672. 0x0F03000F /* KEY_TAB */
  673. 0x0F04003B /* KEY_F1 */
  674. 0x0F05003C /* KEY_F2 */
  675. 0x0F06003A /* KEY_CAPSLOCK */
  676. 0x0F070040 /* KEY_F6 */
  677. /* Software Handled Function Keys */
  678. 0x14000047 /* KEY_KP7 */
  679. 0x15000049 /* KEY_KP9 */
  680. 0x15010048 /* KEY_KP8 */
  681. 0x1502004B /* KEY_KP4 */
  682. 0x1504004F /* KEY_KP1 */
  683. 0x1601004E /* KEY_KPSLASH */
  684. 0x1602004D /* KEY_KP6 */
  685. 0x1603004C /* KEY_KP5 */
  686. 0x16040051 /* KEY_KP3 */
  687. 0x16050050 /* KEY_KP2 */
  688. 0x16070052 /* KEY_KP0 */
  689. 0x1B010037 /* KEY_KPASTERISK */
  690. 0x1B03004A /* KEY_KPMINUS */
  691. 0x1B04004E /* KEY_KPPLUS */
  692. 0x1B050053 /* KEY_KPDOT */
  693. 0x1C050073 /* KEY_VOLUMEUP */
  694. 0x1D030066 /* KEY_HOME */
  695. 0x1D04006B /* KEY_END */
  696. 0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
  697. 0x1D060072 /* KEY_VOLUMEDOWN */
  698. 0x1D0700E1 /* KEY_BRIGHTNESSUP */
  699. 0x1E000045 /* KEY_NUMLOCK */
  700. 0x1E010046 /* KEY_SCROLLLOCK */
  701. 0x1E020071 /* KEY_MUTE */
  702. 0x1F04008A>; /* KEY_HELP */
  703. };
  704. regulators {
  705. compatible = "simple-bus";
  706. #address-cells = <1>;
  707. #size-cells = <0>;
  708. vdd_5v0_reg: regulator@0 {
  709. compatible = "regulator-fixed";
  710. reg = <0>;
  711. regulator-name = "vdd_5v0";
  712. regulator-min-microvolt = <5000000>;
  713. regulator-max-microvolt = <5000000>;
  714. regulator-always-on;
  715. };
  716. regulator@1 {
  717. compatible = "regulator-fixed";
  718. reg = <1>;
  719. regulator-name = "vdd_1v5";
  720. regulator-min-microvolt = <1500000>;
  721. regulator-max-microvolt = <1500000>;
  722. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  723. };
  724. regulator@2 {
  725. compatible = "regulator-fixed";
  726. reg = <2>;
  727. regulator-name = "vdd_1v2";
  728. regulator-min-microvolt = <1200000>;
  729. regulator-max-microvolt = <1200000>;
  730. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  731. enable-active-high;
  732. };
  733. vbus_reg: regulator@3 {
  734. compatible = "regulator-fixed";
  735. reg = <3>;
  736. regulator-name = "vdd_vbus_wup1";
  737. regulator-min-microvolt = <5000000>;
  738. regulator-max-microvolt = <5000000>;
  739. enable-active-high;
  740. gpio = <&gpio 24 0>; /* PD0 */
  741. };
  742. };
  743. sound {
  744. compatible = "nvidia,tegra-audio-wm8903-seaboard",
  745. "nvidia,tegra-audio-wm8903";
  746. nvidia,model = "NVIDIA Tegra Seaboard";
  747. nvidia,audio-routing =
  748. "Headphone Jack", "HPOUTR",
  749. "Headphone Jack", "HPOUTL",
  750. "Int Spk", "ROP",
  751. "Int Spk", "RON",
  752. "Int Spk", "LOP",
  753. "Int Spk", "LON",
  754. "Mic Jack", "MICBIAS",
  755. "IN1R", "Mic Jack";
  756. nvidia,i2s-controller = <&tegra_i2s1>;
  757. nvidia,audio-codec = <&wm8903>;
  758. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  759. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
  760. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  761. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  762. <&tegra_car TEGRA20_CLK_CDEV1>;
  763. clock-names = "pll_a", "pll_a_out0", "mclk";
  764. };
  765. };