tegra20-paz00.dts 12 KB

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  1. /dts-v1/;
  2. #include "tegra20.dtsi"
  3. / {
  4. model = "Toshiba AC100 / Dynabook AZ";
  5. compatible = "compal,paz00", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x20000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  16. GPIO_ACTIVE_HIGH>;
  17. };
  18. };
  19. pinmux {
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&state_default>;
  22. state_default: pinmux {
  23. ata {
  24. nvidia,pins = "ata", "atc", "atd", "ate",
  25. "dap2", "gmb", "gmc", "gmd", "spia",
  26. "spib", "spic", "spid", "spie";
  27. nvidia,function = "gmi";
  28. };
  29. atb {
  30. nvidia,pins = "atb", "gma", "gme";
  31. nvidia,function = "sdio4";
  32. };
  33. cdev1 {
  34. nvidia,pins = "cdev1";
  35. nvidia,function = "plla_out";
  36. };
  37. cdev2 {
  38. nvidia,pins = "cdev2";
  39. nvidia,function = "pllp_out4";
  40. };
  41. crtp {
  42. nvidia,pins = "crtp";
  43. nvidia,function = "crt";
  44. };
  45. csus {
  46. nvidia,pins = "csus";
  47. nvidia,function = "pllc_out1";
  48. };
  49. dap1 {
  50. nvidia,pins = "dap1";
  51. nvidia,function = "dap1";
  52. };
  53. dap3 {
  54. nvidia,pins = "dap3";
  55. nvidia,function = "dap3";
  56. };
  57. dap4 {
  58. nvidia,pins = "dap4";
  59. nvidia,function = "dap4";
  60. };
  61. ddc {
  62. nvidia,pins = "ddc";
  63. nvidia,function = "i2c2";
  64. };
  65. dta {
  66. nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
  67. nvidia,function = "rsvd1";
  68. };
  69. dtf {
  70. nvidia,pins = "dtf";
  71. nvidia,function = "i2c3";
  72. };
  73. gpu {
  74. nvidia,pins = "gpu", "sdb", "sdd";
  75. nvidia,function = "pwm";
  76. };
  77. gpu7 {
  78. nvidia,pins = "gpu7";
  79. nvidia,function = "rtck";
  80. };
  81. gpv {
  82. nvidia,pins = "gpv", "slxa", "slxk";
  83. nvidia,function = "pcie";
  84. };
  85. hdint {
  86. nvidia,pins = "hdint", "pta";
  87. nvidia,function = "hdmi";
  88. };
  89. i2cp {
  90. nvidia,pins = "i2cp";
  91. nvidia,function = "i2cp";
  92. };
  93. irrx {
  94. nvidia,pins = "irrx", "irtx";
  95. nvidia,function = "uarta";
  96. };
  97. kbca {
  98. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  99. nvidia,function = "kbc";
  100. };
  101. kbcb {
  102. nvidia,pins = "kbcb", "kbcd";
  103. nvidia,function = "sdio2";
  104. };
  105. lcsn {
  106. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  107. "ld3", "ld4", "ld5", "ld6", "ld7",
  108. "ld8", "ld9", "ld10", "ld11", "ld12",
  109. "ld13", "ld14", "ld15", "ld16", "ld17",
  110. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  111. "lhs", "lm0", "lm1", "lpp", "lpw0",
  112. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  113. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  114. "lvs";
  115. nvidia,function = "displaya";
  116. };
  117. owc {
  118. nvidia,pins = "owc";
  119. nvidia,function = "owr";
  120. };
  121. pmc {
  122. nvidia,pins = "pmc";
  123. nvidia,function = "pwr_on";
  124. };
  125. rm {
  126. nvidia,pins = "rm";
  127. nvidia,function = "i2c1";
  128. };
  129. sdc {
  130. nvidia,pins = "sdc";
  131. nvidia,function = "twc";
  132. };
  133. sdio1 {
  134. nvidia,pins = "sdio1";
  135. nvidia,function = "sdio1";
  136. };
  137. slxc {
  138. nvidia,pins = "slxc", "slxd";
  139. nvidia,function = "spi4";
  140. };
  141. spdi {
  142. nvidia,pins = "spdi", "spdo";
  143. nvidia,function = "rsvd2";
  144. };
  145. spif {
  146. nvidia,pins = "spif", "uac";
  147. nvidia,function = "rsvd4";
  148. };
  149. spig {
  150. nvidia,pins = "spig", "spih";
  151. nvidia,function = "spi2_alt";
  152. };
  153. uaa {
  154. nvidia,pins = "uaa", "uab", "uda";
  155. nvidia,function = "ulpi";
  156. };
  157. uad {
  158. nvidia,pins = "uad";
  159. nvidia,function = "spdif";
  160. };
  161. uca {
  162. nvidia,pins = "uca", "ucb";
  163. nvidia,function = "uartc";
  164. };
  165. conf_ata {
  166. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  167. "cdev1", "cdev2", "dap1", "dap2", "dtf",
  168. "gma", "gmb", "gmc", "gmd", "gme",
  169. "gpu", "gpu7", "gpv", "i2cp", "pta",
  170. "rm", "sdio1", "slxk", "spdo", "uac",
  171. "uda";
  172. nvidia,pull = <0>;
  173. nvidia,tristate = <0>;
  174. };
  175. conf_ck32 {
  176. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  177. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  178. nvidia,pull = <0>;
  179. };
  180. conf_crtp {
  181. nvidia,pins = "crtp", "dap3", "dap4", "dtb",
  182. "dtc", "dte", "slxa", "slxc", "slxd",
  183. "spdi";
  184. nvidia,pull = <0>;
  185. nvidia,tristate = <1>;
  186. };
  187. conf_csus {
  188. nvidia,pins = "csus", "spia", "spib", "spid",
  189. "spif";
  190. nvidia,pull = <1>;
  191. nvidia,tristate = <1>;
  192. };
  193. conf_ddc {
  194. nvidia,pins = "ddc", "irrx", "irtx", "kbca",
  195. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  196. "spic", "spig", "uaa", "uab";
  197. nvidia,pull = <2>;
  198. nvidia,tristate = <0>;
  199. };
  200. conf_dta {
  201. nvidia,pins = "dta", "dtd", "owc", "sdc", "sdd",
  202. "spie", "spih", "uad", "uca", "ucb";
  203. nvidia,pull = <2>;
  204. nvidia,tristate = <1>;
  205. };
  206. conf_hdint {
  207. nvidia,pins = "hdint", "ld0", "ld1", "ld2",
  208. "ld3", "ld4", "ld5", "ld6", "ld7",
  209. "ld8", "ld9", "ld10", "ld11", "ld12",
  210. "ld13", "ld14", "ld15", "ld16", "ld17",
  211. "ldc", "ldi", "lhs", "lsc0", "lspi",
  212. "lvs", "pmc";
  213. nvidia,tristate = <0>;
  214. };
  215. conf_lc {
  216. nvidia,pins = "lc", "ls";
  217. nvidia,pull = <2>;
  218. };
  219. conf_lcsn {
  220. nvidia,pins = "lcsn", "lhp0", "lhp1", "lhp2",
  221. "lm0", "lm1", "lpp", "lpw0", "lpw1",
  222. "lpw2", "lsc1", "lsck", "lsda", "lsdi",
  223. "lvp0", "lvp1", "sdb";
  224. nvidia,tristate = <1>;
  225. };
  226. conf_ld17_0 {
  227. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  228. "ld23_22";
  229. nvidia,pull = <1>;
  230. };
  231. };
  232. };
  233. i2s@70002800 {
  234. status = "okay";
  235. };
  236. serial@70006000 {
  237. status = "okay";
  238. };
  239. serial@70006200 {
  240. status = "okay";
  241. };
  242. i2c@7000c000 {
  243. status = "okay";
  244. clock-frequency = <400000>;
  245. alc5632: alc5632@1e {
  246. compatible = "realtek,alc5632";
  247. reg = <0x1e>;
  248. gpio-controller;
  249. #gpio-cells = <2>;
  250. };
  251. };
  252. hdmi_ddc: i2c@7000c400 {
  253. status = "okay";
  254. clock-frequency = <100000>;
  255. };
  256. nvec {
  257. compatible = "nvidia,nvec";
  258. reg = <0x7000c500 0x100>;
  259. interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
  260. #address-cells = <1>;
  261. #size-cells = <0>;
  262. clock-frequency = <80000>;
  263. request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
  264. slave-addr = <138>;
  265. clocks = <&tegra_car TEGRA20_CLK_I2C3>,
  266. <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
  267. clock-names = "div-clk", "fast-clk";
  268. };
  269. i2c@7000d000 {
  270. status = "okay";
  271. clock-frequency = <400000>;
  272. pmic: tps6586x@34 {
  273. compatible = "ti,tps6586x";
  274. reg = <0x34>;
  275. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  276. #gpio-cells = <2>;
  277. gpio-controller;
  278. sys-supply = <&p5valw_reg>;
  279. vin-sm0-supply = <&sys_reg>;
  280. vin-sm1-supply = <&sys_reg>;
  281. vin-sm2-supply = <&sys_reg>;
  282. vinldo01-supply = <&sm2_reg>;
  283. vinldo23-supply = <&sm2_reg>;
  284. vinldo4-supply = <&sm2_reg>;
  285. vinldo678-supply = <&sm2_reg>;
  286. vinldo9-supply = <&sm2_reg>;
  287. regulators {
  288. sys_reg: sys {
  289. regulator-name = "vdd_sys";
  290. regulator-always-on;
  291. };
  292. sm0 {
  293. regulator-name = "+1.2vs_sm0,vdd_core";
  294. regulator-min-microvolt = <1200000>;
  295. regulator-max-microvolt = <1200000>;
  296. regulator-always-on;
  297. };
  298. sm1 {
  299. regulator-name = "+1.0vs_sm1,vdd_cpu";
  300. regulator-min-microvolt = <1000000>;
  301. regulator-max-microvolt = <1000000>;
  302. regulator-always-on;
  303. };
  304. sm2_reg: sm2 {
  305. regulator-name = "+3.7vs_sm2,vin_ldo*";
  306. regulator-min-microvolt = <3700000>;
  307. regulator-max-microvolt = <3700000>;
  308. regulator-always-on;
  309. };
  310. /* LDO0 is not connected to anything */
  311. ldo1 {
  312. regulator-name = "+1.1vs_ldo1,avdd_pll*";
  313. regulator-min-microvolt = <1100000>;
  314. regulator-max-microvolt = <1100000>;
  315. regulator-always-on;
  316. };
  317. ldo2 {
  318. regulator-name = "+1.2vs_ldo2,vdd_rtc";
  319. regulator-min-microvolt = <1200000>;
  320. regulator-max-microvolt = <1200000>;
  321. };
  322. ldo3 {
  323. regulator-name = "+3.3vs_ldo3,avdd_usb*";
  324. regulator-min-microvolt = <3300000>;
  325. regulator-max-microvolt = <3300000>;
  326. regulator-always-on;
  327. };
  328. ldo4 {
  329. regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
  330. regulator-min-microvolt = <1800000>;
  331. regulator-max-microvolt = <1800000>;
  332. regulator-always-on;
  333. };
  334. ldo5 {
  335. regulator-name = "+2.85vs_ldo5,vcore_mmc";
  336. regulator-min-microvolt = <2850000>;
  337. regulator-max-microvolt = <2850000>;
  338. regulator-always-on;
  339. };
  340. ldo6 {
  341. /*
  342. * Research indicates this should be
  343. * 1.8v; other boards that use this
  344. * rail for the same purpose need it
  345. * set to 1.8v. The schematic signal
  346. * name is incorrect; perhaps copied
  347. * from an incorrect NVIDIA reference.
  348. */
  349. regulator-name = "+2.85vs_ldo6,avdd_vdac";
  350. regulator-min-microvolt = <1800000>;
  351. regulator-max-microvolt = <1800000>;
  352. };
  353. hdmi_vdd_reg: ldo7 {
  354. regulator-name = "+3.3vs_ldo7,avdd_hdmi";
  355. regulator-min-microvolt = <3300000>;
  356. regulator-max-microvolt = <3300000>;
  357. };
  358. hdmi_pll_reg: ldo8 {
  359. regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
  360. regulator-min-microvolt = <1800000>;
  361. regulator-max-microvolt = <1800000>;
  362. };
  363. ldo9 {
  364. regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
  365. regulator-min-microvolt = <2850000>;
  366. regulator-max-microvolt = <2850000>;
  367. regulator-always-on;
  368. };
  369. ldo_rtc {
  370. regulator-name = "+3.3vs_rtc";
  371. regulator-min-microvolt = <3300000>;
  372. regulator-max-microvolt = <3300000>;
  373. regulator-always-on;
  374. };
  375. };
  376. };
  377. adt7461@4c {
  378. compatible = "adi,adt7461";
  379. reg = <0x4c>;
  380. };
  381. };
  382. pmc {
  383. nvidia,invert-interrupt;
  384. nvidia,suspend-mode = <2>;
  385. nvidia,cpu-pwr-good-time = <2000>;
  386. nvidia,cpu-pwr-off-time = <0>;
  387. nvidia,core-pwr-good-time = <3845 3845>;
  388. nvidia,core-pwr-off-time = <0>;
  389. nvidia,sys-clock-req-active-high;
  390. };
  391. usb@c5000000 {
  392. status = "okay";
  393. };
  394. usb-phy@c5000000 {
  395. status = "okay";
  396. };
  397. usb@c5004000 {
  398. status = "okay";
  399. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  400. GPIO_ACTIVE_LOW>;
  401. };
  402. usb-phy@c5004000 {
  403. status = "okay";
  404. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
  405. GPIO_ACTIVE_LOW>;
  406. };
  407. usb@c5008000 {
  408. status = "okay";
  409. };
  410. usb-phy@c5008000 {
  411. status = "okay";
  412. };
  413. sdhci@c8000000 {
  414. status = "okay";
  415. cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
  416. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  417. power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
  418. bus-width = <4>;
  419. };
  420. sdhci@c8000600 {
  421. status = "okay";
  422. bus-width = <8>;
  423. non-removable;
  424. };
  425. clocks {
  426. compatible = "simple-bus";
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. clk32k_in: clock {
  430. compatible = "fixed-clock";
  431. reg=<0>;
  432. #clock-cells = <0>;
  433. clock-frequency = <32768>;
  434. };
  435. };
  436. gpio-keys {
  437. compatible = "gpio-keys";
  438. power {
  439. label = "Power";
  440. gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
  441. linux,code = <116>; /* KEY_POWER */
  442. gpio-key,wakeup;
  443. };
  444. };
  445. gpio-leds {
  446. compatible = "gpio-leds";
  447. wifi {
  448. label = "wifi-led";
  449. gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  450. linux,default-trigger = "rfkill0";
  451. };
  452. };
  453. regulators {
  454. compatible = "simple-bus";
  455. #address-cells = <1>;
  456. #size-cells = <0>;
  457. p5valw_reg: regulator@0 {
  458. compatible = "regulator-fixed";
  459. reg = <0>;
  460. regulator-name = "+5valw";
  461. regulator-min-microvolt = <5000000>;
  462. regulator-max-microvolt = <5000000>;
  463. regulator-always-on;
  464. };
  465. };
  466. sound {
  467. compatible = "nvidia,tegra-audio-alc5632-paz00",
  468. "nvidia,tegra-audio-alc5632";
  469. nvidia,model = "Compal PAZ00";
  470. nvidia,audio-routing =
  471. "Int Spk", "SPKOUT",
  472. "Int Spk", "SPKOUTN",
  473. "Headset Mic", "MICBIAS1",
  474. "MIC1", "Headset Mic",
  475. "Headset Stereophone", "HPR",
  476. "Headset Stereophone", "HPL",
  477. "DMICDAT", "Digital Mic";
  478. nvidia,audio-codec = <&alc5632>;
  479. nvidia,i2s-controller = <&tegra_i2s1>;
  480. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  481. GPIO_ACTIVE_HIGH>;
  482. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  483. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  484. <&tegra_car TEGRA20_CLK_CDEV1>;
  485. clock-names = "pll_a", "pll_a_out0", "mclk";
  486. };
  487. };