tegra20-harmony.dts 16 KB

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  1. /dts-v1/;
  2. #include "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra20 Harmony evaluation board";
  5. compatible = "nvidia,harmony", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x40000000>;
  8. };
  9. host1x {
  10. hdmi {
  11. status = "okay";
  12. vdd-supply = <&hdmi_vdd_reg>;
  13. pll-supply = <&hdmi_pll_reg>;
  14. nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  15. nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  16. GPIO_ACTIVE_HIGH>;
  17. };
  18. };
  19. pinmux {
  20. pinctrl-names = "default";
  21. pinctrl-0 = <&state_default>;
  22. state_default: pinmux {
  23. ata {
  24. nvidia,pins = "ata";
  25. nvidia,function = "ide";
  26. };
  27. atb {
  28. nvidia,pins = "atb", "gma", "gme";
  29. nvidia,function = "sdio4";
  30. };
  31. atc {
  32. nvidia,pins = "atc";
  33. nvidia,function = "nand";
  34. };
  35. atd {
  36. nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  37. "spia", "spib", "spic";
  38. nvidia,function = "gmi";
  39. };
  40. cdev1 {
  41. nvidia,pins = "cdev1";
  42. nvidia,function = "plla_out";
  43. };
  44. cdev2 {
  45. nvidia,pins = "cdev2";
  46. nvidia,function = "pllp_out4";
  47. };
  48. crtp {
  49. nvidia,pins = "crtp";
  50. nvidia,function = "crt";
  51. };
  52. csus {
  53. nvidia,pins = "csus";
  54. nvidia,function = "vi_sensor_clk";
  55. };
  56. dap1 {
  57. nvidia,pins = "dap1";
  58. nvidia,function = "dap1";
  59. };
  60. dap2 {
  61. nvidia,pins = "dap2";
  62. nvidia,function = "dap2";
  63. };
  64. dap3 {
  65. nvidia,pins = "dap3";
  66. nvidia,function = "dap3";
  67. };
  68. dap4 {
  69. nvidia,pins = "dap4";
  70. nvidia,function = "dap4";
  71. };
  72. ddc {
  73. nvidia,pins = "ddc";
  74. nvidia,function = "i2c2";
  75. };
  76. dta {
  77. nvidia,pins = "dta", "dtd";
  78. nvidia,function = "sdio2";
  79. };
  80. dtb {
  81. nvidia,pins = "dtb", "dtc", "dte";
  82. nvidia,function = "rsvd1";
  83. };
  84. dtf {
  85. nvidia,pins = "dtf";
  86. nvidia,function = "i2c3";
  87. };
  88. gmc {
  89. nvidia,pins = "gmc";
  90. nvidia,function = "uartd";
  91. };
  92. gpu7 {
  93. nvidia,pins = "gpu7";
  94. nvidia,function = "rtck";
  95. };
  96. gpv {
  97. nvidia,pins = "gpv", "slxa", "slxk";
  98. nvidia,function = "pcie";
  99. };
  100. hdint {
  101. nvidia,pins = "hdint", "pta";
  102. nvidia,function = "hdmi";
  103. };
  104. i2cp {
  105. nvidia,pins = "i2cp";
  106. nvidia,function = "i2cp";
  107. };
  108. irrx {
  109. nvidia,pins = "irrx", "irtx";
  110. nvidia,function = "uarta";
  111. };
  112. kbca {
  113. nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
  114. "kbce", "kbcf";
  115. nvidia,function = "kbc";
  116. };
  117. lcsn {
  118. nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
  119. "ld3", "ld4", "ld5", "ld6", "ld7",
  120. "ld8", "ld9", "ld10", "ld11", "ld12",
  121. "ld13", "ld14", "ld15", "ld16", "ld17",
  122. "ldc", "ldi", "lhp0", "lhp1", "lhp2",
  123. "lhs", "lm0", "lm1", "lpp", "lpw0",
  124. "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
  125. "lsda", "lsdi", "lspi", "lvp0", "lvp1",
  126. "lvs";
  127. nvidia,function = "displaya";
  128. };
  129. owc {
  130. nvidia,pins = "owc", "spdi", "spdo", "uac";
  131. nvidia,function = "rsvd2";
  132. };
  133. pmc {
  134. nvidia,pins = "pmc";
  135. nvidia,function = "pwr_on";
  136. };
  137. rm {
  138. nvidia,pins = "rm";
  139. nvidia,function = "i2c1";
  140. };
  141. sdb {
  142. nvidia,pins = "sdb", "sdc", "sdd";
  143. nvidia,function = "pwm";
  144. };
  145. sdio1 {
  146. nvidia,pins = "sdio1";
  147. nvidia,function = "sdio1";
  148. };
  149. slxc {
  150. nvidia,pins = "slxc", "slxd";
  151. nvidia,function = "spdif";
  152. };
  153. spid {
  154. nvidia,pins = "spid", "spie", "spif";
  155. nvidia,function = "spi1";
  156. };
  157. spig {
  158. nvidia,pins = "spig", "spih";
  159. nvidia,function = "spi2_alt";
  160. };
  161. uaa {
  162. nvidia,pins = "uaa", "uab", "uda";
  163. nvidia,function = "ulpi";
  164. };
  165. uad {
  166. nvidia,pins = "uad";
  167. nvidia,function = "irda";
  168. };
  169. uca {
  170. nvidia,pins = "uca", "ucb";
  171. nvidia,function = "uartc";
  172. };
  173. conf_ata {
  174. nvidia,pins = "ata", "atb", "atc", "atd", "ate",
  175. "cdev1", "cdev2", "dap1", "dtb", "gma",
  176. "gmb", "gmc", "gmd", "gme", "gpu7",
  177. "gpv", "i2cp", "pta", "rm", "slxa",
  178. "slxk", "spia", "spib", "uac";
  179. nvidia,pull = <0>;
  180. nvidia,tristate = <0>;
  181. };
  182. conf_ck32 {
  183. nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
  184. "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
  185. nvidia,pull = <0>;
  186. };
  187. conf_csus {
  188. nvidia,pins = "csus", "spid", "spif";
  189. nvidia,pull = <1>;
  190. nvidia,tristate = <1>;
  191. };
  192. conf_crtp {
  193. nvidia,pins = "crtp", "dap2", "dap3", "dap4",
  194. "dtc", "dte", "dtf", "gpu", "sdio1",
  195. "slxc", "slxd", "spdi", "spdo", "spig",
  196. "uda";
  197. nvidia,pull = <0>;
  198. nvidia,tristate = <1>;
  199. };
  200. conf_ddc {
  201. nvidia,pins = "ddc", "dta", "dtd", "kbca",
  202. "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
  203. "sdc";
  204. nvidia,pull = <2>;
  205. nvidia,tristate = <0>;
  206. };
  207. conf_hdint {
  208. nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
  209. "lpw1", "lsc1", "lsck", "lsda", "lsdi",
  210. "lvp0", "owc", "sdb";
  211. nvidia,tristate = <1>;
  212. };
  213. conf_irrx {
  214. nvidia,pins = "irrx", "irtx", "sdd", "spic",
  215. "spie", "spih", "uaa", "uab", "uad",
  216. "uca", "ucb";
  217. nvidia,pull = <2>;
  218. nvidia,tristate = <1>;
  219. };
  220. conf_lc {
  221. nvidia,pins = "lc", "ls";
  222. nvidia,pull = <2>;
  223. };
  224. conf_ld0 {
  225. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  226. "ld5", "ld6", "ld7", "ld8", "ld9",
  227. "ld10", "ld11", "ld12", "ld13", "ld14",
  228. "ld15", "ld16", "ld17", "ldi", "lhp0",
  229. "lhp1", "lhp2", "lhs", "lm0", "lpp",
  230. "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
  231. "lvs", "pmc";
  232. nvidia,tristate = <0>;
  233. };
  234. conf_ld17_0 {
  235. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  236. "ld23_22";
  237. nvidia,pull = <1>;
  238. };
  239. };
  240. };
  241. i2s@70002800 {
  242. status = "okay";
  243. };
  244. serial@70006300 {
  245. status = "okay";
  246. };
  247. i2c@7000c000 {
  248. status = "okay";
  249. clock-frequency = <400000>;
  250. wm8903: wm8903@1a {
  251. compatible = "wlf,wm8903";
  252. reg = <0x1a>;
  253. interrupt-parent = <&gpio>;
  254. interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
  255. gpio-controller;
  256. #gpio-cells = <2>;
  257. micdet-cfg = <0>;
  258. micdet-delay = <100>;
  259. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  260. };
  261. };
  262. hdmi_ddc: i2c@7000c400 {
  263. status = "okay";
  264. clock-frequency = <100000>;
  265. };
  266. i2c@7000c500 {
  267. status = "okay";
  268. clock-frequency = <400000>;
  269. };
  270. i2c@7000d000 {
  271. status = "okay";
  272. clock-frequency = <400000>;
  273. pmic: tps6586x@34 {
  274. compatible = "ti,tps6586x";
  275. reg = <0x34>;
  276. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  277. ti,system-power-controller;
  278. #gpio-cells = <2>;
  279. gpio-controller;
  280. sys-supply = <&vdd_5v0_reg>;
  281. vin-sm0-supply = <&sys_reg>;
  282. vin-sm1-supply = <&sys_reg>;
  283. vin-sm2-supply = <&sys_reg>;
  284. vinldo01-supply = <&sm2_reg>;
  285. vinldo23-supply = <&sm2_reg>;
  286. vinldo4-supply = <&sm2_reg>;
  287. vinldo678-supply = <&sm2_reg>;
  288. vinldo9-supply = <&sm2_reg>;
  289. regulators {
  290. sys_reg: sys {
  291. regulator-name = "vdd_sys";
  292. regulator-always-on;
  293. };
  294. sm0 {
  295. regulator-name = "vdd_sm0,vdd_core";
  296. regulator-min-microvolt = <1200000>;
  297. regulator-max-microvolt = <1200000>;
  298. regulator-always-on;
  299. };
  300. sm1 {
  301. regulator-name = "vdd_sm1,vdd_cpu";
  302. regulator-min-microvolt = <1000000>;
  303. regulator-max-microvolt = <1000000>;
  304. regulator-always-on;
  305. };
  306. sm2_reg: sm2 {
  307. regulator-name = "vdd_sm2,vin_ldo*";
  308. regulator-min-microvolt = <3700000>;
  309. regulator-max-microvolt = <3700000>;
  310. regulator-always-on;
  311. };
  312. ldo0 {
  313. regulator-name = "vdd_ldo0,vddio_pex_clk";
  314. regulator-min-microvolt = <3300000>;
  315. regulator-max-microvolt = <3300000>;
  316. };
  317. ldo1 {
  318. regulator-name = "vdd_ldo1,avdd_pll*";
  319. regulator-min-microvolt = <1100000>;
  320. regulator-max-microvolt = <1100000>;
  321. regulator-always-on;
  322. };
  323. ldo2 {
  324. regulator-name = "vdd_ldo2,vdd_rtc";
  325. regulator-min-microvolt = <1200000>;
  326. regulator-max-microvolt = <1200000>;
  327. };
  328. ldo3 {
  329. regulator-name = "vdd_ldo3,avdd_usb*";
  330. regulator-min-microvolt = <3300000>;
  331. regulator-max-microvolt = <3300000>;
  332. regulator-always-on;
  333. };
  334. ldo4 {
  335. regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
  336. regulator-min-microvolt = <1800000>;
  337. regulator-max-microvolt = <1800000>;
  338. regulator-always-on;
  339. };
  340. ldo5 {
  341. regulator-name = "vdd_ldo5,vcore_mmc";
  342. regulator-min-microvolt = <2850000>;
  343. regulator-max-microvolt = <2850000>;
  344. regulator-always-on;
  345. };
  346. ldo6 {
  347. regulator-name = "vdd_ldo6,avdd_vdac";
  348. regulator-min-microvolt = <1800000>;
  349. regulator-max-microvolt = <1800000>;
  350. };
  351. hdmi_vdd_reg: ldo7 {
  352. regulator-name = "vdd_ldo7,avdd_hdmi";
  353. regulator-min-microvolt = <3300000>;
  354. regulator-max-microvolt = <3300000>;
  355. };
  356. hdmi_pll_reg: ldo8 {
  357. regulator-name = "vdd_ldo8,avdd_hdmi_pll";
  358. regulator-min-microvolt = <1800000>;
  359. regulator-max-microvolt = <1800000>;
  360. };
  361. ldo9 {
  362. regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
  363. regulator-min-microvolt = <2850000>;
  364. regulator-max-microvolt = <2850000>;
  365. regulator-always-on;
  366. };
  367. ldo_rtc {
  368. regulator-name = "vdd_rtc_out,vdd_cell";
  369. regulator-min-microvolt = <3300000>;
  370. regulator-max-microvolt = <3300000>;
  371. regulator-always-on;
  372. };
  373. };
  374. };
  375. temperature-sensor@4c {
  376. compatible = "adi,adt7461";
  377. reg = <0x4c>;
  378. };
  379. };
  380. pmc {
  381. nvidia,invert-interrupt;
  382. nvidia,suspend-mode = <2>;
  383. nvidia,cpu-pwr-good-time = <5000>;
  384. nvidia,cpu-pwr-off-time = <5000>;
  385. nvidia,core-pwr-good-time = <3845 3845>;
  386. nvidia,core-pwr-off-time = <3875>;
  387. nvidia,sys-clock-req-active-high;
  388. };
  389. usb@c5000000 {
  390. status = "okay";
  391. };
  392. usb-phy@c5000000 {
  393. status = "okay";
  394. };
  395. usb@c5004000 {
  396. status = "okay";
  397. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  398. GPIO_ACTIVE_LOW>;
  399. };
  400. usb-phy@c5004000 {
  401. status = "okay";
  402. nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
  403. GPIO_ACTIVE_LOW>;
  404. };
  405. usb@c5008000 {
  406. status = "okay";
  407. };
  408. usb-phy@c5008000 {
  409. status = "okay";
  410. };
  411. sdhci@c8000200 {
  412. status = "okay";
  413. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  414. wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
  415. power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  416. bus-width = <4>;
  417. };
  418. sdhci@c8000600 {
  419. status = "okay";
  420. cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
  421. wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
  422. power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
  423. bus-width = <8>;
  424. };
  425. clocks {
  426. compatible = "simple-bus";
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. clk32k_in: clock {
  430. compatible = "fixed-clock";
  431. reg=<0>;
  432. #clock-cells = <0>;
  433. clock-frequency = <32768>;
  434. };
  435. };
  436. gpio-keys {
  437. compatible = "gpio-keys";
  438. power {
  439. label = "Power";
  440. gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  441. linux,code = <116>; /* KEY_POWER */
  442. gpio-key,wakeup;
  443. };
  444. };
  445. kbc {
  446. status = "okay";
  447. nvidia,debounce-delay-ms = <2>;
  448. nvidia,repeat-delay-ms = <160>;
  449. nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  450. nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
  451. linux,keymap = <0x00020011 /* KEY_W */
  452. 0x0003001F /* KEY_S */
  453. 0x0004001E /* KEY_A */
  454. 0x0005002C /* KEY_Z */
  455. 0x000701D0 /* KEY_FN */
  456. 0x0107008B /* KEY_MENU */
  457. 0x02060038 /* KEY_LEFTALT */
  458. 0x02070064 /* KEY_RIGHTALT */
  459. 0x03000006 /* KEY_5 */
  460. 0x03010005 /* KEY_4 */
  461. 0x03020013 /* KEY_R */
  462. 0x03030012 /* KEY_E */
  463. 0x03040021 /* KEY_F */
  464. 0x03050020 /* KEY_D */
  465. 0x0306002D /* KEY_X */
  466. 0x04000008 /* KEY_7 */
  467. 0x04010007 /* KEY_6 */
  468. 0x04020014 /* KEY_T */
  469. 0x04030023 /* KEY_H */
  470. 0x04040022 /* KEY_G */
  471. 0x0405002F /* KEY_V */
  472. 0x0406002E /* KEY_C */
  473. 0x04070039 /* KEY_SPACE */
  474. 0x0500000A /* KEY_9 */
  475. 0x05010009 /* KEY_8 */
  476. 0x05020016 /* KEY_U */
  477. 0x05030015 /* KEY_Y */
  478. 0x05040024 /* KEY_J */
  479. 0x05050031 /* KEY_N */
  480. 0x05060030 /* KEY_B */
  481. 0x0507002B /* KEY_BACKSLASH */
  482. 0x0600000C /* KEY_MINUS */
  483. 0x0601000B /* KEY_0 */
  484. 0x06020018 /* KEY_O */
  485. 0x06030017 /* KEY_I */
  486. 0x06040026 /* KEY_L */
  487. 0x06050025 /* KEY_K */
  488. 0x06060033 /* KEY_COMMA */
  489. 0x06070032 /* KEY_M */
  490. 0x0701000D /* KEY_EQUAL */
  491. 0x0702001B /* KEY_RIGHTBRACE */
  492. 0x0703001C /* KEY_ENTER */
  493. 0x0707008B /* KEY_MENU */
  494. 0x0804002A /* KEY_LEFTSHIFT */
  495. 0x08050036 /* KEY_RIGHTSHIFT */
  496. 0x0905001D /* KEY_LEFTCTRL */
  497. 0x09070061 /* KEY_RIGHTCTRL */
  498. 0x0B00001A /* KEY_LEFTBRACE */
  499. 0x0B010019 /* KEY_P */
  500. 0x0B020028 /* KEY_APOSTROPHE */
  501. 0x0B030027 /* KEY_SEMICOLON */
  502. 0x0B040035 /* KEY_SLASH */
  503. 0x0B050034 /* KEY_DOT */
  504. 0x0C000044 /* KEY_F10 */
  505. 0x0C010043 /* KEY_F9 */
  506. 0x0C02000E /* KEY_BACKSPACE */
  507. 0x0C030004 /* KEY_3 */
  508. 0x0C040003 /* KEY_2 */
  509. 0x0C050067 /* KEY_UP */
  510. 0x0C0600D2 /* KEY_PRINT */
  511. 0x0C070077 /* KEY_PAUSE */
  512. 0x0D00006E /* KEY_INSERT */
  513. 0x0D01006F /* KEY_DELETE */
  514. 0x0D030068 /* KEY_PAGEUP */
  515. 0x0D04006D /* KEY_PAGEDOWN */
  516. 0x0D05006A /* KEY_RIGHT */
  517. 0x0D06006C /* KEY_DOWN */
  518. 0x0D070069 /* KEY_LEFT */
  519. 0x0E000057 /* KEY_F11 */
  520. 0x0E010058 /* KEY_F12 */
  521. 0x0E020042 /* KEY_F8 */
  522. 0x0E030010 /* KEY_Q */
  523. 0x0E04003E /* KEY_F4 */
  524. 0x0E05003D /* KEY_F3 */
  525. 0x0E060002 /* KEY_1 */
  526. 0x0E070041 /* KEY_F7 */
  527. 0x0F000001 /* KEY_ESC */
  528. 0x0F010029 /* KEY_GRAVE */
  529. 0x0F02003F /* KEY_F5 */
  530. 0x0F03000F /* KEY_TAB */
  531. 0x0F04003B /* KEY_F1 */
  532. 0x0F05003C /* KEY_F2 */
  533. 0x0F06003A /* KEY_CAPSLOCK */
  534. 0x0F070040 /* KEY_F6 */
  535. 0x14000047 /* KEY_KP7 */
  536. 0x15000049 /* KEY_KP9 */
  537. 0x15010048 /* KEY_KP8 */
  538. 0x1502004B /* KEY_KP4 */
  539. 0x1504004F /* KEY_KP1 */
  540. 0x1601004E /* KEY_KPSLASH */
  541. 0x1602004D /* KEY_KP6 */
  542. 0x1603004C /* KEY_KP5 */
  543. 0x16040051 /* KEY_KP3 */
  544. 0x16050050 /* KEY_KP2 */
  545. 0x16070052 /* KEY_KP0 */
  546. 0x1B010037 /* KEY_KPASTERISK */
  547. 0x1B03004A /* KEY_KPMINUS */
  548. 0x1B04004E /* KEY_KPPLUS */
  549. 0x1B050053 /* KEY_KPDOT */
  550. 0x1C050073 /* KEY_VOLUMEUP */
  551. 0x1D030066 /* KEY_HOME */
  552. 0x1D04006B /* KEY_END */
  553. 0x1D0500E1 /* KEY_BRIGHTNESSUP */
  554. 0x1D060072 /* KEY_VOLUMEDOWN */
  555. 0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
  556. 0x1E000045 /* KEY_NUMLOCK */
  557. 0x1E010046 /* KEY_SCROLLLOCK */
  558. 0x1E020071 /* KEY_MUTE */
  559. 0x1F0400D6>; /* KEY_QUESTION */
  560. };
  561. regulators {
  562. compatible = "simple-bus";
  563. #address-cells = <1>;
  564. #size-cells = <0>;
  565. vdd_5v0_reg: regulator@0 {
  566. compatible = "regulator-fixed";
  567. reg = <0>;
  568. regulator-name = "vdd_5v0";
  569. regulator-min-microvolt = <5000000>;
  570. regulator-max-microvolt = <5000000>;
  571. regulator-always-on;
  572. };
  573. regulator@1 {
  574. compatible = "regulator-fixed";
  575. reg = <1>;
  576. regulator-name = "vdd_1v5";
  577. regulator-min-microvolt = <1500000>;
  578. regulator-max-microvolt = <1500000>;
  579. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  580. };
  581. regulator@2 {
  582. compatible = "regulator-fixed";
  583. reg = <2>;
  584. regulator-name = "vdd_1v2";
  585. regulator-min-microvolt = <1200000>;
  586. regulator-max-microvolt = <1200000>;
  587. gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
  588. enable-active-high;
  589. };
  590. regulator@3 {
  591. compatible = "regulator-fixed";
  592. reg = <3>;
  593. regulator-name = "vdd_1v05";
  594. regulator-min-microvolt = <1050000>;
  595. regulator-max-microvolt = <1050000>;
  596. gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
  597. enable-active-high;
  598. /* Hack until board-harmony-pcie.c is removed */
  599. status = "disabled";
  600. };
  601. regulator@4 {
  602. compatible = "regulator-fixed";
  603. reg = <4>;
  604. regulator-name = "vdd_pnl";
  605. regulator-min-microvolt = <2800000>;
  606. regulator-max-microvolt = <2800000>;
  607. gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
  608. enable-active-high;
  609. };
  610. regulator@5 {
  611. compatible = "regulator-fixed";
  612. reg = <5>;
  613. regulator-name = "vdd_bl";
  614. regulator-min-microvolt = <2800000>;
  615. regulator-max-microvolt = <2800000>;
  616. gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
  617. enable-active-high;
  618. };
  619. };
  620. sound {
  621. compatible = "nvidia,tegra-audio-wm8903-harmony",
  622. "nvidia,tegra-audio-wm8903";
  623. nvidia,model = "NVIDIA Tegra Harmony";
  624. nvidia,audio-routing =
  625. "Headphone Jack", "HPOUTR",
  626. "Headphone Jack", "HPOUTL",
  627. "Int Spk", "ROP",
  628. "Int Spk", "RON",
  629. "Int Spk", "LOP",
  630. "Int Spk", "LON",
  631. "Mic Jack", "MICBIAS",
  632. "IN1L", "Mic Jack";
  633. nvidia,i2s-controller = <&tegra_i2s1>;
  634. nvidia,audio-codec = <&wm8903>;
  635. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  636. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  637. GPIO_ACTIVE_HIGH>;
  638. nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
  639. GPIO_ACTIVE_HIGH>;
  640. nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
  641. GPIO_ACTIVE_HIGH>;
  642. clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
  643. <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
  644. <&tegra_car TEGRA20_CLK_CDEV1>;
  645. clock-names = "pll_a", "pll_a_out0", "mclk";
  646. };
  647. };