tegra114-dalmore.dts 22 KB

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  1. /dts-v1/;
  2. #include "tegra114.dtsi"
  3. / {
  4. model = "NVIDIA Tegra114 Dalmore evaluation board";
  5. compatible = "nvidia,dalmore", "nvidia,tegra114";
  6. memory {
  7. reg = <0x80000000 0x40000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. clk1_out_pw4 {
  14. nvidia,pins = "clk1_out_pw4";
  15. nvidia,function = "extperiph1";
  16. nvidia,pull = <0>;
  17. nvidia,tristate = <0>;
  18. nvidia,enable-input = <0>;
  19. };
  20. dap1_din_pn1 {
  21. nvidia,pins = "dap1_din_pn1";
  22. nvidia,function = "i2s0";
  23. nvidia,pull = <0>;
  24. nvidia,tristate = <1>;
  25. nvidia,enable-input = <1>;
  26. };
  27. dap1_dout_pn2 {
  28. nvidia,pins = "dap1_dout_pn2",
  29. "dap1_fs_pn0",
  30. "dap1_sclk_pn3";
  31. nvidia,function = "i2s0";
  32. nvidia,pull = <0>;
  33. nvidia,tristate = <0>;
  34. nvidia,enable-input = <1>;
  35. };
  36. dap2_din_pa4 {
  37. nvidia,pins = "dap2_din_pa4";
  38. nvidia,function = "i2s1";
  39. nvidia,pull = <0>;
  40. nvidia,tristate = <1>;
  41. nvidia,enable-input = <1>;
  42. };
  43. dap2_dout_pa5 {
  44. nvidia,pins = "dap2_dout_pa5",
  45. "dap2_fs_pa2",
  46. "dap2_sclk_pa3";
  47. nvidia,function = "i2s1";
  48. nvidia,pull = <0>;
  49. nvidia,tristate = <0>;
  50. nvidia,enable-input = <1>;
  51. };
  52. dap4_din_pp5 {
  53. nvidia,pins = "dap4_din_pp5",
  54. "dap4_dout_pp6",
  55. "dap4_fs_pp4",
  56. "dap4_sclk_pp7";
  57. nvidia,function = "i2s3";
  58. nvidia,pull = <0>;
  59. nvidia,tristate = <0>;
  60. nvidia,enable-input = <1>;
  61. };
  62. dvfs_pwm_px0 {
  63. nvidia,pins = "dvfs_pwm_px0",
  64. "dvfs_clk_px2";
  65. nvidia,function = "cldvfs";
  66. nvidia,pull = <0>;
  67. nvidia,tristate = <0>;
  68. nvidia,enable-input = <0>;
  69. };
  70. ulpi_clk_py0 {
  71. nvidia,pins = "ulpi_clk_py0",
  72. "ulpi_data0_po1",
  73. "ulpi_data1_po2",
  74. "ulpi_data2_po3",
  75. "ulpi_data3_po4",
  76. "ulpi_data4_po5",
  77. "ulpi_data5_po6",
  78. "ulpi_data6_po7",
  79. "ulpi_data7_po0";
  80. nvidia,function = "ulpi";
  81. nvidia,pull = <0>;
  82. nvidia,tristate = <0>;
  83. nvidia,enable-input = <1>;
  84. };
  85. ulpi_dir_py1 {
  86. nvidia,pins = "ulpi_dir_py1",
  87. "ulpi_nxt_py2";
  88. nvidia,function = "ulpi";
  89. nvidia,pull = <0>;
  90. nvidia,tristate = <1>;
  91. nvidia,enable-input = <1>;
  92. };
  93. ulpi_stp_py3 {
  94. nvidia,pins = "ulpi_stp_py3";
  95. nvidia,function = "ulpi";
  96. nvidia,pull = <0>;
  97. nvidia,tristate = <0>;
  98. nvidia,enable-input = <0>;
  99. };
  100. cam_i2c_scl_pbb1 {
  101. nvidia,pins = "cam_i2c_scl_pbb1",
  102. "cam_i2c_sda_pbb2";
  103. nvidia,function = "i2c3";
  104. nvidia,pull = <0>;
  105. nvidia,tristate = <0>;
  106. nvidia,enable-input = <1>;
  107. nvidia,lock = <0>;
  108. nvidia,open-drain = <0>;
  109. };
  110. cam_mclk_pcc0 {
  111. nvidia,pins = "cam_mclk_pcc0",
  112. "pbb0";
  113. nvidia,function = "vi_alt3";
  114. nvidia,pull = <0>;
  115. nvidia,tristate = <0>;
  116. nvidia,enable-input = <0>;
  117. nvidia,lock = <0>;
  118. };
  119. gen2_i2c_scl_pt5 {
  120. nvidia,pins = "gen2_i2c_scl_pt5",
  121. "gen2_i2c_sda_pt6";
  122. nvidia,function = "i2c2";
  123. nvidia,pull = <0>;
  124. nvidia,tristate = <0>;
  125. nvidia,enable-input = <1>;
  126. nvidia,lock = <0>;
  127. nvidia,open-drain = <0>;
  128. };
  129. gmi_a16_pj7 {
  130. nvidia,pins = "gmi_a16_pj7";
  131. nvidia,function = "uartd";
  132. nvidia,pull = <0>;
  133. nvidia,tristate = <0>;
  134. nvidia,enable-input = <0>;
  135. };
  136. gmi_a17_pb0 {
  137. nvidia,pins = "gmi_a17_pb0",
  138. "gmi_a18_pb1";
  139. nvidia,function = "uartd";
  140. nvidia,pull = <0>;
  141. nvidia,tristate = <1>;
  142. nvidia,enable-input = <1>;
  143. };
  144. gmi_a19_pk7 {
  145. nvidia,pins = "gmi_a19_pk7";
  146. nvidia,function = "uartd";
  147. nvidia,pull = <0>;
  148. nvidia,tristate = <0>;
  149. nvidia,enable-input = <0>;
  150. };
  151. gmi_ad5_pg5 {
  152. nvidia,pins = "gmi_ad5_pg5",
  153. "gmi_cs6_n_pi3",
  154. "gmi_wr_n_pi0";
  155. nvidia,function = "spi4";
  156. nvidia,pull = <0>;
  157. nvidia,tristate = <0>;
  158. nvidia,enable-input = <1>;
  159. };
  160. gmi_ad6_pg6 {
  161. nvidia,pins = "gmi_ad6_pg6",
  162. "gmi_ad7_pg7";
  163. nvidia,function = "spi4";
  164. nvidia,pull = <2>;
  165. nvidia,tristate = <0>;
  166. nvidia,enable-input = <1>;
  167. };
  168. gmi_ad12_ph4 {
  169. nvidia,pins = "gmi_ad12_ph4";
  170. nvidia,function = "rsvd4";
  171. nvidia,pull = <0>;
  172. nvidia,tristate = <0>;
  173. nvidia,enable-input = <0>;
  174. };
  175. gmi_ad9_ph1 {
  176. nvidia,pins = "gmi_ad9_ph1";
  177. nvidia,function = "pwm1";
  178. nvidia,pull = <0>;
  179. nvidia,tristate = <0>;
  180. nvidia,enable-input = <0>;
  181. };
  182. gmi_cs1_n_pj2 {
  183. nvidia,pins = "gmi_cs1_n_pj2",
  184. "gmi_oe_n_pi1";
  185. nvidia,function = "soc";
  186. nvidia,pull = <0>;
  187. nvidia,tristate = <1>;
  188. nvidia,enable-input = <1>;
  189. };
  190. clk2_out_pw5 {
  191. nvidia,pins = "clk2_out_pw5";
  192. nvidia,function = "extperiph2";
  193. nvidia,pull = <0>;
  194. nvidia,tristate = <0>;
  195. nvidia,enable-input = <0>;
  196. };
  197. sdmmc1_clk_pz0 {
  198. nvidia,pins = "sdmmc1_clk_pz0";
  199. nvidia,function = "sdmmc1";
  200. nvidia,pull = <0>;
  201. nvidia,tristate = <0>;
  202. nvidia,enable-input = <1>;
  203. };
  204. sdmmc1_cmd_pz1 {
  205. nvidia,pins = "sdmmc1_cmd_pz1",
  206. "sdmmc1_dat0_py7",
  207. "sdmmc1_dat1_py6",
  208. "sdmmc1_dat2_py5",
  209. "sdmmc1_dat3_py4";
  210. nvidia,function = "sdmmc1";
  211. nvidia,pull = <2>;
  212. nvidia,tristate = <0>;
  213. nvidia,enable-input = <1>;
  214. };
  215. sdmmc1_wp_n_pv3 {
  216. nvidia,pins = "sdmmc1_wp_n_pv3";
  217. nvidia,function = "spi4";
  218. nvidia,pull = <2>;
  219. nvidia,tristate = <0>;
  220. nvidia,enable-input = <0>;
  221. };
  222. sdmmc3_clk_pa6 {
  223. nvidia,pins = "sdmmc3_clk_pa6";
  224. nvidia,function = "sdmmc3";
  225. nvidia,pull = <0>;
  226. nvidia,tristate = <0>;
  227. nvidia,enable-input = <1>;
  228. };
  229. sdmmc3_cmd_pa7 {
  230. nvidia,pins = "sdmmc3_cmd_pa7",
  231. "sdmmc3_dat0_pb7",
  232. "sdmmc3_dat1_pb6",
  233. "sdmmc3_dat2_pb5",
  234. "sdmmc3_dat3_pb4",
  235. "kb_col4_pq4",
  236. "sdmmc3_clk_lb_out_pee4",
  237. "sdmmc3_clk_lb_in_pee5";
  238. nvidia,function = "sdmmc3";
  239. nvidia,pull = <2>;
  240. nvidia,tristate = <0>;
  241. nvidia,enable-input = <1>;
  242. };
  243. sdmmc4_clk_pcc4 {
  244. nvidia,pins = "sdmmc4_clk_pcc4";
  245. nvidia,function = "sdmmc4";
  246. nvidia,pull = <0>;
  247. nvidia,tristate = <0>;
  248. nvidia,enable-input = <1>;
  249. };
  250. sdmmc4_cmd_pt7 {
  251. nvidia,pins = "sdmmc4_cmd_pt7",
  252. "sdmmc4_dat0_paa0",
  253. "sdmmc4_dat1_paa1",
  254. "sdmmc4_dat2_paa2",
  255. "sdmmc4_dat3_paa3",
  256. "sdmmc4_dat4_paa4",
  257. "sdmmc4_dat5_paa5",
  258. "sdmmc4_dat6_paa6",
  259. "sdmmc4_dat7_paa7";
  260. nvidia,function = "sdmmc4";
  261. nvidia,pull = <2>;
  262. nvidia,tristate = <0>;
  263. nvidia,enable-input = <1>;
  264. };
  265. clk_32k_out_pa0 {
  266. nvidia,pins = "clk_32k_out_pa0";
  267. nvidia,function = "blink";
  268. nvidia,pull = <0>;
  269. nvidia,tristate = <0>;
  270. nvidia,enable-input = <0>;
  271. };
  272. kb_col0_pq0 {
  273. nvidia,pins = "kb_col0_pq0",
  274. "kb_col1_pq1",
  275. "kb_col2_pq2",
  276. "kb_row0_pr0",
  277. "kb_row1_pr1",
  278. "kb_row2_pr2";
  279. nvidia,function = "kbc";
  280. nvidia,pull = <2>;
  281. nvidia,tristate = <0>;
  282. nvidia,enable-input = <1>;
  283. };
  284. dap3_din_pp1 {
  285. nvidia,pins = "dap3_din_pp1",
  286. "dap3_sclk_pp3";
  287. nvidia,function = "displayb";
  288. nvidia,pull = <0>;
  289. nvidia,tristate = <1>;
  290. nvidia,enable-input = <0>;
  291. };
  292. pv0 {
  293. nvidia,pins = "pv0";
  294. nvidia,function = "rsvd4";
  295. nvidia,pull = <0>;
  296. nvidia,tristate = <1>;
  297. nvidia,enable-input = <0>;
  298. };
  299. kb_row7_pr7 {
  300. nvidia,pins = "kb_row7_pr7";
  301. nvidia,function = "rsvd2";
  302. nvidia,pull = <2>;
  303. nvidia,tristate = <0>;
  304. nvidia,enable-input = <1>;
  305. };
  306. kb_row10_ps2 {
  307. nvidia,pins = "kb_row10_ps2";
  308. nvidia,function = "uarta";
  309. nvidia,pull = <0>;
  310. nvidia,tristate = <1>;
  311. nvidia,enable-input = <1>;
  312. };
  313. kb_row9_ps1 {
  314. nvidia,pins = "kb_row9_ps1";
  315. nvidia,function = "uarta";
  316. nvidia,pull = <0>;
  317. nvidia,tristate = <0>;
  318. nvidia,enable-input = <0>;
  319. };
  320. pwr_i2c_scl_pz6 {
  321. nvidia,pins = "pwr_i2c_scl_pz6",
  322. "pwr_i2c_sda_pz7";
  323. nvidia,function = "i2cpwr";
  324. nvidia,pull = <0>;
  325. nvidia,tristate = <0>;
  326. nvidia,enable-input = <1>;
  327. nvidia,lock = <0>;
  328. nvidia,open-drain = <0>;
  329. };
  330. sys_clk_req_pz5 {
  331. nvidia,pins = "sys_clk_req_pz5";
  332. nvidia,function = "sysclk";
  333. nvidia,pull = <0>;
  334. nvidia,tristate = <0>;
  335. nvidia,enable-input = <0>;
  336. };
  337. core_pwr_req {
  338. nvidia,pins = "core_pwr_req";
  339. nvidia,function = "pwron";
  340. nvidia,pull = <0>;
  341. nvidia,tristate = <0>;
  342. nvidia,enable-input = <0>;
  343. };
  344. cpu_pwr_req {
  345. nvidia,pins = "cpu_pwr_req";
  346. nvidia,function = "cpu";
  347. nvidia,pull = <0>;
  348. nvidia,tristate = <0>;
  349. nvidia,enable-input = <0>;
  350. };
  351. pwr_int_n {
  352. nvidia,pins = "pwr_int_n";
  353. nvidia,function = "pmi";
  354. nvidia,pull = <0>;
  355. nvidia,tristate = <1>;
  356. nvidia,enable-input = <1>;
  357. };
  358. reset_out_n {
  359. nvidia,pins = "reset_out_n";
  360. nvidia,function = "reset_out_n";
  361. nvidia,pull = <0>;
  362. nvidia,tristate = <0>;
  363. nvidia,enable-input = <0>;
  364. };
  365. clk3_out_pee0 {
  366. nvidia,pins = "clk3_out_pee0";
  367. nvidia,function = "extperiph3";
  368. nvidia,pull = <0>;
  369. nvidia,tristate = <0>;
  370. nvidia,enable-input = <0>;
  371. };
  372. gen1_i2c_scl_pc4 {
  373. nvidia,pins = "gen1_i2c_scl_pc4",
  374. "gen1_i2c_sda_pc5";
  375. nvidia,function = "i2c1";
  376. nvidia,pull = <0>;
  377. nvidia,tristate = <0>;
  378. nvidia,enable-input = <1>;
  379. nvidia,lock = <0>;
  380. nvidia,open-drain = <0>;
  381. };
  382. uart2_cts_n_pj5 {
  383. nvidia,pins = "uart2_cts_n_pj5";
  384. nvidia,function = "uartb";
  385. nvidia,pull = <0>;
  386. nvidia,tristate = <1>;
  387. nvidia,enable-input = <1>;
  388. };
  389. uart2_rts_n_pj6 {
  390. nvidia,pins = "uart2_rts_n_pj6";
  391. nvidia,function = "uartb";
  392. nvidia,pull = <0>;
  393. nvidia,tristate = <0>;
  394. nvidia,enable-input = <0>;
  395. };
  396. uart2_rxd_pc3 {
  397. nvidia,pins = "uart2_rxd_pc3";
  398. nvidia,function = "irda";
  399. nvidia,pull = <0>;
  400. nvidia,tristate = <1>;
  401. nvidia,enable-input = <1>;
  402. };
  403. uart2_txd_pc2 {
  404. nvidia,pins = "uart2_txd_pc2";
  405. nvidia,function = "irda";
  406. nvidia,pull = <0>;
  407. nvidia,tristate = <0>;
  408. nvidia,enable-input = <0>;
  409. };
  410. uart3_cts_n_pa1 {
  411. nvidia,pins = "uart3_cts_n_pa1",
  412. "uart3_rxd_pw7";
  413. nvidia,function = "uartc";
  414. nvidia,pull = <0>;
  415. nvidia,tristate = <1>;
  416. nvidia,enable-input = <1>;
  417. };
  418. uart3_rts_n_pc0 {
  419. nvidia,pins = "uart3_rts_n_pc0",
  420. "uart3_txd_pw6";
  421. nvidia,function = "uartc";
  422. nvidia,pull = <0>;
  423. nvidia,tristate = <0>;
  424. nvidia,enable-input = <0>;
  425. };
  426. owr {
  427. nvidia,pins = "owr";
  428. nvidia,function = "owr";
  429. nvidia,pull = <0>;
  430. nvidia,tristate = <0>;
  431. nvidia,enable-input = <1>;
  432. };
  433. hdmi_cec_pee3 {
  434. nvidia,pins = "hdmi_cec_pee3";
  435. nvidia,function = "cec";
  436. nvidia,pull = <0>;
  437. nvidia,tristate = <0>;
  438. nvidia,enable-input = <1>;
  439. nvidia,lock = <0>;
  440. nvidia,open-drain = <0>;
  441. };
  442. ddc_scl_pv4 {
  443. nvidia,pins = "ddc_scl_pv4",
  444. "ddc_sda_pv5";
  445. nvidia,function = "i2c4";
  446. nvidia,pull = <0>;
  447. nvidia,tristate = <0>;
  448. nvidia,enable-input = <1>;
  449. nvidia,lock = <0>;
  450. nvidia,rcv-sel = <1>;
  451. };
  452. spdif_in_pk6 {
  453. nvidia,pins = "spdif_in_pk6";
  454. nvidia,function = "usb";
  455. nvidia,pull = <2>;
  456. nvidia,tristate = <0>;
  457. nvidia,enable-input = <1>;
  458. nvidia,lock = <0>;
  459. };
  460. usb_vbus_en0_pn4 {
  461. nvidia,pins = "usb_vbus_en0_pn4";
  462. nvidia,function = "usb";
  463. nvidia,pull = <2>;
  464. nvidia,tristate = <0>;
  465. nvidia,enable-input = <1>;
  466. nvidia,lock = <0>;
  467. nvidia,open-drain = <1>;
  468. };
  469. gpio_x6_aud_px6 {
  470. nvidia,pins = "gpio_x6_aud_px6";
  471. nvidia,function = "spi6";
  472. nvidia,pull = <2>;
  473. nvidia,tristate = <1>;
  474. nvidia,enable-input = <1>;
  475. };
  476. gpio_x4_aud_px4 {
  477. nvidia,pins = "gpio_x4_aud_px4",
  478. "gpio_x7_aud_px7";
  479. nvidia,function = "rsvd1";
  480. nvidia,pull = <1>;
  481. nvidia,tristate = <0>;
  482. nvidia,enable-input = <0>;
  483. };
  484. gpio_x5_aud_px5 {
  485. nvidia,pins = "gpio_x5_aud_px5";
  486. nvidia,function = "rsvd1";
  487. nvidia,pull = <2>;
  488. nvidia,tristate = <0>;
  489. nvidia,enable-input = <1>;
  490. };
  491. gpio_w2_aud_pw2 {
  492. nvidia,pins = "gpio_w2_aud_pw2";
  493. nvidia,function = "rsvd2";
  494. nvidia,pull = <2>;
  495. nvidia,tristate = <0>;
  496. nvidia,enable-input = <1>;
  497. };
  498. gpio_w3_aud_pw3 {
  499. nvidia,pins = "gpio_w3_aud_pw3";
  500. nvidia,function = "spi6";
  501. nvidia,pull = <2>;
  502. nvidia,tristate = <0>;
  503. nvidia,enable-input = <1>;
  504. };
  505. gpio_x1_aud_px1 {
  506. nvidia,pins = "gpio_x1_aud_px1";
  507. nvidia,function = "rsvd4";
  508. nvidia,pull = <1>;
  509. nvidia,tristate = <0>;
  510. nvidia,enable-input = <1>;
  511. };
  512. gpio_x3_aud_px3 {
  513. nvidia,pins = "gpio_x3_aud_px3";
  514. nvidia,function = "rsvd4";
  515. nvidia,pull = <2>;
  516. nvidia,tristate = <0>;
  517. nvidia,enable-input = <1>;
  518. };
  519. dap3_fs_pp0 {
  520. nvidia,pins = "dap3_fs_pp0";
  521. nvidia,function = "i2s2";
  522. nvidia,pull = <1>;
  523. nvidia,tristate = <0>;
  524. nvidia,enable-input = <0>;
  525. };
  526. dap3_dout_pp2 {
  527. nvidia,pins = "dap3_dout_pp2";
  528. nvidia,function = "i2s2";
  529. nvidia,pull = <1>;
  530. nvidia,tristate = <0>;
  531. nvidia,enable-input = <0>;
  532. };
  533. pv1 {
  534. nvidia,pins = "pv1";
  535. nvidia,function = "rsvd1";
  536. nvidia,pull = <0>;
  537. nvidia,tristate = <0>;
  538. nvidia,enable-input = <1>;
  539. };
  540. pbb3 {
  541. nvidia,pins = "pbb3",
  542. "pbb5",
  543. "pbb6",
  544. "pbb7";
  545. nvidia,function = "rsvd4";
  546. nvidia,pull = <1>;
  547. nvidia,tristate = <0>;
  548. nvidia,enable-input = <0>;
  549. };
  550. pcc1 {
  551. nvidia,pins = "pcc1",
  552. "pcc2";
  553. nvidia,function = "rsvd4";
  554. nvidia,pull = <1>;
  555. nvidia,tristate = <0>;
  556. nvidia,enable-input = <1>;
  557. };
  558. gmi_ad0_pg0 {
  559. nvidia,pins = "gmi_ad0_pg0",
  560. "gmi_ad1_pg1";
  561. nvidia,function = "gmi";
  562. nvidia,pull = <0>;
  563. nvidia,tristate = <0>;
  564. nvidia,enable-input = <0>;
  565. };
  566. gmi_ad10_ph2 {
  567. nvidia,pins = "gmi_ad10_ph2",
  568. "gmi_ad11_ph3",
  569. "gmi_ad13_ph5",
  570. "gmi_ad8_ph0",
  571. "gmi_clk_pk1";
  572. nvidia,function = "gmi";
  573. nvidia,pull = <1>;
  574. nvidia,tristate = <0>;
  575. nvidia,enable-input = <0>;
  576. };
  577. gmi_ad2_pg2 {
  578. nvidia,pins = "gmi_ad2_pg2",
  579. "gmi_ad3_pg3";
  580. nvidia,function = "gmi";
  581. nvidia,pull = <0>;
  582. nvidia,tristate = <0>;
  583. nvidia,enable-input = <1>;
  584. };
  585. gmi_adv_n_pk0 {
  586. nvidia,pins = "gmi_adv_n_pk0",
  587. "gmi_cs0_n_pj0",
  588. "gmi_cs2_n_pk3",
  589. "gmi_cs4_n_pk2",
  590. "gmi_cs7_n_pi6",
  591. "gmi_dqs_p_pj3",
  592. "gmi_iordy_pi5",
  593. "gmi_wp_n_pc7";
  594. nvidia,function = "gmi";
  595. nvidia,pull = <2>;
  596. nvidia,tristate = <0>;
  597. nvidia,enable-input = <1>;
  598. };
  599. gmi_cs3_n_pk4 {
  600. nvidia,pins = "gmi_cs3_n_pk4";
  601. nvidia,function = "gmi";
  602. nvidia,pull = <2>;
  603. nvidia,tristate = <0>;
  604. nvidia,enable-input = <0>;
  605. };
  606. clk2_req_pcc5 {
  607. nvidia,pins = "clk2_req_pcc5";
  608. nvidia,function = "rsvd4";
  609. nvidia,pull = <0>;
  610. nvidia,tristate = <0>;
  611. nvidia,enable-input = <0>;
  612. };
  613. kb_col3_pq3 {
  614. nvidia,pins = "kb_col3_pq3",
  615. "kb_col6_pq6",
  616. "kb_col7_pq7";
  617. nvidia,function = "kbc";
  618. nvidia,pull = <2>;
  619. nvidia,tristate = <0>;
  620. nvidia,enable-input = <0>;
  621. };
  622. kb_col5_pq5 {
  623. nvidia,pins = "kb_col5_pq5";
  624. nvidia,function = "kbc";
  625. nvidia,pull = <2>;
  626. nvidia,tristate = <0>;
  627. nvidia,enable-input = <1>;
  628. };
  629. kb_row3_pr3 {
  630. nvidia,pins = "kb_row3_pr3",
  631. "kb_row4_pr4",
  632. "kb_row6_pr6",
  633. "kb_row8_ps0";
  634. nvidia,function = "kbc";
  635. nvidia,pull = <1>;
  636. nvidia,tristate = <0>;
  637. nvidia,enable-input = <1>;
  638. };
  639. clk3_req_pee1 {
  640. nvidia,pins = "clk3_req_pee1";
  641. nvidia,function = "rsvd4";
  642. nvidia,pull = <0>;
  643. nvidia,tristate = <0>;
  644. nvidia,enable-input = <0>;
  645. };
  646. pu4 {
  647. nvidia,pins = "pu4";
  648. nvidia,function = "displayb";
  649. nvidia,pull = <0>;
  650. nvidia,tristate = <0>;
  651. nvidia,enable-input = <0>;
  652. };
  653. pu5 {
  654. nvidia,pins = "pu5",
  655. "pu6";
  656. nvidia,function = "displayb";
  657. nvidia,pull = <0>;
  658. nvidia,tristate = <0>;
  659. nvidia,enable-input = <1>;
  660. };
  661. hdmi_int_pn7 {
  662. nvidia,pins = "hdmi_int_pn7";
  663. nvidia,function = "rsvd1";
  664. nvidia,pull = <1>;
  665. nvidia,tristate = <0>;
  666. nvidia,enable-input = <1>;
  667. };
  668. clk1_req_pee2 {
  669. nvidia,pins = "clk1_req_pee2",
  670. "usb_vbus_en1_pn5";
  671. nvidia,function = "rsvd4";
  672. nvidia,pull = <1>;
  673. nvidia,tristate = <1>;
  674. nvidia,enable-input = <0>;
  675. };
  676. drive_sdio1 {
  677. nvidia,pins = "drive_sdio1";
  678. nvidia,high-speed-mode = <1>;
  679. nvidia,schmitt = <0>;
  680. nvidia,low-power-mode = <3>;
  681. nvidia,pull-down-strength = <36>;
  682. nvidia,pull-up-strength = <20>;
  683. nvidia,slew-rate-rising = <2>;
  684. nvidia,slew-rate-falling = <2>;
  685. };
  686. drive_sdio3 {
  687. nvidia,pins = "drive_sdio3";
  688. nvidia,high-speed-mode = <1>;
  689. nvidia,schmitt = <0>;
  690. nvidia,low-power-mode = <3>;
  691. nvidia,pull-down-strength = <22>;
  692. nvidia,pull-up-strength = <36>;
  693. nvidia,slew-rate-rising = <0>;
  694. nvidia,slew-rate-falling = <0>;
  695. };
  696. drive_gma {
  697. nvidia,pins = "drive_gma";
  698. nvidia,high-speed-mode = <1>;
  699. nvidia,schmitt = <0>;
  700. nvidia,low-power-mode = <3>;
  701. nvidia,pull-down-strength = <2>;
  702. nvidia,pull-up-strength = <1>;
  703. nvidia,slew-rate-rising = <0>;
  704. nvidia,slew-rate-falling = <0>;
  705. nvidia,drive-type = <1>;
  706. };
  707. };
  708. };
  709. serial@70006300 {
  710. status = "okay";
  711. };
  712. i2c@7000c000 {
  713. status = "okay";
  714. clock-frequency = <100000>;
  715. battery: smart-battery {
  716. compatible = "ti,bq20z45", "sbs,sbs-battery";
  717. reg = <0xb>;
  718. battery-name = "battery";
  719. sbs,i2c-retry-count = <2>;
  720. sbs,poll-retry-count = <100>;
  721. power-supplies = <&charger>;
  722. };
  723. rt5640: rt5640 {
  724. compatible = "realtek,rt5640";
  725. reg = <0x1c>;
  726. interrupt-parent = <&gpio>;
  727. interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
  728. realtek,ldo1-en-gpios =
  729. <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
  730. };
  731. };
  732. i2c@7000d000 {
  733. status = "okay";
  734. clock-frequency = <400000>;
  735. tps51632 {
  736. compatible = "ti,tps51632";
  737. reg = <0x43>;
  738. regulator-name = "vdd-cpu";
  739. regulator-min-microvolt = <500000>;
  740. regulator-max-microvolt = <1520000>;
  741. regulator-boot-on;
  742. regulator-always-on;
  743. };
  744. tps65090 {
  745. compatible = "ti,tps65090";
  746. reg = <0x48>;
  747. interrupt-parent = <&gpio>;
  748. interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
  749. vsys1-supply = <&vdd_ac_bat_reg>;
  750. vsys2-supply = <&vdd_ac_bat_reg>;
  751. vsys3-supply = <&vdd_ac_bat_reg>;
  752. infet1-supply = <&vdd_ac_bat_reg>;
  753. infet2-supply = <&vdd_ac_bat_reg>;
  754. infet3-supply = <&tps65090_dcdc2_reg>;
  755. infet4-supply = <&tps65090_dcdc2_reg>;
  756. infet5-supply = <&tps65090_dcdc2_reg>;
  757. infet6-supply = <&tps65090_dcdc2_reg>;
  758. infet7-supply = <&tps65090_dcdc2_reg>;
  759. vsys-l1-supply = <&vdd_ac_bat_reg>;
  760. vsys-l2-supply = <&vdd_ac_bat_reg>;
  761. charger: charger {
  762. compatible = "ti,tps65090-charger";
  763. ti,enable-low-current-chrg;
  764. };
  765. regulators {
  766. tps65090_dcdc1_reg: dcdc1 {
  767. regulator-name = "vdd-sys-5v0";
  768. regulator-always-on;
  769. regulator-boot-on;
  770. };
  771. tps65090_dcdc2_reg: dcdc2 {
  772. regulator-name = "vdd-sys-3v3";
  773. regulator-always-on;
  774. regulator-boot-on;
  775. };
  776. dcdc3 {
  777. regulator-name = "vdd-ao";
  778. regulator-always-on;
  779. regulator-boot-on;
  780. };
  781. fet1 {
  782. regulator-name = "vdd-lcd-bl";
  783. };
  784. fet3 {
  785. regulator-name = "vdd-modem-3v3";
  786. };
  787. fet4 {
  788. regulator-name = "avdd-lcd";
  789. };
  790. fet5 {
  791. regulator-name = "vdd-lvds";
  792. };
  793. fet6 {
  794. regulator-name = "vdd-sd-slot";
  795. regulator-always-on;
  796. regulator-boot-on;
  797. };
  798. fet7 {
  799. regulator-name = "vdd-com-3v3";
  800. };
  801. ldo1 {
  802. regulator-name = "vdd-sby-5v0";
  803. regulator-always-on;
  804. regulator-boot-on;
  805. };
  806. ldo2 {
  807. regulator-name = "vdd-sby-3v3";
  808. regulator-always-on;
  809. regulator-boot-on;
  810. };
  811. };
  812. };
  813. };
  814. spi@7000da00 {
  815. status = "okay";
  816. spi-max-frequency = <25000000>;
  817. spi-flash@0 {
  818. compatible = "winbond,w25q32dw";
  819. reg = <0>;
  820. spi-max-frequency = <20000000>;
  821. };
  822. };
  823. pmc {
  824. nvidia,invert-interrupt;
  825. };
  826. ahub {
  827. i2s@70080400 {
  828. status = "okay";
  829. };
  830. };
  831. sdhci@78000400 {
  832. cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
  833. bus-width = <4>;
  834. status = "okay";
  835. };
  836. sdhci@78000600 {
  837. bus-width = <8>;
  838. status = "okay";
  839. non-removable;
  840. };
  841. clocks {
  842. compatible = "simple-bus";
  843. #address-cells = <1>;
  844. #size-cells = <0>;
  845. clk32k_in: clock {
  846. compatible = "fixed-clock";
  847. reg=<0>;
  848. #clock-cells = <0>;
  849. clock-frequency = <32768>;
  850. };
  851. };
  852. regulators {
  853. compatible = "simple-bus";
  854. #address-cells = <1>;
  855. #size-cells = <0>;
  856. vdd_ac_bat_reg: regulator@0 {
  857. compatible = "regulator-fixed";
  858. reg = <0>;
  859. regulator-name = "vdd_ac_bat";
  860. regulator-min-microvolt = <5000000>;
  861. regulator-max-microvolt = <5000000>;
  862. regulator-always-on;
  863. };
  864. dvdd_ts_reg: regulator@1 {
  865. compatible = "regulator-fixed";
  866. reg = <1>;
  867. regulator-name = "dvdd_ts";
  868. regulator-min-microvolt = <1800000>;
  869. regulator-max-microvolt = <1800000>;
  870. enable-active-high;
  871. gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
  872. };
  873. lcd_bl_en_reg: regulator@2 {
  874. compatible = "regulator-fixed";
  875. reg = <2>;
  876. regulator-name = "lcd_bl_en";
  877. regulator-min-microvolt = <5000000>;
  878. regulator-max-microvolt = <5000000>;
  879. enable-active-high;
  880. gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
  881. };
  882. usb1_vbus_reg: regulator@3 {
  883. compatible = "regulator-fixed";
  884. reg = <3>;
  885. regulator-name = "usb1_vbus";
  886. regulator-min-microvolt = <5000000>;
  887. regulator-max-microvolt = <5000000>;
  888. enable-active-high;
  889. gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
  890. gpio-open-drain;
  891. vin-supply = <&tps65090_dcdc1_reg>;
  892. };
  893. usb3_vbus_reg: regulator@4 {
  894. compatible = "regulator-fixed";
  895. reg = <4>;
  896. regulator-name = "usb2_vbus";
  897. regulator-min-microvolt = <5000000>;
  898. regulator-max-microvolt = <5000000>;
  899. enable-active-high;
  900. gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
  901. gpio-open-drain;
  902. vin-supply = <&tps65090_dcdc1_reg>;
  903. };
  904. vdd_hdmi_reg: regulator@5 {
  905. compatible = "regulator-fixed";
  906. reg = <5>;
  907. regulator-name = "vdd_hdmi_5v0";
  908. regulator-min-microvolt = <5000000>;
  909. regulator-max-microvolt = <5000000>;
  910. enable-active-high;
  911. gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
  912. vin-supply = <&tps65090_dcdc1_reg>;
  913. };
  914. };
  915. sound {
  916. compatible = "nvidia,tegra-audio-rt5640-dalmore",
  917. "nvidia,tegra-audio-rt5640";
  918. nvidia,model = "NVIDIA Tegra Dalmore";
  919. nvidia,audio-routing =
  920. "Headphones", "HPOR",
  921. "Headphones", "HPOL",
  922. "Speakers", "SPORP",
  923. "Speakers", "SPORN",
  924. "Speakers", "SPOLP",
  925. "Speakers", "SPOLN";
  926. nvidia,i2s-controller = <&tegra_i2s1>;
  927. nvidia,audio-codec = <&rt5640>;
  928. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  929. clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
  930. <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
  931. <&tegra_car TEGRA114_CLK_EXTERN1>;
  932. clock-names = "pll_a", "pll_a_out0", "mclk";
  933. };
  934. };