rk3066a-clocks.dtsi 8.4 KB

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  1. /*
  2. * Copyright (c) 2013 MundoReader S.L.
  3. * Author: Heiko Stuebner <heiko@sntech.de>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. / {
  16. clocks {
  17. #address-cells = <1>;
  18. #size-cells = <1>;
  19. ranges;
  20. /*
  21. * This is a dummy clock, to be used as placeholder on
  22. * other mux clocks when a specific parent clock is not
  23. * yet implemented. It should be dropped when the driver
  24. * is complete.
  25. */
  26. dummy: dummy {
  27. compatible = "fixed-clock";
  28. clock-frequency = <0>;
  29. #clock-cells = <0>;
  30. };
  31. xin24m: xin24m {
  32. compatible = "fixed-clock";
  33. clock-frequency = <24000000>;
  34. #clock-cells = <0>;
  35. };
  36. dummy48m: dummy48m {
  37. compatible = "fixed-clock";
  38. clock-frequency = <48000000>;
  39. #clock-cells = <0>;
  40. };
  41. dummy150m: dummy150m {
  42. compatible = "fixed-clock";
  43. clock-frequency = <150000000>;
  44. #clock-cells = <0>;
  45. };
  46. clk_gates0: gate-clk@200000d0 {
  47. compatible = "rockchip,rk2928-gate-clk";
  48. reg = <0x200000d0 0x4>;
  49. clocks = <&dummy>, <&dummy>,
  50. <&dummy>, <&dummy>,
  51. <&dummy>, <&dummy>,
  52. <&dummy>, <&dummy>,
  53. <&dummy>, <&dummy>,
  54. <&dummy>, <&dummy>,
  55. <&dummy>, <&dummy>,
  56. <&dummy>, <&dummy>;
  57. clock-output-names =
  58. "gate_core_periph", "gate_cpu_gpll",
  59. "gate_ddrphy", "gate_aclk_cpu",
  60. "gate_hclk_cpu", "gate_pclk_cpu",
  61. "gate_atclk_cpu", "gate_i2s0",
  62. "gate_i2s0_frac", "gate_i2s1",
  63. "gate_i2s1_frac", "gate_i2s2",
  64. "gate_i2s2_frac", "gate_spdif",
  65. "gate_spdif_frac", "gate_testclk";
  66. #clock-cells = <1>;
  67. };
  68. clk_gates1: gate-clk@200000d4 {
  69. compatible = "rockchip,rk2928-gate-clk";
  70. reg = <0x200000d4 0x4>;
  71. clocks = <&xin24m>, <&xin24m>,
  72. <&xin24m>, <&dummy>,
  73. <&dummy>, <&xin24m>,
  74. <&xin24m>, <&dummy>,
  75. <&xin24m>, <&dummy>,
  76. <&xin24m>, <&dummy>,
  77. <&xin24m>, <&dummy>,
  78. <&xin24m>, <&dummy>;
  79. clock-output-names =
  80. "gate_timer0", "gate_timer1",
  81. "gate_timer2", "gate_jtag",
  82. "gate_aclk_lcdc1_src", "gate_otgphy0",
  83. "gate_otgphy1", "gate_ddr_gpll",
  84. "gate_uart0", "gate_frac_uart0",
  85. "gate_uart1", "gate_frac_uart1",
  86. "gate_uart2", "gate_frac_uart2",
  87. "gate_uart3", "gate_frac_uart3";
  88. #clock-cells = <1>;
  89. };
  90. clk_gates2: gate-clk@200000d8 {
  91. compatible = "rockchip,rk2928-gate-clk";
  92. reg = <0x200000d8 0x4>;
  93. clocks = <&clk_gates2 1>, <&dummy>,
  94. <&dummy>, <&dummy>,
  95. <&dummy>, <&dummy>,
  96. <&clk_gates2 3>, <&dummy>,
  97. <&dummy>, <&dummy>,
  98. <&dummy>, <&dummy48m>,
  99. <&dummy>, <&dummy48m>,
  100. <&dummy>, <&dummy>;
  101. clock-output-names =
  102. "gate_periph_src", "gate_aclk_periph",
  103. "gate_hclk_periph", "gate_pclk_periph",
  104. "gate_smc", "gate_mac",
  105. "gate_hsadc", "gate_hsadc_frac",
  106. "gate_saradc", "gate_spi0",
  107. "gate_spi1", "gate_mmc0",
  108. "gate_mac_lbtest", "gate_mmc1",
  109. "gate_emmc", "gate_tsadc";
  110. #clock-cells = <1>;
  111. };
  112. clk_gates3: gate-clk@200000dc {
  113. compatible = "rockchip,rk2928-gate-clk";
  114. reg = <0x200000dc 0x4>;
  115. clocks = <&dummy>, <&dummy>,
  116. <&dummy>, <&dummy>,
  117. <&dummy>, <&dummy>,
  118. <&dummy>, <&dummy>,
  119. <&dummy>, <&dummy>,
  120. <&dummy>, <&dummy>,
  121. <&dummy>, <&dummy>,
  122. <&dummy>, <&dummy>;
  123. clock-output-names =
  124. "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
  125. "gate_dclk_lcdc1", "gate_pclkin_cif0",
  126. "gate_pclkin_cif1", "reserved",
  127. "reserved", "gate_cif0_out",
  128. "gate_cif1_out", "gate_aclk_vepu",
  129. "gate_hclk_vepu", "gate_aclk_vdpu",
  130. "gate_hclk_vdpu", "gate_gpu_src",
  131. "reserved", "gate_xin27m";
  132. #clock-cells = <1>;
  133. };
  134. clk_gates4: gate-clk@200000e0 {
  135. compatible = "rockchip,rk2928-gate-clk";
  136. reg = <0x200000e0 0x4>;
  137. clocks = <&clk_gates2 2>, <&clk_gates2 3>,
  138. <&clk_gates2 1>, <&clk_gates2 1>,
  139. <&clk_gates2 1>, <&clk_gates2 2>,
  140. <&clk_gates2 2>, <&clk_gates2 2>,
  141. <&clk_gates0 4>, <&clk_gates0 4>,
  142. <&clk_gates0 3>, <&clk_gates0 3>,
  143. <&clk_gates0 3>, <&clk_gates2 3>,
  144. <&clk_gates0 4>;
  145. clock-output-names =
  146. "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
  147. "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
  148. "gate_aclk_pei_niu", "gate_hclk_usb_peri",
  149. "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
  150. "gate_hclk_cpubus", "gate_hclk_ahb2apb",
  151. "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
  152. "gate_aclk_intmem", "gate_pclk_tsadc",
  153. "gate_hclk_hdmi";
  154. #clock-cells = <1>;
  155. };
  156. clk_gates5: gate-clk@200000e4 {
  157. compatible = "rockchip,rk2928-gate-clk";
  158. reg = <0x200000e4 0x4>;
  159. clocks = <&clk_gates0 3>, <&clk_gates2 1>,
  160. <&clk_gates0 5>, <&clk_gates0 5>,
  161. <&clk_gates0 5>, <&clk_gates0 5>,
  162. <&clk_gates0 4>, <&clk_gates0 5>,
  163. <&clk_gates2 1>, <&clk_gates2 2>,
  164. <&clk_gates2 2>, <&clk_gates2 2>,
  165. <&clk_gates2 2>, <&clk_gates4 5>,
  166. <&clk_gates4 5>, <&dummy>;
  167. clock-output-names =
  168. "gate_aclk_dmac1", "gate_aclk_dmac2",
  169. "gate_pclk_efuse", "gate_pclk_tzpc",
  170. "gate_pclk_grf", "gate_pclk_pmu",
  171. "gate_hclk_rom", "gate_pclk_ddrupctl",
  172. "gate_aclk_smc", "gate_hclk_nandc",
  173. "gate_hclk_mmc0", "gate_hclk_mmc1",
  174. "gate_hclk_emmc", "gate_hclk_otg0",
  175. "gate_hclk_otg1", "gate_aclk_gpu";
  176. #clock-cells = <1>;
  177. };
  178. clk_gates6: gate-clk@200000e8 {
  179. compatible = "rockchip,rk2928-gate-clk";
  180. reg = <0x200000e8 0x4>;
  181. clocks = <&clk_gates3 0>, <&clk_gates0 4>,
  182. <&clk_gates0 4>, <&clk_gates1 4>,
  183. <&clk_gates0 4>, <&clk_gates3 0>,
  184. <&clk_gates0 4>, <&clk_gates1 4>,
  185. <&clk_gates3 0>, <&clk_gates0 4>,
  186. <&clk_gates0 4>, <&clk_gates1 4>,
  187. <&clk_gates0 4>, <&clk_gates3 0>,
  188. <&dummy>, <&dummy>;
  189. clock-output-names =
  190. "gate_aclk_lcdc0", "gate_hclk_lcdc0",
  191. "gate_hclk_lcdc1", "gate_aclk_lcdc1",
  192. "gate_hclk_cif0", "gate_aclk_cif0",
  193. "gate_hclk_cif1", "gate_aclk_cif1",
  194. "gate_aclk_ipp", "gate_hclk_ipp",
  195. "gate_hclk_rga", "gate_aclk_rga",
  196. "gate_hclk_vio_bus", "gate_aclk_vio0",
  197. "gate_aclk_vcodec", "gate_shclk_vio_h2h";
  198. #clock-cells = <1>;
  199. };
  200. clk_gates7: gate-clk@200000ec {
  201. compatible = "rockchip,rk2928-gate-clk";
  202. reg = <0x200000ec 0x4>;
  203. clocks = <&clk_gates2 2>, <&clk_gates0 4>,
  204. <&clk_gates0 4>, <&clk_gates0 4>,
  205. <&clk_gates0 4>, <&clk_gates2 2>,
  206. <&clk_gates2 2>, <&clk_gates0 5>,
  207. <&clk_gates0 5>, <&clk_gates0 5>,
  208. <&clk_gates0 5>, <&clk_gates2 3>,
  209. <&clk_gates2 3>, <&clk_gates2 3>,
  210. <&clk_gates2 3>, <&clk_gates2 3>;
  211. clock-output-names =
  212. "gate_hclk_emac", "gate_hclk_spdif",
  213. "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
  214. "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
  215. "gate_hclk_pidf", "gate_pclk_timer0",
  216. "gate_pclk_timer1", "gate_pclk_timer2",
  217. "gate_pclk_pwm01", "gate_pclk_pwm23",
  218. "gate_pclk_spi0", "gate_pclk_spi1",
  219. "gate_pclk_saradc", "gate_pclk_wdt";
  220. #clock-cells = <1>;
  221. };
  222. clk_gates8: gate-clk@200000f0 {
  223. compatible = "rockchip,rk2928-gate-clk";
  224. reg = <0x200000f0 0x4>;
  225. clocks = <&clk_gates0 5>, <&clk_gates0 5>,
  226. <&clk_gates2 3>, <&clk_gates2 3>,
  227. <&clk_gates0 5>, <&clk_gates0 5>,
  228. <&clk_gates2 3>, <&clk_gates2 3>,
  229. <&clk_gates2 3>, <&clk_gates0 5>,
  230. <&clk_gates0 5>, <&clk_gates0 5>,
  231. <&clk_gates2 3>, <&clk_gates2 3>,
  232. <&dummy>, <&clk_gates0 5>;
  233. clock-output-names =
  234. "gate_pclk_uart0", "gate_pclk_uart1",
  235. "gate_pclk_uart2", "gate_pclk_uart3",
  236. "gate_pclk_i2c0", "gate_pclk_i2c1",
  237. "gate_pclk_i2c2", "gate_pclk_i2c3",
  238. "gate_pclk_i2c4", "gate_pclk_gpio0",
  239. "gate_pclk_gpio1", "gate_pclk_gpio2",
  240. "gate_pclk_gpio3", "gate_pclk_gpio4",
  241. "reserved", "gate_pclk_gpio6";
  242. #clock-cells = <1>;
  243. };
  244. clk_gates9: gate-clk@200000f4 {
  245. compatible = "rockchip,rk2928-gate-clk";
  246. reg = <0x200000f4 0x4>;
  247. clocks = <&dummy>, <&clk_gates0 5>,
  248. <&dummy>, <&dummy>,
  249. <&dummy>, <&clk_gates1 4>,
  250. <&clk_gates0 5>, <&dummy>,
  251. <&dummy>, <&dummy>,
  252. <&dummy>;
  253. clock-output-names =
  254. "gate_clk_core_dbg", "gate_pclk_dbg",
  255. "gate_clk_trace", "gate_atclk",
  256. "gate_clk_l2c", "gate_aclk_vio1",
  257. "gate_pclk_publ", "gate_aclk_intmem0",
  258. "gate_aclk_intmem1", "gate_aclk_intmem2",
  259. "gate_aclk_intmem3";
  260. #clock-cells = <1>;
  261. };
  262. };
  263. };