imx51.dtsi 19 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include "skeleton.dtsi"
  13. #include "imx51-pinfunc.h"
  14. / {
  15. aliases {
  16. serial0 = &uart1;
  17. serial1 = &uart2;
  18. serial2 = &uart3;
  19. gpio0 = &gpio1;
  20. gpio1 = &gpio2;
  21. gpio2 = &gpio3;
  22. gpio3 = &gpio4;
  23. };
  24. tzic: tz-interrupt-controller@e0000000 {
  25. compatible = "fsl,imx51-tzic", "fsl,tzic";
  26. interrupt-controller;
  27. #interrupt-cells = <1>;
  28. reg = <0xe0000000 0x4000>;
  29. };
  30. clocks {
  31. #address-cells = <1>;
  32. #size-cells = <0>;
  33. ckil {
  34. compatible = "fsl,imx-ckil", "fixed-clock";
  35. clock-frequency = <32768>;
  36. };
  37. ckih1 {
  38. compatible = "fsl,imx-ckih1", "fixed-clock";
  39. clock-frequency = <22579200>;
  40. };
  41. ckih2 {
  42. compatible = "fsl,imx-ckih2", "fixed-clock";
  43. clock-frequency = <0>;
  44. };
  45. osc {
  46. compatible = "fsl,imx-osc", "fixed-clock";
  47. clock-frequency = <24000000>;
  48. };
  49. };
  50. cpus {
  51. #address-cells = <1>;
  52. #size-cells = <0>;
  53. cpu@0 {
  54. device_type = "cpu";
  55. compatible = "arm,cortex-a8";
  56. reg = <0>;
  57. clock-latency = <61036>; /* two CLK32 periods */
  58. clocks = <&clks 24>;
  59. clock-names = "cpu";
  60. operating-points = <
  61. /* kHz uV (No regulator support) */
  62. 160000 0
  63. 800000 0
  64. >;
  65. };
  66. };
  67. soc {
  68. #address-cells = <1>;
  69. #size-cells = <1>;
  70. compatible = "simple-bus";
  71. interrupt-parent = <&tzic>;
  72. ranges;
  73. ipu: ipu@40000000 {
  74. #crtc-cells = <1>;
  75. compatible = "fsl,imx51-ipu";
  76. reg = <0x40000000 0x20000000>;
  77. interrupts = <11 10>;
  78. clocks = <&clks 59>, <&clks 110>, <&clks 61>;
  79. clock-names = "bus", "di0", "di1";
  80. resets = <&src 2>;
  81. };
  82. aips@70000000 { /* AIPS1 */
  83. compatible = "fsl,aips-bus", "simple-bus";
  84. #address-cells = <1>;
  85. #size-cells = <1>;
  86. reg = <0x70000000 0x10000000>;
  87. ranges;
  88. spba@70000000 {
  89. compatible = "fsl,spba-bus", "simple-bus";
  90. #address-cells = <1>;
  91. #size-cells = <1>;
  92. reg = <0x70000000 0x40000>;
  93. ranges;
  94. esdhc1: esdhc@70004000 {
  95. compatible = "fsl,imx51-esdhc";
  96. reg = <0x70004000 0x4000>;
  97. interrupts = <1>;
  98. clocks = <&clks 44>, <&clks 0>, <&clks 71>;
  99. clock-names = "ipg", "ahb", "per";
  100. status = "disabled";
  101. };
  102. esdhc2: esdhc@70008000 {
  103. compatible = "fsl,imx51-esdhc";
  104. reg = <0x70008000 0x4000>;
  105. interrupts = <2>;
  106. clocks = <&clks 45>, <&clks 0>, <&clks 72>;
  107. clock-names = "ipg", "ahb", "per";
  108. bus-width = <4>;
  109. status = "disabled";
  110. };
  111. uart3: serial@7000c000 {
  112. compatible = "fsl,imx51-uart", "fsl,imx21-uart";
  113. reg = <0x7000c000 0x4000>;
  114. interrupts = <33>;
  115. clocks = <&clks 32>, <&clks 33>;
  116. clock-names = "ipg", "per";
  117. status = "disabled";
  118. };
  119. ecspi1: ecspi@70010000 {
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. compatible = "fsl,imx51-ecspi";
  123. reg = <0x70010000 0x4000>;
  124. interrupts = <36>;
  125. clocks = <&clks 51>, <&clks 52>;
  126. clock-names = "ipg", "per";
  127. status = "disabled";
  128. };
  129. ssi2: ssi@70014000 {
  130. compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
  131. reg = <0x70014000 0x4000>;
  132. interrupts = <30>;
  133. clocks = <&clks 49>;
  134. fsl,fifo-depth = <15>;
  135. fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
  136. status = "disabled";
  137. };
  138. esdhc3: esdhc@70020000 {
  139. compatible = "fsl,imx51-esdhc";
  140. reg = <0x70020000 0x4000>;
  141. interrupts = <3>;
  142. clocks = <&clks 46>, <&clks 0>, <&clks 73>;
  143. clock-names = "ipg", "ahb", "per";
  144. bus-width = <4>;
  145. status = "disabled";
  146. };
  147. esdhc4: esdhc@70024000 {
  148. compatible = "fsl,imx51-esdhc";
  149. reg = <0x70024000 0x4000>;
  150. interrupts = <4>;
  151. clocks = <&clks 47>, <&clks 0>, <&clks 74>;
  152. clock-names = "ipg", "ahb", "per";
  153. bus-width = <4>;
  154. status = "disabled";
  155. };
  156. };
  157. usbphy0: usbphy@0 {
  158. compatible = "usb-nop-xceiv";
  159. clocks = <&clks 124>;
  160. clock-names = "main_clk";
  161. status = "okay";
  162. };
  163. usbotg: usb@73f80000 {
  164. compatible = "fsl,imx51-usb", "fsl,imx27-usb";
  165. reg = <0x73f80000 0x0200>;
  166. interrupts = <18>;
  167. clocks = <&clks 108>;
  168. fsl,usbmisc = <&usbmisc 0>;
  169. fsl,usbphy = <&usbphy0>;
  170. status = "disabled";
  171. };
  172. usbh1: usb@73f80200 {
  173. compatible = "fsl,imx51-usb", "fsl,imx27-usb";
  174. reg = <0x73f80200 0x0200>;
  175. interrupts = <14>;
  176. clocks = <&clks 108>;
  177. fsl,usbmisc = <&usbmisc 1>;
  178. status = "disabled";
  179. };
  180. usbh2: usb@73f80400 {
  181. compatible = "fsl,imx51-usb", "fsl,imx27-usb";
  182. reg = <0x73f80400 0x0200>;
  183. interrupts = <16>;
  184. clocks = <&clks 108>;
  185. fsl,usbmisc = <&usbmisc 2>;
  186. status = "disabled";
  187. };
  188. usbh3: usb@73f80600 {
  189. compatible = "fsl,imx51-usb", "fsl,imx27-usb";
  190. reg = <0x73f80600 0x0200>;
  191. interrupts = <17>;
  192. clocks = <&clks 108>;
  193. fsl,usbmisc = <&usbmisc 3>;
  194. status = "disabled";
  195. };
  196. usbmisc: usbmisc@73f80800 {
  197. #index-cells = <1>;
  198. compatible = "fsl,imx51-usbmisc";
  199. reg = <0x73f80800 0x200>;
  200. clocks = <&clks 108>;
  201. };
  202. gpio1: gpio@73f84000 {
  203. compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
  204. reg = <0x73f84000 0x4000>;
  205. interrupts = <50 51>;
  206. gpio-controller;
  207. #gpio-cells = <2>;
  208. interrupt-controller;
  209. #interrupt-cells = <2>;
  210. };
  211. gpio2: gpio@73f88000 {
  212. compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
  213. reg = <0x73f88000 0x4000>;
  214. interrupts = <52 53>;
  215. gpio-controller;
  216. #gpio-cells = <2>;
  217. interrupt-controller;
  218. #interrupt-cells = <2>;
  219. };
  220. gpio3: gpio@73f8c000 {
  221. compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
  222. reg = <0x73f8c000 0x4000>;
  223. interrupts = <54 55>;
  224. gpio-controller;
  225. #gpio-cells = <2>;
  226. interrupt-controller;
  227. #interrupt-cells = <2>;
  228. };
  229. gpio4: gpio@73f90000 {
  230. compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
  231. reg = <0x73f90000 0x4000>;
  232. interrupts = <56 57>;
  233. gpio-controller;
  234. #gpio-cells = <2>;
  235. interrupt-controller;
  236. #interrupt-cells = <2>;
  237. };
  238. kpp: kpp@73f94000 {
  239. compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
  240. reg = <0x73f94000 0x4000>;
  241. interrupts = <60>;
  242. clocks = <&clks 0>;
  243. status = "disabled";
  244. };
  245. wdog1: wdog@73f98000 {
  246. compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
  247. reg = <0x73f98000 0x4000>;
  248. interrupts = <58>;
  249. clocks = <&clks 0>;
  250. };
  251. wdog2: wdog@73f9c000 {
  252. compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
  253. reg = <0x73f9c000 0x4000>;
  254. interrupts = <59>;
  255. clocks = <&clks 0>;
  256. status = "disabled";
  257. };
  258. gpt: timer@73fa0000 {
  259. compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
  260. reg = <0x73fa0000 0x4000>;
  261. interrupts = <39>;
  262. clocks = <&clks 36>, <&clks 41>;
  263. clock-names = "ipg", "per";
  264. };
  265. iomuxc: iomuxc@73fa8000 {
  266. compatible = "fsl,imx51-iomuxc";
  267. reg = <0x73fa8000 0x4000>;
  268. audmux {
  269. pinctrl_audmux_1: audmuxgrp-1 {
  270. fsl,pins = <
  271. MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
  272. MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
  273. MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
  274. MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
  275. >;
  276. };
  277. };
  278. fec {
  279. pinctrl_fec_1: fecgrp-1 {
  280. fsl,pins = <
  281. MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
  282. MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
  283. MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
  284. MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
  285. MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
  286. MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
  287. MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
  288. MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
  289. MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
  290. MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
  291. MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
  292. MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
  293. MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
  294. MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
  295. MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
  296. MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
  297. MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
  298. >;
  299. };
  300. pinctrl_fec_2: fecgrp-2 {
  301. fsl,pins = <
  302. MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
  303. MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
  304. MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
  305. MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
  306. MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
  307. MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
  308. MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
  309. MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
  310. MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
  311. MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
  312. MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
  313. MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
  314. MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
  315. MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
  316. MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
  317. MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
  318. MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
  319. MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
  320. >;
  321. };
  322. };
  323. ecspi1 {
  324. pinctrl_ecspi1_1: ecspi1grp-1 {
  325. fsl,pins = <
  326. MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
  327. MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
  328. MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
  329. >;
  330. };
  331. };
  332. ecspi2 {
  333. pinctrl_ecspi2_1: ecspi2grp-1 {
  334. fsl,pins = <
  335. MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
  336. MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
  337. MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
  338. >;
  339. };
  340. };
  341. esdhc1 {
  342. pinctrl_esdhc1_1: esdhc1grp-1 {
  343. fsl,pins = <
  344. MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
  345. MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
  346. MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
  347. MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
  348. MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
  349. MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
  350. >;
  351. };
  352. };
  353. esdhc2 {
  354. pinctrl_esdhc2_1: esdhc2grp-1 {
  355. fsl,pins = <
  356. MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
  357. MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
  358. MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
  359. MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
  360. MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
  361. MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
  362. >;
  363. };
  364. };
  365. i2c2 {
  366. pinctrl_i2c2_1: i2c2grp-1 {
  367. fsl,pins = <
  368. MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
  369. MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
  370. >;
  371. };
  372. pinctrl_i2c2_2: i2c2grp-2 {
  373. fsl,pins = <
  374. MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
  375. MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
  376. >;
  377. };
  378. };
  379. ipu_disp1 {
  380. pinctrl_ipu_disp1_1: ipudisp1grp-1 {
  381. fsl,pins = <
  382. MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
  383. MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
  384. MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
  385. MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
  386. MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
  387. MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
  388. MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
  389. MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
  390. MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
  391. MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
  392. MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
  393. MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
  394. MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
  395. MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
  396. MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
  397. MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
  398. MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
  399. MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
  400. MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
  401. MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
  402. MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
  403. MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
  404. MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
  405. MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
  406. MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
  407. MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
  408. >;
  409. };
  410. };
  411. ipu_disp2 {
  412. pinctrl_ipu_disp2_1: ipudisp2grp-1 {
  413. fsl,pins = <
  414. MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
  415. MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
  416. MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
  417. MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
  418. MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
  419. MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
  420. MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
  421. MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
  422. MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
  423. MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
  424. MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
  425. MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
  426. MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
  427. MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
  428. MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
  429. MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
  430. MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
  431. MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
  432. MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
  433. MX51_PAD_DI_GP4__DI2_PIN15 0x5
  434. >;
  435. };
  436. };
  437. pata {
  438. pinctrl_pata_1: patagrp-1 {
  439. fsl,pins = <
  440. MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
  441. MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
  442. MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
  443. MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
  444. MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
  445. MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
  446. MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
  447. MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
  448. MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
  449. MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
  450. MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
  451. MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
  452. MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
  453. MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
  454. MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
  455. MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
  456. MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
  457. MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
  458. MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
  459. MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
  460. MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
  461. MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
  462. MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
  463. MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
  464. MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
  465. MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
  466. MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
  467. MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
  468. MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
  469. >;
  470. };
  471. };
  472. uart1 {
  473. pinctrl_uart1_1: uart1grp-1 {
  474. fsl,pins = <
  475. MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
  476. MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
  477. MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
  478. MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
  479. >;
  480. };
  481. };
  482. uart2 {
  483. pinctrl_uart2_1: uart2grp-1 {
  484. fsl,pins = <
  485. MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
  486. MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
  487. >;
  488. };
  489. };
  490. uart3 {
  491. pinctrl_uart3_1: uart3grp-1 {
  492. fsl,pins = <
  493. MX51_PAD_EIM_D25__UART3_RXD 0x1c5
  494. MX51_PAD_EIM_D26__UART3_TXD 0x1c5
  495. MX51_PAD_EIM_D27__UART3_RTS 0x1c5
  496. MX51_PAD_EIM_D24__UART3_CTS 0x1c5
  497. >;
  498. };
  499. pinctrl_uart3_2: uart3grp-2 {
  500. fsl,pins = <
  501. MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
  502. MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
  503. >;
  504. };
  505. };
  506. kpp {
  507. pinctrl_kpp_1: kppgrp-1 {
  508. fsl,pins = <
  509. MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
  510. MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
  511. MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
  512. MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
  513. MX51_PAD_KEY_COL0__KEY_COL0 0xe8
  514. MX51_PAD_KEY_COL1__KEY_COL1 0xe8
  515. MX51_PAD_KEY_COL2__KEY_COL2 0xe8
  516. MX51_PAD_KEY_COL3__KEY_COL3 0xe8
  517. >;
  518. };
  519. };
  520. };
  521. pwm1: pwm@73fb4000 {
  522. #pwm-cells = <2>;
  523. compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
  524. reg = <0x73fb4000 0x4000>;
  525. clocks = <&clks 37>, <&clks 38>;
  526. clock-names = "ipg", "per";
  527. interrupts = <61>;
  528. };
  529. pwm2: pwm@73fb8000 {
  530. #pwm-cells = <2>;
  531. compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
  532. reg = <0x73fb8000 0x4000>;
  533. clocks = <&clks 39>, <&clks 40>;
  534. clock-names = "ipg", "per";
  535. interrupts = <94>;
  536. };
  537. uart1: serial@73fbc000 {
  538. compatible = "fsl,imx51-uart", "fsl,imx21-uart";
  539. reg = <0x73fbc000 0x4000>;
  540. interrupts = <31>;
  541. clocks = <&clks 28>, <&clks 29>;
  542. clock-names = "ipg", "per";
  543. status = "disabled";
  544. };
  545. uart2: serial@73fc0000 {
  546. compatible = "fsl,imx51-uart", "fsl,imx21-uart";
  547. reg = <0x73fc0000 0x4000>;
  548. interrupts = <32>;
  549. clocks = <&clks 30>, <&clks 31>;
  550. clock-names = "ipg", "per";
  551. status = "disabled";
  552. };
  553. src: src@73fd0000 {
  554. compatible = "fsl,imx51-src";
  555. reg = <0x73fd0000 0x4000>;
  556. #reset-cells = <1>;
  557. };
  558. clks: ccm@73fd4000{
  559. compatible = "fsl,imx51-ccm";
  560. reg = <0x73fd4000 0x4000>;
  561. interrupts = <0 71 0x04 0 72 0x04>;
  562. #clock-cells = <1>;
  563. };
  564. };
  565. aips@80000000 { /* AIPS2 */
  566. compatible = "fsl,aips-bus", "simple-bus";
  567. #address-cells = <1>;
  568. #size-cells = <1>;
  569. reg = <0x80000000 0x10000000>;
  570. ranges;
  571. ecspi2: ecspi@83fac000 {
  572. #address-cells = <1>;
  573. #size-cells = <0>;
  574. compatible = "fsl,imx51-ecspi";
  575. reg = <0x83fac000 0x4000>;
  576. interrupts = <37>;
  577. clocks = <&clks 53>, <&clks 54>;
  578. clock-names = "ipg", "per";
  579. status = "disabled";
  580. };
  581. sdma: sdma@83fb0000 {
  582. compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
  583. reg = <0x83fb0000 0x4000>;
  584. interrupts = <6>;
  585. clocks = <&clks 56>, <&clks 56>;
  586. clock-names = "ipg", "ahb";
  587. fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
  588. };
  589. cspi: cspi@83fc0000 {
  590. #address-cells = <1>;
  591. #size-cells = <0>;
  592. compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
  593. reg = <0x83fc0000 0x4000>;
  594. interrupts = <38>;
  595. clocks = <&clks 55>, <&clks 55>;
  596. clock-names = "ipg", "per";
  597. status = "disabled";
  598. };
  599. i2c2: i2c@83fc4000 {
  600. #address-cells = <1>;
  601. #size-cells = <0>;
  602. compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
  603. reg = <0x83fc4000 0x4000>;
  604. interrupts = <63>;
  605. clocks = <&clks 35>;
  606. status = "disabled";
  607. };
  608. i2c1: i2c@83fc8000 {
  609. #address-cells = <1>;
  610. #size-cells = <0>;
  611. compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
  612. reg = <0x83fc8000 0x4000>;
  613. interrupts = <62>;
  614. clocks = <&clks 34>;
  615. status = "disabled";
  616. };
  617. ssi1: ssi@83fcc000 {
  618. compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
  619. reg = <0x83fcc000 0x4000>;
  620. interrupts = <29>;
  621. clocks = <&clks 48>;
  622. fsl,fifo-depth = <15>;
  623. fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
  624. status = "disabled";
  625. };
  626. audmux: audmux@83fd0000 {
  627. compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
  628. reg = <0x83fd0000 0x4000>;
  629. status = "disabled";
  630. };
  631. nfc: nand@83fdb000 {
  632. compatible = "fsl,imx51-nand";
  633. reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
  634. interrupts = <8>;
  635. clocks = <&clks 60>;
  636. status = "disabled";
  637. };
  638. pata: pata@83fe0000 {
  639. compatible = "fsl,imx51-pata", "fsl,imx27-pata";
  640. reg = <0x83fe0000 0x4000>;
  641. interrupts = <70>;
  642. clocks = <&clks 161>;
  643. status = "disabled";
  644. };
  645. ssi3: ssi@83fe8000 {
  646. compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
  647. reg = <0x83fe8000 0x4000>;
  648. interrupts = <96>;
  649. clocks = <&clks 50>;
  650. fsl,fifo-depth = <15>;
  651. fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
  652. status = "disabled";
  653. };
  654. fec: ethernet@83fec000 {
  655. compatible = "fsl,imx51-fec", "fsl,imx27-fec";
  656. reg = <0x83fec000 0x4000>;
  657. interrupts = <87>;
  658. clocks = <&clks 42>, <&clks 42>, <&clks 42>;
  659. clock-names = "ipg", "ahb", "ptp";
  660. status = "disabled";
  661. };
  662. };
  663. };
  664. };