exynos5420.dtsi 3.2 KB

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  1. /*
  2. * SAMSUNG EXYNOS5420 SoC device tree source
  3. *
  4. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
  8. * EXYNOS5420 based board files can include this file and provide
  9. * values for board specfic bindings.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include "exynos5.dtsi"
  16. /include/ "exynos5420-pinctrl.dtsi"
  17. / {
  18. compatible = "samsung,exynos5420";
  19. aliases {
  20. pinctrl0 = &pinctrl_0;
  21. pinctrl1 = &pinctrl_1;
  22. pinctrl2 = &pinctrl_2;
  23. pinctrl3 = &pinctrl_3;
  24. pinctrl4 = &pinctrl_4;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu0: cpu@0 {
  30. device_type = "cpu";
  31. compatible = "arm,cortex-a15";
  32. reg = <0x0>;
  33. clock-frequency = <1800000000>;
  34. };
  35. cpu1: cpu@1 {
  36. device_type = "cpu";
  37. compatible = "arm,cortex-a15";
  38. reg = <0x1>;
  39. clock-frequency = <1800000000>;
  40. };
  41. cpu2: cpu@2 {
  42. device_type = "cpu";
  43. compatible = "arm,cortex-a15";
  44. reg = <0x2>;
  45. clock-frequency = <1800000000>;
  46. };
  47. cpu3: cpu@3 {
  48. device_type = "cpu";
  49. compatible = "arm,cortex-a15";
  50. reg = <0x3>;
  51. clock-frequency = <1800000000>;
  52. };
  53. };
  54. clock: clock-controller@0x10010000 {
  55. compatible = "samsung,exynos5420-clock";
  56. reg = <0x10010000 0x30000>;
  57. #clock-cells = <1>;
  58. };
  59. mct@101C0000 {
  60. compatible = "samsung,exynos4210-mct";
  61. reg = <0x101C0000 0x800>;
  62. interrupt-controller;
  63. #interrups-cells = <1>;
  64. interrupt-parent = <&mct_map>;
  65. interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
  66. clocks = <&clock 1>, <&clock 315>;
  67. clock-names = "fin_pll", "mct";
  68. mct_map: mct-map {
  69. #interrupt-cells = <1>;
  70. #address-cells = <0>;
  71. #size-cells = <0>;
  72. interrupt-map = <0 &combiner 23 3>,
  73. <1 &combiner 23 4>,
  74. <2 &combiner 25 2>,
  75. <3 &combiner 25 3>,
  76. <4 &gic 0 120 0>,
  77. <5 &gic 0 121 0>,
  78. <6 &gic 0 122 0>,
  79. <7 &gic 0 123 0>;
  80. };
  81. };
  82. pinctrl_0: pinctrl@13400000 {
  83. compatible = "samsung,exynos5420-pinctrl";
  84. reg = <0x13400000 0x1000>;
  85. interrupts = <0 45 0>;
  86. wakeup-interrupt-controller {
  87. compatible = "samsung,exynos4210-wakeup-eint";
  88. interrupt-parent = <&gic>;
  89. interrupts = <0 32 0>;
  90. };
  91. };
  92. pinctrl_1: pinctrl@13410000 {
  93. compatible = "samsung,exynos5420-pinctrl";
  94. reg = <0x13410000 0x1000>;
  95. interrupts = <0 78 0>;
  96. };
  97. pinctrl_2: pinctrl@14000000 {
  98. compatible = "samsung,exynos5420-pinctrl";
  99. reg = <0x14000000 0x1000>;
  100. interrupts = <0 46 0>;
  101. };
  102. pinctrl_3: pinctrl@14010000 {
  103. compatible = "samsung,exynos5420-pinctrl";
  104. reg = <0x14010000 0x1000>;
  105. interrupts = <0 50 0>;
  106. };
  107. pinctrl_4: pinctrl@03860000 {
  108. compatible = "samsung,exynos5420-pinctrl";
  109. reg = <0x03860000 0x1000>;
  110. interrupts = <0 47 0>;
  111. };
  112. serial@12C00000 {
  113. clocks = <&clock 257>, <&clock 128>;
  114. clock-names = "uart", "clk_uart_baud0";
  115. };
  116. serial@12C10000 {
  117. clocks = <&clock 258>, <&clock 129>;
  118. clock-names = "uart", "clk_uart_baud0";
  119. };
  120. serial@12C20000 {
  121. clocks = <&clock 259>, <&clock 130>;
  122. clock-names = "uart", "clk_uart_baud0";
  123. };
  124. serial@12C30000 {
  125. clocks = <&clock 260>, <&clock 131>;
  126. clock-names = "uart", "clk_uart_baud0";
  127. };
  128. };