ecx-common.dtsi 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239
  1. /*
  2. * Copyright 2011-2012 Calxeda, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. / {
  17. chosen {
  18. bootargs = "console=ttyAMA0";
  19. };
  20. soc {
  21. #address-cells = <1>;
  22. #size-cells = <1>;
  23. compatible = "simple-bus";
  24. interrupt-parent = <&intc>;
  25. sata@ffe08000 {
  26. compatible = "calxeda,hb-ahci";
  27. reg = <0xffe08000 0x10000>;
  28. interrupts = <0 83 4>;
  29. dma-coherent;
  30. calxeda,port-phys = <&combophy5 0 &combophy0 0
  31. &combophy0 1 &combophy0 2
  32. &combophy0 3>;
  33. calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
  34. calxeda,led-order = <4 0 1 2 3>;
  35. };
  36. sdhci@ffe0e000 {
  37. compatible = "calxeda,hb-sdhci";
  38. reg = <0xffe0e000 0x1000>;
  39. interrupts = <0 90 4>;
  40. clocks = <&eclk>;
  41. status = "disabled";
  42. };
  43. memory-controller@fff00000 {
  44. compatible = "calxeda,hb-ddr-ctrl";
  45. reg = <0xfff00000 0x1000>;
  46. interrupts = <0 91 4>;
  47. };
  48. ipc@fff20000 {
  49. compatible = "arm,pl320", "arm,primecell";
  50. reg = <0xfff20000 0x1000>;
  51. interrupts = <0 7 4>;
  52. clocks = <&pclk>;
  53. clock-names = "apb_pclk";
  54. };
  55. gpioe: gpio@fff30000 {
  56. #gpio-cells = <2>;
  57. compatible = "arm,pl061", "arm,primecell";
  58. gpio-controller;
  59. reg = <0xfff30000 0x1000>;
  60. interrupts = <0 14 4>;
  61. clocks = <&pclk>;
  62. clock-names = "apb_pclk";
  63. status = "disabled";
  64. };
  65. gpiof: gpio@fff31000 {
  66. #gpio-cells = <2>;
  67. compatible = "arm,pl061", "arm,primecell";
  68. gpio-controller;
  69. reg = <0xfff31000 0x1000>;
  70. interrupts = <0 15 4>;
  71. clocks = <&pclk>;
  72. clock-names = "apb_pclk";
  73. status = "disabled";
  74. };
  75. gpiog: gpio@fff32000 {
  76. #gpio-cells = <2>;
  77. compatible = "arm,pl061", "arm,primecell";
  78. gpio-controller;
  79. reg = <0xfff32000 0x1000>;
  80. interrupts = <0 16 4>;
  81. clocks = <&pclk>;
  82. clock-names = "apb_pclk";
  83. status = "disabled";
  84. };
  85. gpioh: gpio@fff33000 {
  86. #gpio-cells = <2>;
  87. compatible = "arm,pl061", "arm,primecell";
  88. gpio-controller;
  89. reg = <0xfff33000 0x1000>;
  90. interrupts = <0 17 4>;
  91. clocks = <&pclk>;
  92. clock-names = "apb_pclk";
  93. status = "disabled";
  94. };
  95. timer@fff34000 {
  96. compatible = "arm,sp804", "arm,primecell";
  97. reg = <0xfff34000 0x1000>;
  98. interrupts = <0 18 4>;
  99. clocks = <&pclk>;
  100. clock-names = "apb_pclk";
  101. };
  102. rtc@fff35000 {
  103. compatible = "arm,pl031", "arm,primecell";
  104. reg = <0xfff35000 0x1000>;
  105. interrupts = <0 19 4>;
  106. clocks = <&pclk>;
  107. clock-names = "apb_pclk";
  108. };
  109. serial@fff36000 {
  110. compatible = "arm,pl011", "arm,primecell";
  111. reg = <0xfff36000 0x1000>;
  112. interrupts = <0 20 4>;
  113. clocks = <&pclk>;
  114. clock-names = "apb_pclk";
  115. };
  116. smic@fff3a000 {
  117. compatible = "ipmi-smic";
  118. device_type = "ipmi";
  119. reg = <0xfff3a000 0x1000>;
  120. interrupts = <0 24 4>;
  121. reg-size = <4>;
  122. reg-spacing = <4>;
  123. };
  124. sregs@fff3c000 {
  125. compatible = "calxeda,hb-sregs";
  126. reg = <0xfff3c000 0x1000>;
  127. clocks {
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. osc: oscillator {
  131. #clock-cells = <0>;
  132. compatible = "fixed-clock";
  133. clock-frequency = <33333000>;
  134. };
  135. ddrpll: ddrpll {
  136. #clock-cells = <0>;
  137. compatible = "calxeda,hb-pll-clock";
  138. clocks = <&osc>;
  139. reg = <0x108>;
  140. };
  141. a9pll: a9pll {
  142. #clock-cells = <0>;
  143. compatible = "calxeda,hb-pll-clock";
  144. clocks = <&osc>;
  145. reg = <0x100>;
  146. };
  147. a9periphclk: a9periphclk {
  148. #clock-cells = <0>;
  149. compatible = "calxeda,hb-a9periph-clock";
  150. clocks = <&a9pll>;
  151. reg = <0x104>;
  152. };
  153. a9bclk: a9bclk {
  154. #clock-cells = <0>;
  155. compatible = "calxeda,hb-a9bus-clock";
  156. clocks = <&a9pll>;
  157. reg = <0x104>;
  158. };
  159. emmcpll: emmcpll {
  160. #clock-cells = <0>;
  161. compatible = "calxeda,hb-pll-clock";
  162. clocks = <&osc>;
  163. reg = <0x10C>;
  164. };
  165. eclk: eclk {
  166. #clock-cells = <0>;
  167. compatible = "calxeda,hb-emmc-clock";
  168. clocks = <&emmcpll>;
  169. reg = <0x114>;
  170. };
  171. pclk: pclk {
  172. #clock-cells = <0>;
  173. compatible = "fixed-clock";
  174. clock-frequency = <150000000>;
  175. };
  176. };
  177. };
  178. dma@fff3d000 {
  179. compatible = "arm,pl330", "arm,primecell";
  180. reg = <0xfff3d000 0x1000>;
  181. interrupts = <0 92 4>;
  182. clocks = <&pclk>;
  183. clock-names = "apb_pclk";
  184. };
  185. ethernet@fff50000 {
  186. compatible = "calxeda,hb-xgmac";
  187. reg = <0xfff50000 0x1000>;
  188. interrupts = <0 77 4 0 78 4 0 79 4>;
  189. dma-coherent;
  190. };
  191. ethernet@fff51000 {
  192. compatible = "calxeda,hb-xgmac";
  193. reg = <0xfff51000 0x1000>;
  194. interrupts = <0 80 4 0 81 4 0 82 4>;
  195. dma-coherent;
  196. };
  197. combophy0: combo-phy@fff58000 {
  198. compatible = "calxeda,hb-combophy";
  199. #phy-cells = <1>;
  200. reg = <0xfff58000 0x1000>;
  201. phydev = <5>;
  202. };
  203. combophy5: combo-phy@fff5d000 {
  204. compatible = "calxeda,hb-combophy";
  205. #phy-cells = <1>;
  206. reg = <0xfff5d000 0x1000>;
  207. phydev = <31>;
  208. };
  209. };
  210. };