dove.dtsi 5.4 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "marvell,dove";
  4. model = "Marvell Armada 88AP510 SoC";
  5. aliases {
  6. gpio0 = &gpio0;
  7. gpio1 = &gpio1;
  8. gpio2 = &gpio2;
  9. };
  10. soc@f1000000 {
  11. compatible = "simple-bus";
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. interrupt-parent = <&intc>;
  15. ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
  16. 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
  17. 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
  18. 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
  19. 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
  20. 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
  21. 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
  22. 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
  23. l2: l2-cache {
  24. compatible = "marvell,tauros2-cache";
  25. marvell,tauros2-cache-features = <0>;
  26. };
  27. intc: interrupt-controller {
  28. compatible = "marvell,orion-intc";
  29. interrupt-controller;
  30. #interrupt-cells = <1>;
  31. reg = <0x20204 0x04>, <0x20214 0x04>;
  32. };
  33. core_clk: core-clocks@d0214 {
  34. compatible = "marvell,dove-core-clock";
  35. reg = <0xd0214 0x4>;
  36. #clock-cells = <1>;
  37. };
  38. gate_clk: clock-gating-control@d0038 {
  39. compatible = "marvell,dove-gating-clock";
  40. reg = <0xd0038 0x4>;
  41. clocks = <&core_clk 0>;
  42. #clock-cells = <1>;
  43. };
  44. thermal: thermal@d001c {
  45. compatible = "marvell,dove-thermal";
  46. reg = <0xd001c 0x0c>, <0xd005c 0x08>;
  47. };
  48. uart0: serial@12000 {
  49. compatible = "ns16550a";
  50. reg = <0x12000 0x100>;
  51. reg-shift = <2>;
  52. interrupts = <7>;
  53. clocks = <&core_clk 0>;
  54. status = "disabled";
  55. };
  56. uart1: serial@12100 {
  57. compatible = "ns16550a";
  58. reg = <0x12100 0x100>;
  59. reg-shift = <2>;
  60. interrupts = <8>;
  61. clocks = <&core_clk 0>;
  62. status = "disabled";
  63. };
  64. uart2: serial@12200 {
  65. compatible = "ns16550a";
  66. reg = <0x12000 0x100>;
  67. reg-shift = <2>;
  68. interrupts = <9>;
  69. clocks = <&core_clk 0>;
  70. status = "disabled";
  71. };
  72. uart3: serial@12300 {
  73. compatible = "ns16550a";
  74. reg = <0x12100 0x100>;
  75. reg-shift = <2>;
  76. interrupts = <10>;
  77. clocks = <&core_clk 0>;
  78. status = "disabled";
  79. };
  80. gpio0: gpio@d0400 {
  81. compatible = "marvell,orion-gpio";
  82. #gpio-cells = <2>;
  83. gpio-controller;
  84. reg = <0xd0400 0x20>;
  85. ngpios = <32>;
  86. interrupt-controller;
  87. #interrupt-cells = <2>;
  88. interrupts = <12>, <13>, <14>, <60>;
  89. };
  90. gpio1: gpio@d0420 {
  91. compatible = "marvell,orion-gpio";
  92. #gpio-cells = <2>;
  93. gpio-controller;
  94. reg = <0xd0420 0x20>;
  95. ngpios = <32>;
  96. interrupt-controller;
  97. #interrupt-cells = <2>;
  98. interrupts = <61>;
  99. };
  100. gpio2: gpio@e8400 {
  101. compatible = "marvell,orion-gpio";
  102. #gpio-cells = <2>;
  103. gpio-controller;
  104. reg = <0xe8400 0x0c>;
  105. ngpios = <8>;
  106. };
  107. pinctrl: pinctrl@d0200 {
  108. compatible = "marvell,dove-pinctrl";
  109. reg = <0xd0200 0x10>;
  110. clocks = <&gate_clk 22>;
  111. };
  112. spi0: spi@10600 {
  113. compatible = "marvell,orion-spi";
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. cell-index = <0>;
  117. interrupts = <6>;
  118. reg = <0x10600 0x28>;
  119. clocks = <&core_clk 0>;
  120. status = "disabled";
  121. };
  122. spi1: spi@14600 {
  123. compatible = "marvell,orion-spi";
  124. #address-cells = <1>;
  125. #size-cells = <0>;
  126. cell-index = <1>;
  127. interrupts = <5>;
  128. reg = <0x14600 0x28>;
  129. clocks = <&core_clk 0>;
  130. status = "disabled";
  131. };
  132. i2c0: i2c@11000 {
  133. compatible = "marvell,mv64xxx-i2c";
  134. reg = <0x11000 0x20>;
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. interrupts = <11>;
  138. clock-frequency = <400000>;
  139. timeout-ms = <1000>;
  140. clocks = <&core_clk 0>;
  141. status = "disabled";
  142. };
  143. ehci0: usb-host@50000 {
  144. compatible = "marvell,orion-ehci";
  145. reg = <0x50000 0x1000>;
  146. interrupts = <24>;
  147. clocks = <&gate_clk 0>;
  148. status = "okay";
  149. };
  150. ehci1: usb-host@51000 {
  151. compatible = "marvell,orion-ehci";
  152. reg = <0x51000 0x1000>;
  153. interrupts = <25>;
  154. clocks = <&gate_clk 1>;
  155. status = "okay";
  156. };
  157. sdio0: sdio@92000 {
  158. compatible = "marvell,dove-sdhci";
  159. reg = <0x92000 0x100>;
  160. interrupts = <35>, <37>;
  161. clocks = <&gate_clk 8>;
  162. status = "disabled";
  163. };
  164. sdio1: sdio@90000 {
  165. compatible = "marvell,dove-sdhci";
  166. reg = <0x90000 0x100>;
  167. interrupts = <36>, <38>;
  168. clocks = <&gate_clk 9>;
  169. status = "disabled";
  170. };
  171. sata0: sata@a0000 {
  172. compatible = "marvell,orion-sata";
  173. reg = <0xa0000 0x2400>;
  174. interrupts = <62>;
  175. clocks = <&gate_clk 3>;
  176. nr-ports = <1>;
  177. status = "disabled";
  178. };
  179. rtc@d8500 {
  180. compatible = "marvell,orion-rtc";
  181. reg = <0xd8500 0x20>;
  182. };
  183. crypto: crypto@30000 {
  184. compatible = "marvell,orion-crypto";
  185. reg = <0x30000 0x10000>,
  186. <0xc8000000 0x800>;
  187. reg-names = "regs", "sram";
  188. interrupts = <31>;
  189. clocks = <&gate_clk 15>;
  190. status = "okay";
  191. };
  192. xor0: dma-engine@60800 {
  193. compatible = "marvell,orion-xor";
  194. reg = <0x60800 0x100
  195. 0x60a00 0x100>;
  196. clocks = <&gate_clk 23>;
  197. status = "okay";
  198. channel0 {
  199. interrupts = <39>;
  200. dmacap,memcpy;
  201. dmacap,xor;
  202. };
  203. channel1 {
  204. interrupts = <40>;
  205. dmacap,memset;
  206. dmacap,memcpy;
  207. dmacap,xor;
  208. };
  209. };
  210. xor1: dma-engine@60900 {
  211. compatible = "marvell,orion-xor";
  212. reg = <0x60900 0x100
  213. 0x60b00 0x100>;
  214. clocks = <&gate_clk 24>;
  215. status = "okay";
  216. channel0 {
  217. interrupts = <42>;
  218. dmacap,memcpy;
  219. dmacap,xor;
  220. };
  221. channel1 {
  222. interrupts = <43>;
  223. dmacap,memset;
  224. dmacap,memcpy;
  225. dmacap,xor;
  226. };
  227. };
  228. };
  229. };