at91sam9g45.dtsi 21 KB

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  1. /*
  2. * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
  3. * applies to AT91SAM9G45, AT91SAM9M10,
  4. * AT91SAM9G46, AT91SAM9M11 SoC
  5. *
  6. * Copyright (C) 2011 Atmel,
  7. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. #include "skeleton.dtsi"
  12. #include <dt-bindings/dma/at91.h>
  13. #include <dt-bindings/pinctrl/at91.h>
  14. #include <dt-bindings/interrupt-controller/irq.h>
  15. #include <dt-bindings/gpio/gpio.h>
  16. / {
  17. model = "Atmel AT91SAM9G45 family SoC";
  18. compatible = "atmel,at91sam9g45";
  19. interrupt-parent = <&aic>;
  20. aliases {
  21. serial0 = &dbgu;
  22. serial1 = &usart0;
  23. serial2 = &usart1;
  24. serial3 = &usart2;
  25. serial4 = &usart3;
  26. gpio0 = &pioA;
  27. gpio1 = &pioB;
  28. gpio2 = &pioC;
  29. gpio3 = &pioD;
  30. gpio4 = &pioE;
  31. tcb0 = &tcb0;
  32. tcb1 = &tcb1;
  33. i2c0 = &i2c0;
  34. i2c1 = &i2c1;
  35. ssc0 = &ssc0;
  36. ssc1 = &ssc1;
  37. };
  38. cpus {
  39. #address-cells = <0>;
  40. #size-cells = <0>;
  41. cpu {
  42. compatible = "arm,arm926ej-s";
  43. device_type = "cpu";
  44. };
  45. };
  46. memory {
  47. reg = <0x70000000 0x10000000>;
  48. };
  49. ahb {
  50. compatible = "simple-bus";
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. apb {
  55. compatible = "simple-bus";
  56. #address-cells = <1>;
  57. #size-cells = <1>;
  58. ranges;
  59. aic: interrupt-controller@fffff000 {
  60. #interrupt-cells = <3>;
  61. compatible = "atmel,at91rm9200-aic";
  62. interrupt-controller;
  63. reg = <0xfffff000 0x200>;
  64. atmel,external-irqs = <31>;
  65. };
  66. ramc0: ramc@ffffe400 {
  67. compatible = "atmel,at91sam9g45-ddramc";
  68. reg = <0xffffe400 0x200
  69. 0xffffe600 0x200>;
  70. };
  71. pmc: pmc@fffffc00 {
  72. compatible = "atmel,at91rm9200-pmc";
  73. reg = <0xfffffc00 0x100>;
  74. };
  75. rstc@fffffd00 {
  76. compatible = "atmel,at91sam9g45-rstc";
  77. reg = <0xfffffd00 0x10>;
  78. };
  79. pit: timer@fffffd30 {
  80. compatible = "atmel,at91sam9260-pit";
  81. reg = <0xfffffd30 0xf>;
  82. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  83. };
  84. shdwc@fffffd10 {
  85. compatible = "atmel,at91sam9rl-shdwc";
  86. reg = <0xfffffd10 0x10>;
  87. };
  88. tcb0: timer@fff7c000 {
  89. compatible = "atmel,at91rm9200-tcb";
  90. reg = <0xfff7c000 0x100>;
  91. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
  92. };
  93. tcb1: timer@fffd4000 {
  94. compatible = "atmel,at91rm9200-tcb";
  95. reg = <0xfffd4000 0x100>;
  96. interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
  97. };
  98. dma: dma-controller@ffffec00 {
  99. compatible = "atmel,at91sam9g45-dma";
  100. reg = <0xffffec00 0x200>;
  101. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
  102. #dma-cells = <2>;
  103. };
  104. pinctrl@fffff200 {
  105. #address-cells = <1>;
  106. #size-cells = <1>;
  107. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  108. ranges = <0xfffff200 0xfffff200 0xa00>;
  109. atmel,mux-mask = <
  110. /* A B */
  111. 0xffffffff 0xffc003ff /* pioA */
  112. 0xffffffff 0x800f8f00 /* pioB */
  113. 0xffffffff 0x00000e00 /* pioC */
  114. 0xffffffff 0xff0c1381 /* pioD */
  115. 0xffffffff 0x81ffff81 /* pioE */
  116. >;
  117. /* shared pinctrl settings */
  118. dbgu {
  119. pinctrl_dbgu: dbgu-0 {
  120. atmel,pins =
  121. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
  122. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
  123. };
  124. };
  125. usart0 {
  126. pinctrl_usart0: usart0-0 {
  127. atmel,pins =
  128. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
  129. AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  130. };
  131. pinctrl_usart0_rts: usart0_rts-0 {
  132. atmel,pins =
  133. <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
  134. };
  135. pinctrl_usart0_cts: usart0_cts-0 {
  136. atmel,pins =
  137. <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
  138. };
  139. };
  140. uart1 {
  141. pinctrl_usart1: usart1-0 {
  142. atmel,pins =
  143. <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
  144. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  145. };
  146. pinctrl_usart1_rts: usart1_rts-0 {
  147. atmel,pins =
  148. <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
  149. };
  150. pinctrl_usart1_cts: usart1_cts-0 {
  151. atmel,pins =
  152. <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
  153. };
  154. };
  155. usart2 {
  156. pinctrl_usart2: usart2-0 {
  157. atmel,pins =
  158. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
  159. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
  160. };
  161. pinctrl_usart2_rts: usart2_rts-0 {
  162. atmel,pins =
  163. <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
  164. };
  165. pinctrl_usart2_cts: usart2_cts-0 {
  166. atmel,pins =
  167. <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
  168. };
  169. };
  170. usart3 {
  171. pinctrl_usart3: usart3-0 {
  172. atmel,pins =
  173. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
  174. AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  175. };
  176. pinctrl_usart3_rts: usart3_rts-0 {
  177. atmel,pins =
  178. <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
  179. };
  180. pinctrl_usart3_cts: usart3_cts-0 {
  181. atmel,pins =
  182. <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
  183. };
  184. };
  185. nand {
  186. pinctrl_nand: nand-0 {
  187. atmel,pins =
  188. <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
  189. AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
  190. };
  191. };
  192. macb {
  193. pinctrl_macb_rmii: macb_rmii-0 {
  194. atmel,pins =
  195. <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
  196. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
  197. AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  198. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  199. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  200. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  201. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
  202. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  203. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
  204. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
  205. };
  206. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  207. atmel,pins =
  208. <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
  209. AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
  210. AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
  211. AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
  212. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  213. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  214. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
  215. AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  216. };
  217. };
  218. mmc0 {
  219. pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
  220. atmel,pins =
  221. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
  222. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  223. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
  224. };
  225. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  226. atmel,pins =
  227. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
  228. AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
  229. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
  230. };
  231. pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
  232. atmel,pins =
  233. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
  234. AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  235. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
  236. AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
  237. };
  238. };
  239. mmc1 {
  240. pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
  241. atmel,pins =
  242. <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
  243. AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
  244. AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
  245. };
  246. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  247. atmel,pins =
  248. <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
  249. AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
  250. AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
  251. };
  252. pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
  253. atmel,pins =
  254. <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
  255. AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
  256. AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
  257. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
  258. };
  259. };
  260. ssc0 {
  261. pinctrl_ssc0_tx: ssc0_tx-0 {
  262. atmel,pins =
  263. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
  264. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
  265. AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
  266. };
  267. pinctrl_ssc0_rx: ssc0_rx-0 {
  268. atmel,pins =
  269. <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
  270. AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
  271. AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
  272. };
  273. };
  274. ssc1 {
  275. pinctrl_ssc1_tx: ssc1_tx-0 {
  276. atmel,pins =
  277. <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
  278. AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
  279. AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
  280. };
  281. pinctrl_ssc1_rx: ssc1_rx-0 {
  282. atmel,pins =
  283. <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
  284. AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
  285. AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
  286. };
  287. };
  288. spi0 {
  289. pinctrl_spi0: spi0-0 {
  290. atmel,pins =
  291. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
  292. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
  293. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
  294. };
  295. };
  296. spi1 {
  297. pinctrl_spi1: spi1-0 {
  298. atmel,pins =
  299. <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
  300. AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
  301. AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
  302. };
  303. };
  304. tcb0 {
  305. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  306. atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  307. };
  308. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  309. atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  310. };
  311. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  312. atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  313. };
  314. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  315. atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  316. };
  317. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  318. atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  319. };
  320. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  321. atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  322. };
  323. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  324. atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  325. };
  326. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  327. atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  328. };
  329. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  330. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  331. };
  332. };
  333. tcb1 {
  334. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  335. atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  336. };
  337. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  338. atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  339. };
  340. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  341. atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  342. };
  343. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  344. atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  345. };
  346. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  347. atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  348. };
  349. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  350. atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  351. };
  352. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  353. atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  354. };
  355. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  356. atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  357. };
  358. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  359. atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  360. };
  361. };
  362. pioA: gpio@fffff200 {
  363. compatible = "atmel,at91rm9200-gpio";
  364. reg = <0xfffff200 0x200>;
  365. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  366. #gpio-cells = <2>;
  367. gpio-controller;
  368. interrupt-controller;
  369. #interrupt-cells = <2>;
  370. };
  371. pioB: gpio@fffff400 {
  372. compatible = "atmel,at91rm9200-gpio";
  373. reg = <0xfffff400 0x200>;
  374. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  375. #gpio-cells = <2>;
  376. gpio-controller;
  377. interrupt-controller;
  378. #interrupt-cells = <2>;
  379. };
  380. pioC: gpio@fffff600 {
  381. compatible = "atmel,at91rm9200-gpio";
  382. reg = <0xfffff600 0x200>;
  383. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  384. #gpio-cells = <2>;
  385. gpio-controller;
  386. interrupt-controller;
  387. #interrupt-cells = <2>;
  388. };
  389. pioD: gpio@fffff800 {
  390. compatible = "atmel,at91rm9200-gpio";
  391. reg = <0xfffff800 0x200>;
  392. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  393. #gpio-cells = <2>;
  394. gpio-controller;
  395. interrupt-controller;
  396. #interrupt-cells = <2>;
  397. };
  398. pioE: gpio@fffffa00 {
  399. compatible = "atmel,at91rm9200-gpio";
  400. reg = <0xfffffa00 0x200>;
  401. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
  402. #gpio-cells = <2>;
  403. gpio-controller;
  404. interrupt-controller;
  405. #interrupt-cells = <2>;
  406. };
  407. };
  408. dbgu: serial@ffffee00 {
  409. compatible = "atmel,at91sam9260-usart";
  410. reg = <0xffffee00 0x200>;
  411. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  412. pinctrl-names = "default";
  413. pinctrl-0 = <&pinctrl_dbgu>;
  414. status = "disabled";
  415. };
  416. usart0: serial@fff8c000 {
  417. compatible = "atmel,at91sam9260-usart";
  418. reg = <0xfff8c000 0x200>;
  419. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  420. atmel,use-dma-rx;
  421. atmel,use-dma-tx;
  422. pinctrl-names = "default";
  423. pinctrl-0 = <&pinctrl_usart0>;
  424. status = "disabled";
  425. };
  426. usart1: serial@fff90000 {
  427. compatible = "atmel,at91sam9260-usart";
  428. reg = <0xfff90000 0x200>;
  429. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  430. atmel,use-dma-rx;
  431. atmel,use-dma-tx;
  432. pinctrl-names = "default";
  433. pinctrl-0 = <&pinctrl_usart1>;
  434. status = "disabled";
  435. };
  436. usart2: serial@fff94000 {
  437. compatible = "atmel,at91sam9260-usart";
  438. reg = <0xfff94000 0x200>;
  439. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
  440. atmel,use-dma-rx;
  441. atmel,use-dma-tx;
  442. pinctrl-names = "default";
  443. pinctrl-0 = <&pinctrl_usart2>;
  444. status = "disabled";
  445. };
  446. usart3: serial@fff98000 {
  447. compatible = "atmel,at91sam9260-usart";
  448. reg = <0xfff98000 0x200>;
  449. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
  450. atmel,use-dma-rx;
  451. atmel,use-dma-tx;
  452. pinctrl-names = "default";
  453. pinctrl-0 = <&pinctrl_usart3>;
  454. status = "disabled";
  455. };
  456. macb0: ethernet@fffbc000 {
  457. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  458. reg = <0xfffbc000 0x100>;
  459. interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
  460. pinctrl-names = "default";
  461. pinctrl-0 = <&pinctrl_macb_rmii>;
  462. status = "disabled";
  463. };
  464. i2c0: i2c@fff84000 {
  465. compatible = "atmel,at91sam9g10-i2c";
  466. reg = <0xfff84000 0x100>;
  467. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
  468. #address-cells = <1>;
  469. #size-cells = <0>;
  470. status = "disabled";
  471. };
  472. i2c1: i2c@fff88000 {
  473. compatible = "atmel,at91sam9g10-i2c";
  474. reg = <0xfff88000 0x100>;
  475. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
  476. #address-cells = <1>;
  477. #size-cells = <0>;
  478. status = "disabled";
  479. };
  480. ssc0: ssc@fff9c000 {
  481. compatible = "atmel,at91sam9g45-ssc";
  482. reg = <0xfff9c000 0x4000>;
  483. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  484. pinctrl-names = "default";
  485. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  486. status = "disabled";
  487. };
  488. ssc1: ssc@fffa0000 {
  489. compatible = "atmel,at91sam9g45-ssc";
  490. reg = <0xfffa0000 0x4000>;
  491. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
  492. pinctrl-names = "default";
  493. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  494. status = "disabled";
  495. };
  496. adc0: adc@fffb0000 {
  497. compatible = "atmel,at91sam9260-adc";
  498. reg = <0xfffb0000 0x100>;
  499. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
  500. atmel,adc-use-external-triggers;
  501. atmel,adc-channels-used = <0xff>;
  502. atmel,adc-vref = <3300>;
  503. atmel,adc-num-channels = <8>;
  504. atmel,adc-startup-time = <40>;
  505. atmel,adc-channel-base = <0x30>;
  506. atmel,adc-drdy-mask = <0x10000>;
  507. atmel,adc-status-register = <0x1c>;
  508. atmel,adc-trigger-register = <0x08>;
  509. atmel,adc-res = <8 10>;
  510. atmel,adc-res-names = "lowres", "highres";
  511. atmel,adc-use-res = "highres";
  512. trigger@0 {
  513. trigger-name = "external-rising";
  514. trigger-value = <0x1>;
  515. trigger-external;
  516. };
  517. trigger@1 {
  518. trigger-name = "external-falling";
  519. trigger-value = <0x2>;
  520. trigger-external;
  521. };
  522. trigger@2 {
  523. trigger-name = "external-any";
  524. trigger-value = <0x3>;
  525. trigger-external;
  526. };
  527. trigger@3 {
  528. trigger-name = "continuous";
  529. trigger-value = <0x6>;
  530. };
  531. };
  532. mmc0: mmc@fff80000 {
  533. compatible = "atmel,hsmci";
  534. reg = <0xfff80000 0x600>;
  535. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
  536. dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
  537. dma-names = "rxtx";
  538. #address-cells = <1>;
  539. #size-cells = <0>;
  540. status = "disabled";
  541. };
  542. mmc1: mmc@fffd0000 {
  543. compatible = "atmel,hsmci";
  544. reg = <0xfffd0000 0x600>;
  545. interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
  546. dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
  547. dma-names = "rxtx";
  548. #address-cells = <1>;
  549. #size-cells = <0>;
  550. status = "disabled";
  551. };
  552. watchdog@fffffd40 {
  553. compatible = "atmel,at91sam9260-wdt";
  554. reg = <0xfffffd40 0x10>;
  555. status = "disabled";
  556. };
  557. spi0: spi@fffa4000 {
  558. #address-cells = <1>;
  559. #size-cells = <0>;
  560. compatible = "atmel,at91rm9200-spi";
  561. reg = <0xfffa4000 0x200>;
  562. interrupts = <14 4 3>;
  563. pinctrl-names = "default";
  564. pinctrl-0 = <&pinctrl_spi0>;
  565. status = "disabled";
  566. };
  567. spi1: spi@fffa8000 {
  568. #address-cells = <1>;
  569. #size-cells = <0>;
  570. compatible = "atmel,at91rm9200-spi";
  571. reg = <0xfffa8000 0x200>;
  572. interrupts = <15 4 3>;
  573. pinctrl-names = "default";
  574. pinctrl-0 = <&pinctrl_spi1>;
  575. status = "disabled";
  576. };
  577. usb2: gadget@fff78000 {
  578. #address-cells = <1>;
  579. #size-cells = <0>;
  580. compatible = "atmel,at91sam9rl-udc";
  581. reg = <0x00600000 0x80000
  582. 0xfff78000 0x400>;
  583. interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
  584. status = "disabled";
  585. ep0 {
  586. reg = <0>;
  587. atmel,fifo-size = <64>;
  588. atmel,nb-banks = <1>;
  589. };
  590. ep1 {
  591. reg = <1>;
  592. atmel,fifo-size = <1024>;
  593. atmel,nb-banks = <2>;
  594. atmel,can-dma;
  595. atmel,can-isoc;
  596. };
  597. ep2 {
  598. reg = <2>;
  599. atmel,fifo-size = <1024>;
  600. atmel,nb-banks = <2>;
  601. atmel,can-dma;
  602. atmel,can-isoc;
  603. };
  604. ep3 {
  605. reg = <3>;
  606. atmel,fifo-size = <1024>;
  607. atmel,nb-banks = <3>;
  608. atmel,can-dma;
  609. };
  610. ep4 {
  611. reg = <4>;
  612. atmel,fifo-size = <1024>;
  613. atmel,nb-banks = <3>;
  614. atmel,can-dma;
  615. };
  616. ep5 {
  617. reg = <5>;
  618. atmel,fifo-size = <1024>;
  619. atmel,nb-banks = <3>;
  620. atmel,can-dma;
  621. atmel,can-isoc;
  622. };
  623. ep6 {
  624. reg = <6>;
  625. atmel,fifo-size = <1024>;
  626. atmel,nb-banks = <3>;
  627. atmel,can-dma;
  628. atmel,can-isoc;
  629. };
  630. };
  631. };
  632. nand0: nand@40000000 {
  633. compatible = "atmel,at91rm9200-nand";
  634. #address-cells = <1>;
  635. #size-cells = <1>;
  636. reg = <0x40000000 0x10000000
  637. 0xffffe200 0x200
  638. >;
  639. atmel,nand-addr-offset = <21>;
  640. atmel,nand-cmd-offset = <22>;
  641. pinctrl-names = "default";
  642. pinctrl-0 = <&pinctrl_nand>;
  643. gpios = <&pioC 8 GPIO_ACTIVE_HIGH
  644. &pioC 14 GPIO_ACTIVE_HIGH
  645. 0
  646. >;
  647. status = "disabled";
  648. };
  649. usb0: ohci@00700000 {
  650. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  651. reg = <0x00700000 0x100000>;
  652. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  653. status = "disabled";
  654. };
  655. usb1: ehci@00800000 {
  656. compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
  657. reg = <0x00800000 0x100000>;
  658. interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
  659. status = "disabled";
  660. };
  661. };
  662. i2c@0 {
  663. compatible = "i2c-gpio";
  664. gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
  665. &pioA 21 GPIO_ACTIVE_HIGH /* scl */
  666. >;
  667. i2c-gpio,sda-open-drain;
  668. i2c-gpio,scl-open-drain;
  669. i2c-gpio,delay-us = <5>; /* ~100 kHz */
  670. #address-cells = <1>;
  671. #size-cells = <0>;
  672. status = "disabled";
  673. };
  674. };