at91sam9263.dtsi 17 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. #include "skeleton.dtsi"
  9. #include <dt-bindings/pinctrl/at91.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include <dt-bindings/gpio/gpio.h>
  12. / {
  13. model = "Atmel AT91SAM9263 family SoC";
  14. compatible = "atmel,at91sam9263";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. gpio4 = &pioE;
  26. tcb0 = &tcb0;
  27. i2c0 = &i2c0;
  28. ssc0 = &ssc0;
  29. ssc1 = &ssc1;
  30. };
  31. cpus {
  32. #address-cells = <0>;
  33. #size-cells = <0>;
  34. cpu {
  35. compatible = "arm,arm926ej-s";
  36. device_type = "cpu";
  37. };
  38. };
  39. memory {
  40. reg = <0x20000000 0x08000000>;
  41. };
  42. ahb {
  43. compatible = "simple-bus";
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. ranges;
  47. apb {
  48. compatible = "simple-bus";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. aic: interrupt-controller@fffff000 {
  53. #interrupt-cells = <3>;
  54. compatible = "atmel,at91rm9200-aic";
  55. interrupt-controller;
  56. reg = <0xfffff000 0x200>;
  57. atmel,external-irqs = <30 31>;
  58. };
  59. pmc: pmc@fffffc00 {
  60. compatible = "atmel,at91rm9200-pmc";
  61. reg = <0xfffffc00 0x100>;
  62. };
  63. ramc: ramc@ffffe200 {
  64. compatible = "atmel,at91sam9260-sdramc";
  65. reg = <0xffffe200 0x200
  66. 0xffffe800 0x200>;
  67. };
  68. pit: timer@fffffd30 {
  69. compatible = "atmel,at91sam9260-pit";
  70. reg = <0xfffffd30 0xf>;
  71. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  72. };
  73. tcb0: timer@fff7c000 {
  74. compatible = "atmel,at91rm9200-tcb";
  75. reg = <0xfff7c000 0x100>;
  76. interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
  77. };
  78. rstc@fffffd00 {
  79. compatible = "atmel,at91sam9260-rstc";
  80. reg = <0xfffffd00 0x10>;
  81. };
  82. shdwc@fffffd10 {
  83. compatible = "atmel,at91sam9260-shdwc";
  84. reg = <0xfffffd10 0x10>;
  85. };
  86. pinctrl@fffff200 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  90. ranges = <0xfffff200 0xfffff200 0xa00>;
  91. atmel,mux-mask = <
  92. /* A B */
  93. 0xfffffffb 0xffffe07f /* pioA */
  94. 0x0007ffff 0x39072fff /* pioB */
  95. 0xffffffff 0x3ffffff8 /* pioC */
  96. 0xfffffbff 0xffffffff /* pioD */
  97. 0xffe00fff 0xfbfcff00 /* pioE */
  98. >;
  99. /* shared pinctrl settings */
  100. dbgu {
  101. pinctrl_dbgu: dbgu-0 {
  102. atmel,pins =
  103. <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
  104. AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
  105. };
  106. };
  107. usart0 {
  108. pinctrl_usart0: usart0-0 {
  109. atmel,pins =
  110. <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */
  111. AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
  112. };
  113. pinctrl_usart0_rts: usart0_rts-0 {
  114. atmel,pins =
  115. <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
  116. };
  117. pinctrl_usart0_cts: usart0_cts-0 {
  118. atmel,pins =
  119. <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
  120. };
  121. };
  122. usart1 {
  123. pinctrl_usart1: usart1-0 {
  124. atmel,pins =
  125. <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
  126. AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */
  127. };
  128. pinctrl_usart1_rts: usart1_rts-0 {
  129. atmel,pins =
  130. <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */
  131. };
  132. pinctrl_usart1_cts: usart1_cts-0 {
  133. atmel,pins =
  134. <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */
  135. };
  136. };
  137. usart2 {
  138. pinctrl_usart2: usart2-0 {
  139. atmel,pins =
  140. <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
  141. AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */
  142. };
  143. pinctrl_usart2_rts: usart2_rts-0 {
  144. atmel,pins =
  145. <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */
  146. };
  147. pinctrl_usart2_cts: usart2_cts-0 {
  148. atmel,pins =
  149. <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */
  150. };
  151. };
  152. nand {
  153. pinctrl_nand: nand-0 {
  154. atmel,pins =
  155. <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/
  156. AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */
  157. };
  158. };
  159. macb {
  160. pinctrl_macb_rmii: macb_rmii-0 {
  161. atmel,pins =
  162. <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
  163. AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
  164. AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
  165. AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
  166. AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
  167. AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
  168. AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
  169. AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
  170. AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
  171. AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
  172. };
  173. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  174. atmel,pins =
  175. <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
  176. AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
  177. AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */
  178. AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */
  179. AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */
  180. AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
  181. AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
  182. AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
  183. };
  184. };
  185. mmc0 {
  186. pinctrl_mmc0_clk: mmc0_clk-0 {
  187. atmel,pins =
  188. <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
  189. };
  190. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  191. atmel,pins =
  192. <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
  193. AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
  194. };
  195. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  196. atmel,pins =
  197. <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
  198. AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
  199. AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
  200. };
  201. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  202. atmel,pins =
  203. <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
  204. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */
  205. };
  206. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  207. atmel,pins =
  208. <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
  209. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
  210. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
  211. };
  212. };
  213. mmc1 {
  214. pinctrl_mmc1_clk: mmc1_clk-0 {
  215. atmel,pins =
  216. <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
  217. };
  218. pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
  219. atmel,pins =
  220. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  221. AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */
  222. };
  223. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  224. atmel,pins =
  225. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
  226. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
  227. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
  228. };
  229. pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
  230. atmel,pins =
  231. <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */
  232. AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */
  233. };
  234. pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
  235. atmel,pins =
  236. <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */
  237. AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
  238. AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */
  239. };
  240. };
  241. ssc0 {
  242. pinctrl_ssc0_tx: ssc0_tx-0 {
  243. atmel,pins =
  244. <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
  245. AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */
  246. AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
  247. };
  248. pinctrl_ssc0_rx: ssc0_rx-0 {
  249. atmel,pins =
  250. <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */
  251. AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */
  252. AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */
  253. };
  254. };
  255. ssc1 {
  256. pinctrl_ssc1_tx: ssc1_tx-0 {
  257. atmel,pins =
  258. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
  259. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
  260. AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
  261. };
  262. pinctrl_ssc1_rx: ssc1_rx-0 {
  263. atmel,pins =
  264. <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
  265. AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
  266. AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
  267. };
  268. };
  269. spi0 {
  270. pinctrl_spi0: spi0-0 {
  271. atmel,pins =
  272. <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
  273. AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */
  274. AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */
  275. };
  276. };
  277. spi1 {
  278. pinctrl_spi1: spi1-0 {
  279. atmel,pins =
  280. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */
  281. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */
  282. AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
  283. };
  284. };
  285. tcb0 {
  286. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  287. atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  288. };
  289. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  290. atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  291. };
  292. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  293. atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  294. };
  295. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  296. atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  297. };
  298. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  299. atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  300. };
  301. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  302. atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  303. };
  304. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  305. atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  306. };
  307. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  308. atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  309. };
  310. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  311. atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  312. };
  313. };
  314. pioA: gpio@fffff200 {
  315. compatible = "atmel,at91rm9200-gpio";
  316. reg = <0xfffff200 0x200>;
  317. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  318. #gpio-cells = <2>;
  319. gpio-controller;
  320. interrupt-controller;
  321. #interrupt-cells = <2>;
  322. };
  323. pioB: gpio@fffff400 {
  324. compatible = "atmel,at91rm9200-gpio";
  325. reg = <0xfffff400 0x200>;
  326. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  327. #gpio-cells = <2>;
  328. gpio-controller;
  329. interrupt-controller;
  330. #interrupt-cells = <2>;
  331. };
  332. pioC: gpio@fffff600 {
  333. compatible = "atmel,at91rm9200-gpio";
  334. reg = <0xfffff600 0x200>;
  335. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  336. #gpio-cells = <2>;
  337. gpio-controller;
  338. interrupt-controller;
  339. #interrupt-cells = <2>;
  340. };
  341. pioD: gpio@fffff800 {
  342. compatible = "atmel,at91rm9200-gpio";
  343. reg = <0xfffff800 0x200>;
  344. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  345. #gpio-cells = <2>;
  346. gpio-controller;
  347. interrupt-controller;
  348. #interrupt-cells = <2>;
  349. };
  350. pioE: gpio@fffffa00 {
  351. compatible = "atmel,at91rm9200-gpio";
  352. reg = <0xfffffa00 0x200>;
  353. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  354. #gpio-cells = <2>;
  355. gpio-controller;
  356. interrupt-controller;
  357. #interrupt-cells = <2>;
  358. };
  359. };
  360. dbgu: serial@ffffee00 {
  361. compatible = "atmel,at91sam9260-usart";
  362. reg = <0xffffee00 0x200>;
  363. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  364. pinctrl-names = "default";
  365. pinctrl-0 = <&pinctrl_dbgu>;
  366. status = "disabled";
  367. };
  368. usart0: serial@fff8c000 {
  369. compatible = "atmel,at91sam9260-usart";
  370. reg = <0xfff8c000 0x200>;
  371. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  372. atmel,use-dma-rx;
  373. atmel,use-dma-tx;
  374. pinctrl-names = "default";
  375. pinctrl-0 = <&pinctrl_usart0>;
  376. status = "disabled";
  377. };
  378. usart1: serial@fff90000 {
  379. compatible = "atmel,at91sam9260-usart";
  380. reg = <0xfff90000 0x200>;
  381. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  382. atmel,use-dma-rx;
  383. atmel,use-dma-tx;
  384. pinctrl-names = "default";
  385. pinctrl-0 = <&pinctrl_usart1>;
  386. status = "disabled";
  387. };
  388. usart2: serial@fff94000 {
  389. compatible = "atmel,at91sam9260-usart";
  390. reg = <0xfff94000 0x200>;
  391. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
  392. atmel,use-dma-rx;
  393. atmel,use-dma-tx;
  394. pinctrl-names = "default";
  395. pinctrl-0 = <&pinctrl_usart2>;
  396. status = "disabled";
  397. };
  398. ssc0: ssc@fff98000 {
  399. compatible = "atmel,at91rm9200-ssc";
  400. reg = <0xfff98000 0x4000>;
  401. interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
  402. pinctrl-names = "default";
  403. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  404. status = "disabled";
  405. };
  406. ssc1: ssc@fff9c000 {
  407. compatible = "atmel,at91rm9200-ssc";
  408. reg = <0xfff9c000 0x4000>;
  409. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
  410. pinctrl-names = "default";
  411. pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
  412. status = "disabled";
  413. };
  414. macb0: ethernet@fffbc000 {
  415. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  416. reg = <0xfffbc000 0x100>;
  417. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
  418. pinctrl-names = "default";
  419. pinctrl-0 = <&pinctrl_macb_rmii>;
  420. status = "disabled";
  421. };
  422. usb1: gadget@fff78000 {
  423. compatible = "atmel,at91rm9200-udc";
  424. reg = <0xfff78000 0x4000>;
  425. interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
  426. status = "disabled";
  427. };
  428. i2c0: i2c@fff88000 {
  429. compatible = "atmel,at91sam9263-i2c";
  430. reg = <0xfff88000 0x100>;
  431. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
  432. #address-cells = <1>;
  433. #size-cells = <0>;
  434. status = "disabled";
  435. };
  436. mmc0: mmc@fff80000 {
  437. compatible = "atmel,hsmci";
  438. reg = <0xfff80000 0x600>;
  439. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
  440. #address-cells = <1>;
  441. #size-cells = <0>;
  442. status = "disabled";
  443. };
  444. mmc1: mmc@fff84000 {
  445. compatible = "atmel,hsmci";
  446. reg = <0xfff84000 0x600>;
  447. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
  448. #address-cells = <1>;
  449. #size-cells = <0>;
  450. status = "disabled";
  451. };
  452. watchdog@fffffd40 {
  453. compatible = "atmel,at91sam9260-wdt";
  454. reg = <0xfffffd40 0x10>;
  455. status = "disabled";
  456. };
  457. spi0: spi@fffa4000 {
  458. #address-cells = <1>;
  459. #size-cells = <0>;
  460. compatible = "atmel,at91rm9200-spi";
  461. reg = <0xfffa4000 0x200>;
  462. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
  463. pinctrl-names = "default";
  464. pinctrl-0 = <&pinctrl_spi0>;
  465. status = "disabled";
  466. };
  467. spi1: spi@fffa8000 {
  468. #address-cells = <1>;
  469. #size-cells = <0>;
  470. compatible = "atmel,at91rm9200-spi";
  471. reg = <0xfffa8000 0x200>;
  472. interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
  473. pinctrl-names = "default";
  474. pinctrl-0 = <&pinctrl_spi1>;
  475. status = "disabled";
  476. };
  477. };
  478. nand0: nand@40000000 {
  479. compatible = "atmel,at91rm9200-nand";
  480. #address-cells = <1>;
  481. #size-cells = <1>;
  482. reg = <0x40000000 0x10000000
  483. 0xffffe000 0x200
  484. >;
  485. atmel,nand-addr-offset = <21>;
  486. atmel,nand-cmd-offset = <22>;
  487. pinctrl-names = "default";
  488. pinctrl-0 = <&pinctrl_nand>;
  489. gpios = <&pioA 22 GPIO_ACTIVE_HIGH
  490. &pioD 15 GPIO_ACTIVE_HIGH
  491. 0
  492. >;
  493. status = "disabled";
  494. };
  495. usb0: ohci@00a00000 {
  496. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  497. reg = <0x00a00000 0x100000>;
  498. interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
  499. status = "disabled";
  500. };
  501. };
  502. i2c@0 {
  503. compatible = "i2c-gpio";
  504. gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
  505. &pioB 5 GPIO_ACTIVE_HIGH /* scl */
  506. >;
  507. i2c-gpio,sda-open-drain;
  508. i2c-gpio,scl-open-drain;
  509. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  510. #address-cells = <1>;
  511. #size-cells = <0>;
  512. status = "disabled";
  513. };
  514. };