at91sam9260.dtsi 20 KB

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  1. /*
  2. * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7. *
  8. * Licensed under GPLv2 or later.
  9. */
  10. #include "skeleton.dtsi"
  11. #include <dt-bindings/pinctrl/at91.h>
  12. #include <dt-bindings/interrupt-controller/irq.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. / {
  15. model = "Atmel AT91SAM9260 family SoC";
  16. compatible = "atmel,at91sam9260";
  17. interrupt-parent = <&aic>;
  18. aliases {
  19. serial0 = &dbgu;
  20. serial1 = &usart0;
  21. serial2 = &usart1;
  22. serial3 = &usart2;
  23. serial4 = &usart3;
  24. serial5 = &uart0;
  25. serial6 = &uart1;
  26. gpio0 = &pioA;
  27. gpio1 = &pioB;
  28. gpio2 = &pioC;
  29. tcb0 = &tcb0;
  30. tcb1 = &tcb1;
  31. i2c0 = &i2c0;
  32. ssc0 = &ssc0;
  33. };
  34. cpus {
  35. #address-cells = <0>;
  36. #size-cells = <0>;
  37. cpu {
  38. compatible = "arm,arm926ej-s";
  39. device_type = "cpu";
  40. };
  41. };
  42. memory {
  43. reg = <0x20000000 0x04000000>;
  44. };
  45. ahb {
  46. compatible = "simple-bus";
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. ranges;
  50. apb {
  51. compatible = "simple-bus";
  52. #address-cells = <1>;
  53. #size-cells = <1>;
  54. ranges;
  55. aic: interrupt-controller@fffff000 {
  56. #interrupt-cells = <3>;
  57. compatible = "atmel,at91rm9200-aic";
  58. interrupt-controller;
  59. reg = <0xfffff000 0x200>;
  60. atmel,external-irqs = <29 30 31>;
  61. };
  62. ramc0: ramc@ffffea00 {
  63. compatible = "atmel,at91sam9260-sdramc";
  64. reg = <0xffffea00 0x200>;
  65. };
  66. pmc: pmc@fffffc00 {
  67. compatible = "atmel,at91rm9200-pmc";
  68. reg = <0xfffffc00 0x100>;
  69. };
  70. rstc@fffffd00 {
  71. compatible = "atmel,at91sam9260-rstc";
  72. reg = <0xfffffd00 0x10>;
  73. };
  74. shdwc@fffffd10 {
  75. compatible = "atmel,at91sam9260-shdwc";
  76. reg = <0xfffffd10 0x10>;
  77. };
  78. pit: timer@fffffd30 {
  79. compatible = "atmel,at91sam9260-pit";
  80. reg = <0xfffffd30 0xf>;
  81. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  82. };
  83. tcb0: timer@fffa0000 {
  84. compatible = "atmel,at91rm9200-tcb";
  85. reg = <0xfffa0000 0x100>;
  86. interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
  87. 18 IRQ_TYPE_LEVEL_HIGH 0
  88. 19 IRQ_TYPE_LEVEL_HIGH 0>;
  89. };
  90. tcb1: timer@fffdc000 {
  91. compatible = "atmel,at91rm9200-tcb";
  92. reg = <0xfffdc000 0x100>;
  93. interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
  94. 27 IRQ_TYPE_LEVEL_HIGH 0
  95. 28 IRQ_TYPE_LEVEL_HIGH 0>;
  96. };
  97. pinctrl@fffff400 {
  98. #address-cells = <1>;
  99. #size-cells = <1>;
  100. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  101. ranges = <0xfffff400 0xfffff400 0x600>;
  102. atmel,mux-mask = <
  103. /* A B */
  104. 0xffffffff 0xffc00c3b /* pioA */
  105. 0xffffffff 0x7fff3ccf /* pioB */
  106. 0xffffffff 0x007fffff /* pioC */
  107. >;
  108. /* shared pinctrl settings */
  109. dbgu {
  110. pinctrl_dbgu: dbgu-0 {
  111. atmel,pins =
  112. <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A */
  113. AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB15 periph with pullup */
  114. };
  115. };
  116. usart0 {
  117. pinctrl_usart0: usart0-0 {
  118. atmel,pins =
  119. <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */
  120. AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
  121. };
  122. pinctrl_usart0_rts: usart0_rts-0 {
  123. atmel,pins =
  124. <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
  125. };
  126. pinctrl_usart0_cts: usart0_cts-0 {
  127. atmel,pins =
  128. <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
  129. };
  130. pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
  131. atmel,pins =
  132. <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */
  133. AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
  134. };
  135. pinctrl_usart0_dcd: usart0_dcd-0 {
  136. atmel,pins =
  137. <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
  138. };
  139. pinctrl_usart0_ri: usart0_ri-0 {
  140. atmel,pins =
  141. <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
  142. };
  143. };
  144. usart1 {
  145. pinctrl_usart1: usart1-0 {
  146. atmel,pins =
  147. <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
  148. AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
  149. };
  150. pinctrl_usart1_rts: usart1_rts-0 {
  151. atmel,pins =
  152. <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
  153. };
  154. pinctrl_usart1_cts: usart1_cts-0 {
  155. atmel,pins =
  156. <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
  157. };
  158. };
  159. usart2 {
  160. pinctrl_usart2: usart2-0 {
  161. atmel,pins =
  162. <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
  163. AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB9 periph A */
  164. };
  165. pinctrl_usart2_rts: usart2_rts-0 {
  166. atmel,pins =
  167. <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */
  168. };
  169. pinctrl_usart2_cts: usart2_cts-0 {
  170. atmel,pins =
  171. <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */
  172. };
  173. };
  174. usart3 {
  175. pinctrl_usart3: usart3-0 {
  176. atmel,pins =
  177. <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB10 periph A with pullup */
  178. AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
  179. };
  180. pinctrl_usart3_rts: usart3_rts-0 {
  181. atmel,pins =
  182. <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC8 periph B */
  183. };
  184. pinctrl_usart3_cts: usart3_cts-0 {
  185. atmel,pins =
  186. <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
  187. };
  188. };
  189. uart0 {
  190. pinctrl_uart0: uart0-0 {
  191. atmel,pins =
  192. <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA31 periph B with pullup */
  193. AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
  194. };
  195. };
  196. uart1 {
  197. pinctrl_uart1: uart1-0 {
  198. atmel,pins =
  199. <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB12 periph A with pullup */
  200. AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
  201. };
  202. };
  203. nand {
  204. pinctrl_nand: nand-0 {
  205. atmel,pins =
  206. <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC13 gpio RDY pin pull_up */
  207. AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
  208. };
  209. };
  210. macb {
  211. pinctrl_macb_rmii: macb_rmii-0 {
  212. atmel,pins =
  213. <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
  214. AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
  215. AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
  216. AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
  217. AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
  218. AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
  219. AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
  220. AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */
  221. AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */
  222. AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
  223. };
  224. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  225. atmel,pins =
  226. <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
  227. AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */
  228. AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */
  229. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  230. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
  231. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  232. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  233. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  234. };
  235. pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
  236. atmel,pins =
  237. <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */
  238. AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */
  239. AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */
  240. AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */
  241. AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */
  242. AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
  243. AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
  244. AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
  245. };
  246. };
  247. mmc0 {
  248. pinctrl_mmc0_clk: mmc0_clk-0 {
  249. atmel,pins =
  250. <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */
  251. };
  252. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  253. atmel,pins =
  254. <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
  255. AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */
  256. };
  257. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  258. atmel,pins =
  259. <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
  260. AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
  261. AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
  262. };
  263. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  264. atmel,pins =
  265. <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */
  266. AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */
  267. };
  268. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  269. atmel,pins =
  270. <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
  271. AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */
  272. AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */
  273. };
  274. };
  275. ssc0 {
  276. pinctrl_ssc0_tx: ssc0_tx-0 {
  277. atmel,pins =
  278. <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */
  279. AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */
  280. AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
  281. };
  282. pinctrl_ssc0_rx: ssc0_rx-0 {
  283. atmel,pins =
  284. <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */
  285. AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */
  286. AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
  287. };
  288. };
  289. spi0 {
  290. pinctrl_spi0: spi0-0 {
  291. atmel,pins =
  292. <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */
  293. AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */
  294. AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */
  295. };
  296. };
  297. spi1 {
  298. pinctrl_spi1: spi1-0 {
  299. atmel,pins =
  300. <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */
  301. AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */
  302. AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */
  303. };
  304. };
  305. i2c_gpio0 {
  306. pinctrl_i2c_gpio0: i2c_gpio0-0 {
  307. atmel,pins =
  308. <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
  309. AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
  310. };
  311. };
  312. tcb0 {
  313. pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
  314. atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  315. };
  316. pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
  317. atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  318. };
  319. pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
  320. atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  321. };
  322. pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
  323. atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  324. };
  325. pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
  326. atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  327. };
  328. pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
  329. atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  330. };
  331. pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
  332. atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  333. };
  334. pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
  335. atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  336. };
  337. pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
  338. atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
  339. };
  340. };
  341. tcb1 {
  342. pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
  343. atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  344. };
  345. pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
  346. atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  347. };
  348. pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
  349. atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  350. };
  351. pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
  352. atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  353. };
  354. pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
  355. atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  356. };
  357. pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
  358. atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  359. };
  360. pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
  361. atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  362. };
  363. pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
  364. atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  365. };
  366. pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
  367. atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
  368. };
  369. };
  370. pioA: gpio@fffff400 {
  371. compatible = "atmel,at91rm9200-gpio";
  372. reg = <0xfffff400 0x200>;
  373. interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
  374. #gpio-cells = <2>;
  375. gpio-controller;
  376. interrupt-controller;
  377. #interrupt-cells = <2>;
  378. };
  379. pioB: gpio@fffff600 {
  380. compatible = "atmel,at91rm9200-gpio";
  381. reg = <0xfffff600 0x200>;
  382. interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
  383. #gpio-cells = <2>;
  384. gpio-controller;
  385. interrupt-controller;
  386. #interrupt-cells = <2>;
  387. };
  388. pioC: gpio@fffff800 {
  389. compatible = "atmel,at91rm9200-gpio";
  390. reg = <0xfffff800 0x200>;
  391. interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
  392. #gpio-cells = <2>;
  393. gpio-controller;
  394. interrupt-controller;
  395. #interrupt-cells = <2>;
  396. };
  397. };
  398. dbgu: serial@fffff200 {
  399. compatible = "atmel,at91sam9260-usart";
  400. reg = <0xfffff200 0x200>;
  401. interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
  402. pinctrl-names = "default";
  403. pinctrl-0 = <&pinctrl_dbgu>;
  404. status = "disabled";
  405. };
  406. usart0: serial@fffb0000 {
  407. compatible = "atmel,at91sam9260-usart";
  408. reg = <0xfffb0000 0x200>;
  409. interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
  410. atmel,use-dma-rx;
  411. atmel,use-dma-tx;
  412. pinctrl-names = "default";
  413. pinctrl-0 = <&pinctrl_usart0>;
  414. status = "disabled";
  415. };
  416. usart1: serial@fffb4000 {
  417. compatible = "atmel,at91sam9260-usart";
  418. reg = <0xfffb4000 0x200>;
  419. interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
  420. atmel,use-dma-rx;
  421. atmel,use-dma-tx;
  422. pinctrl-names = "default";
  423. pinctrl-0 = <&pinctrl_usart1>;
  424. status = "disabled";
  425. };
  426. usart2: serial@fffb8000 {
  427. compatible = "atmel,at91sam9260-usart";
  428. reg = <0xfffb8000 0x200>;
  429. interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
  430. atmel,use-dma-rx;
  431. atmel,use-dma-tx;
  432. pinctrl-names = "default";
  433. pinctrl-0 = <&pinctrl_usart2>;
  434. status = "disabled";
  435. };
  436. usart3: serial@fffd0000 {
  437. compatible = "atmel,at91sam9260-usart";
  438. reg = <0xfffd0000 0x200>;
  439. interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
  440. atmel,use-dma-rx;
  441. atmel,use-dma-tx;
  442. pinctrl-names = "default";
  443. pinctrl-0 = <&pinctrl_usart3>;
  444. status = "disabled";
  445. };
  446. uart0: serial@fffd4000 {
  447. compatible = "atmel,at91sam9260-usart";
  448. reg = <0xfffd4000 0x200>;
  449. interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
  450. atmel,use-dma-rx;
  451. atmel,use-dma-tx;
  452. pinctrl-names = "default";
  453. pinctrl-0 = <&pinctrl_uart0>;
  454. status = "disabled";
  455. };
  456. uart1: serial@fffd8000 {
  457. compatible = "atmel,at91sam9260-usart";
  458. reg = <0xfffd8000 0x200>;
  459. interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
  460. atmel,use-dma-rx;
  461. atmel,use-dma-tx;
  462. pinctrl-names = "default";
  463. pinctrl-0 = <&pinctrl_uart1>;
  464. status = "disabled";
  465. };
  466. macb0: ethernet@fffc4000 {
  467. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  468. reg = <0xfffc4000 0x100>;
  469. interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
  470. pinctrl-names = "default";
  471. pinctrl-0 = <&pinctrl_macb_rmii>;
  472. status = "disabled";
  473. };
  474. usb1: gadget@fffa4000 {
  475. compatible = "atmel,at91rm9200-udc";
  476. reg = <0xfffa4000 0x4000>;
  477. interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
  478. status = "disabled";
  479. };
  480. i2c0: i2c@fffac000 {
  481. compatible = "atmel,at91sam9260-i2c";
  482. reg = <0xfffac000 0x100>;
  483. interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
  484. #address-cells = <1>;
  485. #size-cells = <0>;
  486. status = "disabled";
  487. };
  488. mmc0: mmc@fffa8000 {
  489. compatible = "atmel,hsmci";
  490. reg = <0xfffa8000 0x600>;
  491. interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
  492. #address-cells = <1>;
  493. #size-cells = <0>;
  494. status = "disabled";
  495. };
  496. ssc0: ssc@fffbc000 {
  497. compatible = "atmel,at91rm9200-ssc";
  498. reg = <0xfffbc000 0x4000>;
  499. interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
  500. pinctrl-names = "default";
  501. pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
  502. status = "disabled";
  503. };
  504. spi0: spi@fffc8000 {
  505. #address-cells = <1>;
  506. #size-cells = <0>;
  507. compatible = "atmel,at91rm9200-spi";
  508. reg = <0xfffc8000 0x200>;
  509. interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
  510. pinctrl-names = "default";
  511. pinctrl-0 = <&pinctrl_spi0>;
  512. status = "disabled";
  513. };
  514. spi1: spi@fffcc000 {
  515. #address-cells = <1>;
  516. #size-cells = <0>;
  517. compatible = "atmel,at91rm9200-spi";
  518. reg = <0xfffcc000 0x200>;
  519. interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
  520. pinctrl-names = "default";
  521. pinctrl-0 = <&pinctrl_spi1>;
  522. status = "disabled";
  523. };
  524. adc0: adc@fffe0000 {
  525. compatible = "atmel,at91sam9260-adc";
  526. reg = <0xfffe0000 0x100>;
  527. interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
  528. atmel,adc-use-external-triggers;
  529. atmel,adc-channels-used = <0xf>;
  530. atmel,adc-vref = <3300>;
  531. atmel,adc-num-channels = <4>;
  532. atmel,adc-startup-time = <15>;
  533. atmel,adc-channel-base = <0x30>;
  534. atmel,adc-drdy-mask = <0x10000>;
  535. atmel,adc-status-register = <0x1c>;
  536. atmel,adc-trigger-register = <0x04>;
  537. atmel,adc-res = <8 10>;
  538. atmel,adc-res-names = "lowres", "highres";
  539. atmel,adc-use-res = "highres";
  540. trigger@0 {
  541. trigger-name = "timer-counter-0";
  542. trigger-value = <0x1>;
  543. };
  544. trigger@1 {
  545. trigger-name = "timer-counter-1";
  546. trigger-value = <0x3>;
  547. };
  548. trigger@2 {
  549. trigger-name = "timer-counter-2";
  550. trigger-value = <0x5>;
  551. };
  552. trigger@3 {
  553. trigger-name = "external";
  554. trigger-value = <0x13>;
  555. trigger-external;
  556. };
  557. };
  558. watchdog@fffffd40 {
  559. compatible = "atmel,at91sam9260-wdt";
  560. reg = <0xfffffd40 0x10>;
  561. status = "disabled";
  562. };
  563. };
  564. nand0: nand@40000000 {
  565. compatible = "atmel,at91rm9200-nand";
  566. #address-cells = <1>;
  567. #size-cells = <1>;
  568. reg = <0x40000000 0x10000000
  569. 0xffffe800 0x200
  570. >;
  571. atmel,nand-addr-offset = <21>;
  572. atmel,nand-cmd-offset = <22>;
  573. pinctrl-names = "default";
  574. pinctrl-0 = <&pinctrl_nand>;
  575. gpios = <&pioC 13 GPIO_ACTIVE_HIGH
  576. &pioC 14 GPIO_ACTIVE_HIGH
  577. 0
  578. >;
  579. status = "disabled";
  580. };
  581. usb0: ohci@00500000 {
  582. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  583. reg = <0x00500000 0x100000>;
  584. interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
  585. status = "disabled";
  586. };
  587. };
  588. i2c@0 {
  589. compatible = "i2c-gpio";
  590. gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
  591. &pioA 24 GPIO_ACTIVE_HIGH /* scl */
  592. >;
  593. i2c-gpio,sda-open-drain;
  594. i2c-gpio,scl-open-drain;
  595. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  596. #address-cells = <1>;
  597. #size-cells = <0>;
  598. pinctrl-names = "default";
  599. pinctrl-0 = <&pinctrl_i2c_gpio0>;
  600. status = "disabled";
  601. };
  602. };