armada-370-rd.dts 1.9 KB

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  1. /*
  2. * Device Tree file for Marvell Armada 370 Reference Design board
  3. * (RD-88F6710-A1)
  4. *
  5. * Copied from arch/arm/boot/dts/armada-370-db.dts
  6. *
  7. * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. /dts-v1/;
  14. /include/ "armada-370.dtsi"
  15. / {
  16. model = "Marvell Armada 370 Reference Design";
  17. compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
  18. chosen {
  19. bootargs = "console=ttyS0,115200 earlyprintk";
  20. };
  21. memory {
  22. device_type = "memory";
  23. reg = <0x00000000 0x20000000>; /* 512 MB */
  24. };
  25. soc {
  26. internal-regs {
  27. serial@12000 {
  28. clock-frequency = <200000000>;
  29. status = "okay";
  30. };
  31. sata@a0000 {
  32. nr-ports = <2>;
  33. status = "okay";
  34. };
  35. mdio {
  36. phy0: ethernet-phy@0 {
  37. reg = <0>;
  38. };
  39. phy1: ethernet-phy@1 {
  40. reg = <1>;
  41. };
  42. };
  43. ethernet@70000 {
  44. status = "okay";
  45. phy = <&phy0>;
  46. phy-mode = "sgmii";
  47. };
  48. ethernet@74000 {
  49. status = "okay";
  50. phy = <&phy1>;
  51. phy-mode = "rgmii-id";
  52. };
  53. mvsdio@d4000 {
  54. pinctrl-0 = <&sdio_pins1>;
  55. pinctrl-names = "default";
  56. status = "okay";
  57. /* No CD or WP GPIOs */
  58. broken-cd;
  59. };
  60. usb@50000 {
  61. status = "okay";
  62. };
  63. usb@51000 {
  64. status = "okay";
  65. };
  66. gpio-keys {
  67. compatible = "gpio-keys";
  68. #address-cells = <1>;
  69. #size-cells = <0>;
  70. button@1 {
  71. label = "Software Button";
  72. linux,code = <116>;
  73. gpios = <&gpio0 6 1>;
  74. };
  75. };
  76. pcie-controller {
  77. status = "okay";
  78. /* Internal mini-PCIe connector */
  79. pcie@1,0 {
  80. /* Port 0, Lane 0 */
  81. status = "okay";
  82. };
  83. /* Internal mini-PCIe connector */
  84. pcie@2,0 {
  85. /* Port 1, Lane 0 */
  86. status = "okay";
  87. };
  88. };
  89. };
  90. };
  91. };