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- Power Architecture CPU Binding
- Copyright 2013 Freescale Semiconductor Inc.
- Power Architecture CPUs in Freescale SOCs are represented in device trees as
- per the definition in ePAPR.
- In addition to the ePAPR definitions, the properties defined below may be
- present on CPU nodes.
- PROPERTIES
- - fsl,eref-*
- Usage: optional
- Value type: <empty>
- Definition: The EREF (EREF: A Programmer.s Reference Manual for
- Freescale Power Architecture) defines the architecture for Freescale
- Power CPUs. The EREF defines some architecture categories not defined
- by the Power ISA. For these EREF-specific categories, the existence of
- a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
- name with all uppercase letters converted to lowercase, indicates that
- the category is supported by the implementation.
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