linux-vybrid_public/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt

* Samsung Audio Subsystem Clock Controller

The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
binding described here is applicable to all SoC's in Exynos family.

Required Properties:

- compatible: should be one of the following:
  - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
  - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs.

- reg: physical base address and length of the controller's register set.

- #clock-cells: should be 1.

The following is the list of clocks generated by the controller. Each clock is
assigned an identifier and client nodes use this identifier to specify the
clock which they consume. Some of the clocks are available only on a particular
Exynos4 SoC and this is specified where applicable.

Provided clocks:

Clock           ID      SoC (if specific)
-----------------------------------------------

mout_audss      0
mout_i2s        1
dout_srp        2
dout_aud_bus    3
dout_i2s        4
srp_clk         5
i2s_bus         6
sclk_i2s        7
pcm_bus         8
sclk_pcm        9

Example 1: An example of a clock controller node is listed below.

clock_audss: audss-clock-controller@3810000 {
	compatible = "samsung,exynos5250-audss-clock";
	reg = <0x03810000 0x0C>;
	#clock-cells = <1>;
};

Example 2: I2S controller node that consumes the clock generated by the clock
           controller. Refer to the standard clock bindings for information
           about 'clocks' and 'clock-names' property.

i2s0: i2s@03830000 {
	compatible = "samsung,i2s-v5";
	reg = <0x03830000 0x100>;
	dmas = <&pdma0 10
		&pdma0 9
		&pdma0 8>;
	dma-names = "tx", "rx", "tx-sec";
	clocks = <&clock_audss EXYNOS_I2S_BUS>,
		<&clock_audss EXYNOS_I2S_BUS>,
		<&clock_audss EXYNOS_SCLK_I2S>,
		<&clock_audss EXYNOS_MOUT_AUDSS>,
		<&clock_audss EXYNOS_MOUT_I2S>;
	clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
	"mout_audss", "mout_i2s";
};