ppc85xx_rio.c 25 KB

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  1. /*
  2. * MPC85xx RapidIO support
  3. *
  4. * Copyright 2005 MontaVista Software, Inc.
  5. * Matt Porter <mporter@kernel.crashing.org>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <linux/config.h>
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/types.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/rio.h>
  19. #include <linux/rio_drv.h>
  20. #include <asm/io.h>
  21. #define RIO_REGS_BASE (CCSRBAR + 0xc0000)
  22. #define RIO_ATMU_REGS_OFFSET 0x10c00
  23. #define RIO_MSG_REGS_OFFSET 0x11000
  24. #define RIO_MAINT_WIN_SIZE 0x400000
  25. #define RIO_DBELL_WIN_SIZE 0x1000
  26. #define RIO_MSG_OMR_MUI 0x00000002
  27. #define RIO_MSG_OSR_TE 0x00000080
  28. #define RIO_MSG_OSR_QOI 0x00000020
  29. #define RIO_MSG_OSR_QFI 0x00000010
  30. #define RIO_MSG_OSR_MUB 0x00000004
  31. #define RIO_MSG_OSR_EOMI 0x00000002
  32. #define RIO_MSG_OSR_QEI 0x00000001
  33. #define RIO_MSG_IMR_MI 0x00000002
  34. #define RIO_MSG_ISR_TE 0x00000080
  35. #define RIO_MSG_ISR_QFI 0x00000010
  36. #define RIO_MSG_ISR_DIQI 0x00000001
  37. #define RIO_MSG_DESC_SIZE 32
  38. #define RIO_MSG_BUFFER_SIZE 4096
  39. #define RIO_MIN_TX_RING_SIZE 2
  40. #define RIO_MAX_TX_RING_SIZE 2048
  41. #define RIO_MIN_RX_RING_SIZE 2
  42. #define RIO_MAX_RX_RING_SIZE 2048
  43. #define DOORBELL_DMR_DI 0x00000002
  44. #define DOORBELL_DSR_TE 0x00000080
  45. #define DOORBELL_DSR_QFI 0x00000010
  46. #define DOORBELL_DSR_DIQI 0x00000001
  47. #define DOORBELL_TID_OFFSET 0x03
  48. #define DOORBELL_SID_OFFSET 0x05
  49. #define DOORBELL_INFO_OFFSET 0x06
  50. #define DOORBELL_MESSAGE_SIZE 0x08
  51. #define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET))
  52. #define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET))
  53. #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
  54. #define is_power_of_2(x) (((x) & ((x) - 1)) == 0)
  55. struct rio_atmu_regs {
  56. u32 rowtar;
  57. u32 pad1;
  58. u32 rowbar;
  59. u32 pad2;
  60. u32 rowar;
  61. u32 pad3[3];
  62. };
  63. struct rio_msg_regs {
  64. u32 omr;
  65. u32 osr;
  66. u32 pad1;
  67. u32 odqdpar;
  68. u32 pad2;
  69. u32 osar;
  70. u32 odpr;
  71. u32 odatr;
  72. u32 odcr;
  73. u32 pad3;
  74. u32 odqepar;
  75. u32 pad4[13];
  76. u32 imr;
  77. u32 isr;
  78. u32 pad5;
  79. u32 ifqdpar;
  80. u32 pad6;
  81. u32 ifqepar;
  82. u32 pad7[250];
  83. u32 dmr;
  84. u32 dsr;
  85. u32 pad8;
  86. u32 dqdpar;
  87. u32 pad9;
  88. u32 dqepar;
  89. u32 pad10[26];
  90. u32 pwmr;
  91. u32 pwsr;
  92. u32 pad11;
  93. u32 pwqbar;
  94. };
  95. struct rio_tx_desc {
  96. u32 res1;
  97. u32 saddr;
  98. u32 dport;
  99. u32 dattr;
  100. u32 res2;
  101. u32 res3;
  102. u32 dwcnt;
  103. u32 res4;
  104. };
  105. static u32 regs_win;
  106. static struct rio_atmu_regs *atmu_regs;
  107. static struct rio_atmu_regs *maint_atmu_regs;
  108. static struct rio_atmu_regs *dbell_atmu_regs;
  109. static u32 dbell_win;
  110. static u32 maint_win;
  111. static struct rio_msg_regs *msg_regs;
  112. static struct rio_dbell_ring {
  113. void *virt;
  114. dma_addr_t phys;
  115. } dbell_ring;
  116. static struct rio_msg_tx_ring {
  117. void *virt;
  118. dma_addr_t phys;
  119. void *virt_buffer[RIO_MAX_TX_RING_SIZE];
  120. dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
  121. int tx_slot;
  122. int size;
  123. } msg_tx_ring;
  124. static struct rio_msg_rx_ring {
  125. void *virt;
  126. dma_addr_t phys;
  127. void *virt_buffer[RIO_MAX_RX_RING_SIZE];
  128. int rx_slot;
  129. int size;
  130. } msg_rx_ring;
  131. /**
  132. * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message
  133. * @index: ID of RapidIO interface
  134. * @destid: Destination ID of target device
  135. * @data: 16-bit info field of RapidIO doorbell message
  136. *
  137. * Sends a MPC85xx doorbell message. Returns %0 on success or
  138. * %-EINVAL on failure.
  139. */
  140. static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data)
  141. {
  142. pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n",
  143. index, destid, data);
  144. out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22);
  145. out_be16((void *)(dbell_win), data);
  146. return 0;
  147. }
  148. /**
  149. * mpc85xx_local_config_read - Generate a MPC85xx local config space read
  150. * @index: ID of RapdiIO interface
  151. * @offset: Offset into configuration space
  152. * @len: Length (in bytes) of the maintenance transaction
  153. * @data: Value to be read into
  154. *
  155. * Generates a MPC85xx local configuration space read. Returns %0 on
  156. * success or %-EINVAL on failure.
  157. */
  158. static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data)
  159. {
  160. pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index,
  161. offset);
  162. *data = in_be32((void *)(regs_win + offset));
  163. return 0;
  164. }
  165. /**
  166. * mpc85xx_local_config_write - Generate a MPC85xx local config space write
  167. * @index: ID of RapdiIO interface
  168. * @offset: Offset into configuration space
  169. * @len: Length (in bytes) of the maintenance transaction
  170. * @data: Value to be written
  171. *
  172. * Generates a MPC85xx local configuration space write. Returns %0 on
  173. * success or %-EINVAL on failure.
  174. */
  175. static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data)
  176. {
  177. pr_debug
  178. ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n",
  179. index, offset, data);
  180. out_be32((void *)(regs_win + offset), data);
  181. return 0;
  182. }
  183. /**
  184. * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction
  185. * @index: ID of RapdiIO interface
  186. * @destid: Destination ID of transaction
  187. * @hopcount: Number of hops to target device
  188. * @offset: Offset into configuration space
  189. * @len: Length (in bytes) of the maintenance transaction
  190. * @val: Location to be read into
  191. *
  192. * Generates a MPC85xx read maintenance transaction. Returns %0 on
  193. * success or %-EINVAL on failure.
  194. */
  195. static int
  196. mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len,
  197. u32 * val)
  198. {
  199. u8 *data;
  200. pr_debug
  201. ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
  202. index, destid, hopcount, offset, len);
  203. out_be32((void *)&maint_atmu_regs->rowtar,
  204. (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
  205. data = (u8 *) maint_win + offset;
  206. switch (len) {
  207. case 1:
  208. *val = in_8((u8 *) data);
  209. break;
  210. case 2:
  211. *val = in_be16((u16 *) data);
  212. break;
  213. default:
  214. *val = in_be32((u32 *) data);
  215. break;
  216. }
  217. return 0;
  218. }
  219. /**
  220. * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction
  221. * @index: ID of RapdiIO interface
  222. * @destid: Destination ID of transaction
  223. * @hopcount: Number of hops to target device
  224. * @offset: Offset into configuration space
  225. * @len: Length (in bytes) of the maintenance transaction
  226. * @val: Value to be written
  227. *
  228. * Generates an MPC85xx write maintenance transaction. Returns %0 on
  229. * success or %-EINVAL on failure.
  230. */
  231. static int
  232. mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset,
  233. int len, u32 val)
  234. {
  235. u8 *data;
  236. pr_debug
  237. ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
  238. index, destid, hopcount, offset, len, val);
  239. out_be32((void *)&maint_atmu_regs->rowtar,
  240. (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9));
  241. data = (u8 *) maint_win + offset;
  242. switch (len) {
  243. case 1:
  244. out_8((u8 *) data, val);
  245. break;
  246. case 2:
  247. out_be16((u16 *) data, val);
  248. break;
  249. default:
  250. out_be32((u32 *) data, val);
  251. break;
  252. }
  253. return 0;
  254. }
  255. /**
  256. * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue
  257. * @mport: Master port with outbound message queue
  258. * @rdev: Target of outbound message
  259. * @mbox: Outbound mailbox
  260. * @buffer: Message to add to outbound queue
  261. * @len: Length of message
  262. *
  263. * Adds the @buffer message to the MPC85xx outbound message queue. Returns
  264. * %0 on success or %-EINVAL on failure.
  265. */
  266. int
  267. rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
  268. void *buffer, size_t len)
  269. {
  270. u32 omr;
  271. struct rio_tx_desc *desc =
  272. (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot;
  273. int ret = 0;
  274. pr_debug
  275. ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n",
  276. rdev->destid, mbox, (int)buffer, len);
  277. if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
  278. ret = -EINVAL;
  279. goto out;
  280. }
  281. /* Copy and clear rest of buffer */
  282. memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len);
  283. if (len < (RIO_MAX_MSG_SIZE - 4))
  284. memset((void *)((u32) msg_tx_ring.
  285. virt_buffer[msg_tx_ring.tx_slot] + len), 0,
  286. RIO_MAX_MSG_SIZE - len);
  287. /* Set mbox field for message */
  288. desc->dport = mbox & 0x3;
  289. /* Enable EOMI interrupt, set priority, and set destid */
  290. desc->dattr = 0x28000000 | (rdev->destid << 2);
  291. /* Set transfer size aligned to next power of 2 (in double words) */
  292. desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
  293. /* Set snooping and source buffer address */
  294. desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot];
  295. /* Increment enqueue pointer */
  296. omr = in_be32((void *)&msg_regs->omr);
  297. out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI);
  298. /* Go to next descriptor */
  299. if (++msg_tx_ring.tx_slot == msg_tx_ring.size)
  300. msg_tx_ring.tx_slot = 0;
  301. out:
  302. return ret;
  303. }
  304. EXPORT_SYMBOL_GPL(rio_hw_add_outb_message);
  305. /**
  306. * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler
  307. * @irq: Linux interrupt number
  308. * @dev_instance: Pointer to interrupt-specific data
  309. * @regs: Register context
  310. *
  311. * Handles outbound message interrupts. Executes a register outbound
  312. * mailbox event handler and acks the interrupt occurence.
  313. */
  314. static irqreturn_t
  315. mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs)
  316. {
  317. int osr;
  318. struct rio_mport *port = (struct rio_mport *)dev_instance;
  319. osr = in_be32((void *)&msg_regs->osr);
  320. if (osr & RIO_MSG_OSR_TE) {
  321. pr_info("RIO: outbound message transmission error\n");
  322. out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE);
  323. goto out;
  324. }
  325. if (osr & RIO_MSG_OSR_QOI) {
  326. pr_info("RIO: outbound message queue overflow\n");
  327. out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI);
  328. goto out;
  329. }
  330. if (osr & RIO_MSG_OSR_EOMI) {
  331. u32 dqp = in_be32((void *)&msg_regs->odqdpar);
  332. int slot = (dqp - msg_tx_ring.phys) >> 5;
  333. port->outb_msg[0].mcback(port, -1, slot);
  334. /* Ack the end-of-message interrupt */
  335. out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI);
  336. }
  337. out:
  338. return IRQ_HANDLED;
  339. }
  340. /**
  341. * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox
  342. * @mport: Master port implementing the outbound message unit
  343. * @mbox: Mailbox to open
  344. * @entries: Number of entries in the outbound mailbox ring
  345. *
  346. * Initializes buffer ring, request the outbound message interrupt,
  347. * and enables the outbound message unit. Returns %0 on success and
  348. * %-EINVAL or %-ENOMEM on failure.
  349. */
  350. int rio_open_outb_mbox(struct rio_mport *mport, int mbox, int entries)
  351. {
  352. int i, j, rc = 0;
  353. if ((entries < RIO_MIN_TX_RING_SIZE) ||
  354. (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
  355. rc = -EINVAL;
  356. goto out;
  357. }
  358. /* Initialize shadow copy ring */
  359. msg_tx_ring.size = entries;
  360. for (i = 0; i < msg_tx_ring.size; i++) {
  361. if (!
  362. (msg_tx_ring.virt_buffer[i] =
  363. dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE,
  364. &msg_tx_ring.phys_buffer[i],
  365. GFP_KERNEL))) {
  366. rc = -ENOMEM;
  367. for (j = 0; j < msg_tx_ring.size; j++)
  368. if (msg_tx_ring.virt_buffer[j])
  369. dma_free_coherent(NULL,
  370. RIO_MSG_BUFFER_SIZE,
  371. msg_tx_ring.
  372. virt_buffer[j],
  373. msg_tx_ring.
  374. phys_buffer[j]);
  375. goto out;
  376. }
  377. }
  378. /* Initialize outbound message descriptor ring */
  379. if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL,
  380. msg_tx_ring.size *
  381. RIO_MSG_DESC_SIZE,
  382. &msg_tx_ring.phys,
  383. GFP_KERNEL))) {
  384. rc = -ENOMEM;
  385. goto out_dma;
  386. }
  387. memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE);
  388. msg_tx_ring.tx_slot = 0;
  389. /* Point dequeue/enqueue pointers at first entry in ring */
  390. out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys);
  391. out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys);
  392. /* Configure for snooping */
  393. out_be32((void *)&msg_regs->osar, 0x00000004);
  394. /* Clear interrupt status */
  395. out_be32((void *)&msg_regs->osr, 0x000000b3);
  396. /* Hook up outbound message handler */
  397. if ((rc =
  398. request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0,
  399. "msg_tx", (void *)mport)) < 0)
  400. goto out_irq;
  401. /*
  402. * Configure outbound message unit
  403. * Snooping
  404. * Interrupts (all enabled, except QEIE)
  405. * Chaining mode
  406. * Disable
  407. */
  408. out_be32((void *)&msg_regs->omr, 0x00100220);
  409. /* Set number of entries */
  410. out_be32((void *)&msg_regs->omr,
  411. in_be32((void *)&msg_regs->omr) |
  412. ((get_bitmask_order(entries) - 2) << 12));
  413. /* Now enable the unit */
  414. out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1);
  415. out:
  416. return rc;
  417. out_irq:
  418. dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
  419. msg_tx_ring.virt, msg_tx_ring.phys);
  420. out_dma:
  421. for (i = 0; i < msg_tx_ring.size; i++)
  422. dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
  423. msg_tx_ring.virt_buffer[i],
  424. msg_tx_ring.phys_buffer[i]);
  425. return rc;
  426. }
  427. /**
  428. * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox
  429. * @mport: Master port implementing the outbound message unit
  430. * @mbox: Mailbox to close
  431. *
  432. * Disables the outbound message unit, free all buffers, and
  433. * frees the outbound message interrupt.
  434. */
  435. void rio_close_outb_mbox(struct rio_mport *mport, int mbox)
  436. {
  437. /* Disable inbound message unit */
  438. out_be32((void *)&msg_regs->omr, 0);
  439. /* Free ring */
  440. dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE,
  441. msg_tx_ring.virt, msg_tx_ring.phys);
  442. /* Free interrupt */
  443. free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport);
  444. }
  445. /**
  446. * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler
  447. * @irq: Linux interrupt number
  448. * @dev_instance: Pointer to interrupt-specific data
  449. * @regs: Register context
  450. *
  451. * Handles inbound message interrupts. Executes a registered inbound
  452. * mailbox event handler and acks the interrupt occurence.
  453. */
  454. static irqreturn_t
  455. mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs)
  456. {
  457. int isr;
  458. struct rio_mport *port = (struct rio_mport *)dev_instance;
  459. isr = in_be32((void *)&msg_regs->isr);
  460. if (isr & RIO_MSG_ISR_TE) {
  461. pr_info("RIO: inbound message reception error\n");
  462. out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE);
  463. goto out;
  464. }
  465. /* XXX Need to check/dispatch until queue empty */
  466. if (isr & RIO_MSG_ISR_DIQI) {
  467. /*
  468. * We implement *only* mailbox 0, but can receive messages
  469. * for any mailbox/letter to that mailbox destination. So,
  470. * make the callback with an unknown/invalid mailbox number
  471. * argument.
  472. */
  473. port->inb_msg[0].mcback(port, -1, -1);
  474. /* Ack the queueing interrupt */
  475. out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI);
  476. }
  477. out:
  478. return IRQ_HANDLED;
  479. }
  480. /**
  481. * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox
  482. * @mport: Master port implementing the inbound message unit
  483. * @mbox: Mailbox to open
  484. * @entries: Number of entries in the inbound mailbox ring
  485. *
  486. * Initializes buffer ring, request the inbound message interrupt,
  487. * and enables the inbound message unit. Returns %0 on success
  488. * and %-EINVAL or %-ENOMEM on failure.
  489. */
  490. int rio_open_inb_mbox(struct rio_mport *mport, int mbox, int entries)
  491. {
  492. int i, rc = 0;
  493. if ((entries < RIO_MIN_RX_RING_SIZE) ||
  494. (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
  495. rc = -EINVAL;
  496. goto out;
  497. }
  498. /* Initialize client buffer ring */
  499. msg_rx_ring.size = entries;
  500. msg_rx_ring.rx_slot = 0;
  501. for (i = 0; i < msg_rx_ring.size; i++)
  502. msg_rx_ring.virt_buffer[i] = NULL;
  503. /* Initialize inbound message ring */
  504. if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL,
  505. msg_rx_ring.size *
  506. RIO_MAX_MSG_SIZE,
  507. &msg_rx_ring.phys,
  508. GFP_KERNEL))) {
  509. rc = -ENOMEM;
  510. goto out;
  511. }
  512. /* Point dequeue/enqueue pointers at first entry in ring */
  513. out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys);
  514. out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys);
  515. /* Clear interrupt status */
  516. out_be32((void *)&msg_regs->isr, 0x00000091);
  517. /* Hook up inbound message handler */
  518. if ((rc =
  519. request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0,
  520. "msg_rx", (void *)mport)) < 0) {
  521. dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE,
  522. msg_tx_ring.virt_buffer[i],
  523. msg_tx_ring.phys_buffer[i]);
  524. goto out;
  525. }
  526. /*
  527. * Configure inbound message unit:
  528. * Snooping
  529. * 4KB max message size
  530. * Unmask all interrupt sources
  531. * Disable
  532. */
  533. out_be32((void *)&msg_regs->imr, 0x001b0060);
  534. /* Set number of queue entries */
  535. out_be32((void *)&msg_regs->imr,
  536. in_be32((void *)&msg_regs->imr) |
  537. ((get_bitmask_order(entries) - 2) << 12));
  538. /* Now enable the unit */
  539. out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1);
  540. out:
  541. return rc;
  542. }
  543. /**
  544. * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox
  545. * @mport: Master port implementing the inbound message unit
  546. * @mbox: Mailbox to close
  547. *
  548. * Disables the inbound message unit, free all buffers, and
  549. * frees the inbound message interrupt.
  550. */
  551. void rio_close_inb_mbox(struct rio_mport *mport, int mbox)
  552. {
  553. /* Disable inbound message unit */
  554. out_be32((void *)&msg_regs->imr, 0);
  555. /* Free ring */
  556. dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE,
  557. msg_rx_ring.virt, msg_rx_ring.phys);
  558. /* Free interrupt */
  559. free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport);
  560. }
  561. /**
  562. * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
  563. * @mport: Master port implementing the inbound message unit
  564. * @mbox: Inbound mailbox number
  565. * @buf: Buffer to add to inbound queue
  566. *
  567. * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
  568. * %0 on success or %-EINVAL on failure.
  569. */
  570. int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
  571. {
  572. int rc = 0;
  573. pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
  574. msg_rx_ring.rx_slot);
  575. if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) {
  576. printk(KERN_ERR
  577. "RIO: error adding inbound buffer %d, buffer exists\n",
  578. msg_rx_ring.rx_slot);
  579. rc = -EINVAL;
  580. goto out;
  581. }
  582. msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf;
  583. if (++msg_rx_ring.rx_slot == msg_rx_ring.size)
  584. msg_rx_ring.rx_slot = 0;
  585. out:
  586. return rc;
  587. }
  588. EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer);
  589. /**
  590. * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit
  591. * @mport: Master port implementing the inbound message unit
  592. * @mbox: Inbound mailbox number
  593. *
  594. * Gets the next available inbound message from the inbound message queue.
  595. * A pointer to the message is returned on success or NULL on failure.
  596. */
  597. void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox)
  598. {
  599. u32 imr;
  600. u32 phys_buf, virt_buf;
  601. void *buf = NULL;
  602. int buf_idx;
  603. phys_buf = in_be32((void *)&msg_regs->ifqdpar);
  604. /* If no more messages, then bail out */
  605. if (phys_buf == in_be32((void *)&msg_regs->ifqepar))
  606. goto out2;
  607. virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys);
  608. buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
  609. buf = msg_rx_ring.virt_buffer[buf_idx];
  610. if (!buf) {
  611. printk(KERN_ERR
  612. "RIO: inbound message copy failed, no buffers\n");
  613. goto out1;
  614. }
  615. /* Copy max message size, caller is expected to allocate that big */
  616. memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
  617. /* Clear the available buffer */
  618. msg_rx_ring.virt_buffer[buf_idx] = NULL;
  619. out1:
  620. imr = in_be32((void *)&msg_regs->imr);
  621. out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI);
  622. out2:
  623. return buf;
  624. }
  625. EXPORT_SYMBOL_GPL(rio_hw_get_inb_message);
  626. /**
  627. * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler
  628. * @irq: Linux interrupt number
  629. * @dev_instance: Pointer to interrupt-specific data
  630. * @regs: Register context
  631. *
  632. * Handles doorbell interrupts. Parses a list of registered
  633. * doorbell event handlers and executes a matching event handler.
  634. */
  635. static irqreturn_t
  636. mpc85xx_rio_dbell_handler(int irq, void *dev_instance, struct pt_regs *regs)
  637. {
  638. int dsr;
  639. struct rio_mport *port = (struct rio_mport *)dev_instance;
  640. dsr = in_be32((void *)&msg_regs->dsr);
  641. if (dsr & DOORBELL_DSR_TE) {
  642. pr_info("RIO: doorbell reception error\n");
  643. out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE);
  644. goto out;
  645. }
  646. if (dsr & DOORBELL_DSR_QFI) {
  647. pr_info("RIO: doorbell queue full\n");
  648. out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI);
  649. goto out;
  650. }
  651. /* XXX Need to check/dispatch until queue empty */
  652. if (dsr & DOORBELL_DSR_DIQI) {
  653. u32 dmsg =
  654. (u32) dbell_ring.virt +
  655. (in_be32((void *)&msg_regs->dqdpar) & 0xfff);
  656. u32 dmr;
  657. struct rio_dbell *dbell;
  658. int found = 0;
  659. pr_debug
  660. ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
  661. DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
  662. list_for_each_entry(dbell, &port->dbells, node) {
  663. if ((dbell->res->start <= DBELL_INF(dmsg)) &&
  664. (dbell->res->end >= DBELL_INF(dmsg))) {
  665. found = 1;
  666. break;
  667. }
  668. }
  669. if (found) {
  670. dbell->dinb(port, DBELL_SID(dmsg), DBELL_TID(dmsg),
  671. DBELL_INF(dmsg));
  672. } else {
  673. pr_debug
  674. ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
  675. DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
  676. }
  677. dmr = in_be32((void *)&msg_regs->dmr);
  678. out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI);
  679. out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI);
  680. }
  681. out:
  682. return IRQ_HANDLED;
  683. }
  684. /**
  685. * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init
  686. * @mport: Master port implementing the inbound doorbell unit
  687. *
  688. * Initializes doorbell unit hardware and inbound DMA buffer
  689. * ring. Called from mpc85xx_rio_setup(). Returns %0 on success
  690. * or %-ENOMEM on failure.
  691. */
  692. static int mpc85xx_rio_doorbell_init(struct rio_mport *mport)
  693. {
  694. int rc = 0;
  695. /* Map outbound doorbell window immediately after maintenance window */
  696. if (!(dbell_win =
  697. (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
  698. RIO_DBELL_WIN_SIZE))) {
  699. printk(KERN_ERR
  700. "RIO: unable to map outbound doorbell window\n");
  701. rc = -ENOMEM;
  702. goto out;
  703. }
  704. /* Initialize inbound doorbells */
  705. if (!(dbell_ring.virt = dma_alloc_coherent(NULL,
  706. 512 * DOORBELL_MESSAGE_SIZE,
  707. &dbell_ring.phys,
  708. GFP_KERNEL))) {
  709. printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
  710. rc = -ENOMEM;
  711. iounmap((void *)dbell_win);
  712. goto out;
  713. }
  714. /* Point dequeue/enqueue pointers at first entry in ring */
  715. out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys);
  716. out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys);
  717. /* Clear interrupt status */
  718. out_be32((void *)&msg_regs->dsr, 0x00000091);
  719. /* Hook up doorbell handler */
  720. if ((rc =
  721. request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0,
  722. "dbell_rx", (void *)mport) < 0)) {
  723. iounmap((void *)dbell_win);
  724. dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE,
  725. dbell_ring.virt, dbell_ring.phys);
  726. printk(KERN_ERR
  727. "MPC85xx RIO: unable to request inbound doorbell irq");
  728. goto out;
  729. }
  730. /* Configure doorbells for snooping, 512 entries, and enable */
  731. out_be32((void *)&msg_regs->dmr, 0x00108161);
  732. out:
  733. return rc;
  734. }
  735. static char *cmdline = NULL;
  736. static int mpc85xx_rio_get_hdid(int index)
  737. {
  738. /* XXX Need to parse multiple entries in some format */
  739. if (!cmdline)
  740. return -1;
  741. return simple_strtol(cmdline, NULL, 0);
  742. }
  743. static int mpc85xx_rio_get_cmdline(char *s)
  744. {
  745. if (!s)
  746. return 0;
  747. cmdline = s;
  748. return 1;
  749. }
  750. __setup("riohdid=", mpc85xx_rio_get_cmdline);
  751. /**
  752. * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface
  753. * @law_start: Starting physical address of RapidIO LAW
  754. * @law_size: Size of RapidIO LAW
  755. *
  756. * Initializes MPC85xx RapidIO hardware interface, configures
  757. * master port with system-specific info, and registers the
  758. * master port with the RapidIO subsystem.
  759. */
  760. void mpc85xx_rio_setup(int law_start, int law_size)
  761. {
  762. struct rio_ops *ops;
  763. struct rio_mport *port;
  764. ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
  765. ops->lcread = mpc85xx_local_config_read;
  766. ops->lcwrite = mpc85xx_local_config_write;
  767. ops->cread = mpc85xx_rio_config_read;
  768. ops->cwrite = mpc85xx_rio_config_write;
  769. ops->dsend = mpc85xx_rio_doorbell_send;
  770. port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL);
  771. port->id = 0;
  772. port->index = 0;
  773. INIT_LIST_HEAD(&port->dbells);
  774. port->iores.start = law_start;
  775. port->iores.end = law_start + law_size;
  776. port->iores.flags = IORESOURCE_MEM;
  777. rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
  778. rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
  779. rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
  780. strcpy(port->name, "RIO0 mport");
  781. port->ops = ops;
  782. port->host_deviceid = mpc85xx_rio_get_hdid(port->id);
  783. rio_register_mport(port);
  784. regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000);
  785. atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET);
  786. maint_atmu_regs = atmu_regs + 1;
  787. dbell_atmu_regs = atmu_regs + 2;
  788. msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET);
  789. /* Configure maintenance transaction window */
  790. out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000);
  791. out_be32((void *)&maint_atmu_regs->rowar, 0x80077015);
  792. maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE);
  793. /* Configure outbound doorbell window */
  794. out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400);
  795. out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b);
  796. mpc85xx_rio_doorbell_init(port);
  797. }