slc90e66.c 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195
  1. /*
  2. * linux/drivers/ide/pci/slc90e66.c Version 0.18 Aug 9, 2007
  3. *
  4. * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
  5. * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
  6. *
  7. * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
  8. * but this keeps the ISA-Bridge and slots alive.
  9. *
  10. */
  11. #include <linux/types.h>
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/ioport.h>
  15. #include <linux/pci.h>
  16. #include <linux/hdreg.h>
  17. #include <linux/ide.h>
  18. #include <linux/delay.h>
  19. #include <linux/init.h>
  20. #include <asm/io.h>
  21. static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
  22. {
  23. ide_hwif_t *hwif = HWIF(drive);
  24. struct pci_dev *dev = hwif->pci_dev;
  25. int is_slave = drive->dn & 1;
  26. int master_port = hwif->channel ? 0x42 : 0x40;
  27. int slave_port = 0x44;
  28. unsigned long flags;
  29. u16 master_data;
  30. u8 slave_data;
  31. int control = 0;
  32. /* ISP RTC */
  33. static const u8 timings[][2]= {
  34. { 0, 0 },
  35. { 0, 0 },
  36. { 1, 0 },
  37. { 2, 1 },
  38. { 2, 3 }, };
  39. spin_lock_irqsave(&ide_lock, flags);
  40. pci_read_config_word(dev, master_port, &master_data);
  41. if (pio > 1)
  42. control |= 1; /* Programmable timing on */
  43. if (drive->media == ide_disk)
  44. control |= 4; /* Prefetch, post write */
  45. if (pio > 2)
  46. control |= 2; /* IORDY */
  47. if (is_slave) {
  48. master_data |= 0x4000;
  49. master_data &= ~0x0070;
  50. if (pio > 1) {
  51. /* Set PPE, IE and TIME */
  52. master_data |= control << 4;
  53. }
  54. pci_read_config_byte(dev, slave_port, &slave_data);
  55. slave_data &= hwif->channel ? 0x0f : 0xf0;
  56. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  57. (hwif->channel ? 4 : 0);
  58. } else {
  59. master_data &= ~0x3307;
  60. if (pio > 1) {
  61. /* enable PPE, IE and TIME */
  62. master_data |= control;
  63. }
  64. master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  65. }
  66. pci_write_config_word(dev, master_port, master_data);
  67. if (is_slave)
  68. pci_write_config_byte(dev, slave_port, slave_data);
  69. spin_unlock_irqrestore(&ide_lock, flags);
  70. }
  71. static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
  72. {
  73. ide_hwif_t *hwif = HWIF(drive);
  74. struct pci_dev *dev = hwif->pci_dev;
  75. u8 maslave = hwif->channel ? 0x42 : 0x40;
  76. int sitre = 0, a_speed = 7 << (drive->dn * 4);
  77. int u_speed = 0, u_flag = 1 << drive->dn;
  78. u16 reg4042, reg44, reg48, reg4a;
  79. pci_read_config_word(dev, maslave, &reg4042);
  80. sitre = (reg4042 & 0x4000) ? 1 : 0;
  81. pci_read_config_word(dev, 0x44, &reg44);
  82. pci_read_config_word(dev, 0x48, &reg48);
  83. pci_read_config_word(dev, 0x4a, &reg4a);
  84. switch(speed) {
  85. case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
  86. case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
  87. case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
  88. case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
  89. case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
  90. case XFER_MW_DMA_2:
  91. case XFER_MW_DMA_1:
  92. case XFER_SW_DMA_2: break;
  93. default: return;
  94. }
  95. if (speed >= XFER_UDMA_0) {
  96. if (!(reg48 & u_flag))
  97. pci_write_config_word(dev, 0x48, reg48|u_flag);
  98. /* FIXME: (reg4a & a_speed) ? */
  99. if ((reg4a & u_speed) != u_speed) {
  100. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  101. pci_read_config_word(dev, 0x4a, &reg4a);
  102. pci_write_config_word(dev, 0x4a, reg4a|u_speed);
  103. }
  104. } else {
  105. const u8 mwdma_to_pio[] = { 0, 3, 4 };
  106. u8 pio;
  107. if (reg48 & u_flag)
  108. pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
  109. if (reg4a & a_speed)
  110. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  111. if (speed >= XFER_MW_DMA_0)
  112. pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
  113. else
  114. pio = 2; /* only SWDMA2 is allowed */
  115. slc90e66_set_pio_mode(drive, pio);
  116. }
  117. }
  118. static void __devinit init_hwif_slc90e66 (ide_hwif_t *hwif)
  119. {
  120. u8 reg47 = 0;
  121. u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
  122. if (!hwif->irq)
  123. hwif->irq = hwif->channel ? 15 : 14;
  124. hwif->set_pio_mode = &slc90e66_set_pio_mode;
  125. hwif->set_dma_mode = &slc90e66_set_dma_mode;
  126. pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
  127. hwif->drives[0].autotune = 1;
  128. hwif->drives[1].autotune = 1;
  129. if (hwif->dma_base == 0)
  130. return;
  131. hwif->atapi_dma = 1;
  132. hwif->ultra_mask = 0x1f;
  133. hwif->mwdma_mask = 0x06;
  134. hwif->swdma_mask = 0x04;
  135. if (hwif->cbl != ATA_CBL_PATA40_SHORT)
  136. /* bit[0(1)]: 0:80, 1:40 */
  137. hwif->cbl = (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
  138. }
  139. static ide_pci_device_t slc90e66_chipset __devinitdata = {
  140. .name = "SLC90E66",
  141. .init_hwif = init_hwif_slc90e66,
  142. .autodma = AUTODMA,
  143. .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
  144. .bootable = ON_BOARD,
  145. .pio_mask = ATA_PIO4,
  146. };
  147. static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  148. {
  149. return ide_setup_pci_device(dev, &slc90e66_chipset);
  150. }
  151. static const struct pci_device_id slc90e66_pci_tbl[] = {
  152. { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
  153. { 0, },
  154. };
  155. MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
  156. static struct pci_driver driver = {
  157. .name = "SLC90e66_IDE",
  158. .id_table = slc90e66_pci_tbl,
  159. .probe = slc90e66_init_one,
  160. };
  161. static int __init slc90e66_ide_init(void)
  162. {
  163. return ide_pci_register_driver(&driver);
  164. }
  165. module_init(slc90e66_ide_init);
  166. MODULE_AUTHOR("Andre Hedrick");
  167. MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
  168. MODULE_LICENSE("GPL");