iwl-rx.c 35 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <net/mac80211.h>
  31. #include <asm/unaligned.h>
  32. #include "iwl-eeprom.h"
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-sta.h"
  36. #include "iwl-io.h"
  37. #include "iwl-calib.h"
  38. #include "iwl-helpers.h"
  39. /************************** RX-FUNCTIONS ****************************/
  40. /*
  41. * Rx theory of operation
  42. *
  43. * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  44. * each of which point to Receive Buffers to be filled by the NIC. These get
  45. * used not only for Rx frames, but for any command response or notification
  46. * from the NIC. The driver and NIC manage the Rx buffers by means
  47. * of indexes into the circular buffer.
  48. *
  49. * Rx Queue Indexes
  50. * The host/firmware share two index registers for managing the Rx buffers.
  51. *
  52. * The READ index maps to the first position that the firmware may be writing
  53. * to -- the driver can read up to (but not including) this position and get
  54. * good data.
  55. * The READ index is managed by the firmware once the card is enabled.
  56. *
  57. * The WRITE index maps to the last position the driver has read from -- the
  58. * position preceding WRITE is the last slot the firmware can place a packet.
  59. *
  60. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  61. * WRITE = READ.
  62. *
  63. * During initialization, the host sets up the READ queue position to the first
  64. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  65. *
  66. * When the firmware places a packet in a buffer, it will advance the READ index
  67. * and fire the RX interrupt. The driver can then query the READ index and
  68. * process as many packets as possible, moving the WRITE index forward as it
  69. * resets the Rx queue buffers with new memory.
  70. *
  71. * The management in the driver is as follows:
  72. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  73. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  74. * to replenish the iwl->rxq->rx_free.
  75. * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  76. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  77. * 'processed' and 'read' driver indexes as well)
  78. * + A received packet is processed and handed to the kernel network stack,
  79. * detached from the iwl->rxq. The driver 'processed' index is updated.
  80. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  81. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  82. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  83. * were enough free buffers and RX_STALLED is set it is cleared.
  84. *
  85. *
  86. * Driver sequence:
  87. *
  88. * iwl_rx_queue_alloc() Allocates rx_free
  89. * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
  90. * iwl_rx_queue_restock
  91. * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
  92. * queue, updates firmware pointers, and updates
  93. * the WRITE index. If insufficient rx_free buffers
  94. * are available, schedules iwl_rx_replenish
  95. *
  96. * -- enable interrupts --
  97. * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
  98. * READ INDEX, detaching the SKB from the pool.
  99. * Moves the packet buffer from queue to rx_used.
  100. * Calls iwl_rx_queue_restock to refill any empty
  101. * slots.
  102. * ...
  103. *
  104. */
  105. /**
  106. * iwl_rx_queue_space - Return number of free slots available in queue.
  107. */
  108. int iwl_rx_queue_space(const struct iwl_rx_queue *q)
  109. {
  110. int s = q->read - q->write;
  111. if (s <= 0)
  112. s += RX_QUEUE_SIZE;
  113. /* keep some buffer to not confuse full and empty queue */
  114. s -= 2;
  115. if (s < 0)
  116. s = 0;
  117. return s;
  118. }
  119. EXPORT_SYMBOL(iwl_rx_queue_space);
  120. /**
  121. * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  122. */
  123. int iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  124. {
  125. u32 reg = 0;
  126. int ret = 0;
  127. unsigned long flags;
  128. spin_lock_irqsave(&q->lock, flags);
  129. if (q->need_update == 0)
  130. goto exit_unlock;
  131. /* If power-saving is in use, make sure device is awake */
  132. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  133. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  134. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  135. iwl_set_bit(priv, CSR_GP_CNTRL,
  136. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  137. goto exit_unlock;
  138. }
  139. ret = iwl_grab_nic_access(priv);
  140. if (ret)
  141. goto exit_unlock;
  142. /* Device expects a multiple of 8 */
  143. iwl_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  144. q->write & ~0x7);
  145. iwl_release_nic_access(priv);
  146. /* Else device is assumed to be awake */
  147. } else
  148. /* Device expects a multiple of 8 */
  149. iwl_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  150. q->need_update = 0;
  151. exit_unlock:
  152. spin_unlock_irqrestore(&q->lock, flags);
  153. return ret;
  154. }
  155. EXPORT_SYMBOL(iwl_rx_queue_update_write_ptr);
  156. /**
  157. * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  158. */
  159. static inline __le32 iwl_dma_addr2rbd_ptr(struct iwl_priv *priv,
  160. dma_addr_t dma_addr)
  161. {
  162. return cpu_to_le32((u32)(dma_addr >> 8));
  163. }
  164. /**
  165. * iwl_rx_queue_restock - refill RX queue from pre-allocated pool
  166. *
  167. * If there are slots in the RX queue that need to be restocked,
  168. * and we have free pre-allocated buffers, fill the ranks as much
  169. * as we can, pulling from rx_free.
  170. *
  171. * This moves the 'write' index forward to catch up with 'processed', and
  172. * also updates the memory address in the firmware to reference the new
  173. * target buffer.
  174. */
  175. int iwl_rx_queue_restock(struct iwl_priv *priv)
  176. {
  177. struct iwl_rx_queue *rxq = &priv->rxq;
  178. struct list_head *element;
  179. struct iwl_rx_mem_buffer *rxb;
  180. unsigned long flags;
  181. int write;
  182. int ret = 0;
  183. spin_lock_irqsave(&rxq->lock, flags);
  184. write = rxq->write & ~0x7;
  185. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  186. /* Get next free Rx buffer, remove from free list */
  187. element = rxq->rx_free.next;
  188. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  189. list_del(element);
  190. /* Point to Rx buffer via next RBD in circular buffer */
  191. rxq->bd[rxq->write] = iwl_dma_addr2rbd_ptr(priv, rxb->aligned_dma_addr);
  192. rxq->queue[rxq->write] = rxb;
  193. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  194. rxq->free_count--;
  195. }
  196. spin_unlock_irqrestore(&rxq->lock, flags);
  197. /* If the pre-allocated buffer pool is dropping low, schedule to
  198. * refill it */
  199. if (rxq->free_count <= RX_LOW_WATERMARK)
  200. queue_work(priv->workqueue, &priv->rx_replenish);
  201. /* If we've added more space for the firmware to place data, tell it.
  202. * Increment device's write pointer in multiples of 8. */
  203. if (write != (rxq->write & ~0x7)) {
  204. spin_lock_irqsave(&rxq->lock, flags);
  205. rxq->need_update = 1;
  206. spin_unlock_irqrestore(&rxq->lock, flags);
  207. ret = iwl_rx_queue_update_write_ptr(priv, rxq);
  208. }
  209. return ret;
  210. }
  211. EXPORT_SYMBOL(iwl_rx_queue_restock);
  212. /**
  213. * iwl_rx_replenish - Move all used packet from rx_used to rx_free
  214. *
  215. * When moving to rx_free an SKB is allocated for the slot.
  216. *
  217. * Also restock the Rx queue via iwl_rx_queue_restock.
  218. * This is called as a scheduled work item (except for during initialization)
  219. */
  220. void iwl_rx_allocate(struct iwl_priv *priv)
  221. {
  222. struct iwl_rx_queue *rxq = &priv->rxq;
  223. struct list_head *element;
  224. struct iwl_rx_mem_buffer *rxb;
  225. unsigned long flags;
  226. spin_lock_irqsave(&rxq->lock, flags);
  227. while (!list_empty(&rxq->rx_used)) {
  228. element = rxq->rx_used.next;
  229. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  230. /* Alloc a new receive buffer */
  231. rxb->skb = alloc_skb(priv->hw_params.rx_buf_size + 256,
  232. __GFP_NOWARN | GFP_ATOMIC);
  233. if (!rxb->skb) {
  234. if (net_ratelimit())
  235. printk(KERN_CRIT DRV_NAME
  236. ": Can not allocate SKB buffers\n");
  237. /* We don't reschedule replenish work here -- we will
  238. * call the restock method and if it still needs
  239. * more buffers it will schedule replenish */
  240. break;
  241. }
  242. priv->alloc_rxb_skb++;
  243. list_del(element);
  244. /* Get physical address of RB/SKB */
  245. rxb->real_dma_addr = pci_map_single(
  246. priv->pci_dev,
  247. rxb->skb->data,
  248. priv->hw_params.rx_buf_size + 256,
  249. PCI_DMA_FROMDEVICE);
  250. /* dma address must be no more than 36 bits */
  251. BUG_ON(rxb->real_dma_addr & ~DMA_BIT_MASK(36));
  252. /* and also 256 byte aligned! */
  253. rxb->aligned_dma_addr = ALIGN(rxb->real_dma_addr, 256);
  254. skb_reserve(rxb->skb, rxb->aligned_dma_addr - rxb->real_dma_addr);
  255. list_add_tail(&rxb->list, &rxq->rx_free);
  256. rxq->free_count++;
  257. }
  258. spin_unlock_irqrestore(&rxq->lock, flags);
  259. }
  260. EXPORT_SYMBOL(iwl_rx_allocate);
  261. void iwl_rx_replenish(struct iwl_priv *priv)
  262. {
  263. unsigned long flags;
  264. iwl_rx_allocate(priv);
  265. spin_lock_irqsave(&priv->lock, flags);
  266. iwl_rx_queue_restock(priv);
  267. spin_unlock_irqrestore(&priv->lock, flags);
  268. }
  269. EXPORT_SYMBOL(iwl_rx_replenish);
  270. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  271. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  272. * This free routine walks the list of POOL entries and if SKB is set to
  273. * non NULL it is unmapped and freed
  274. */
  275. void iwl_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  276. {
  277. int i;
  278. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  279. if (rxq->pool[i].skb != NULL) {
  280. pci_unmap_single(priv->pci_dev,
  281. rxq->pool[i].real_dma_addr,
  282. priv->hw_params.rx_buf_size + 256,
  283. PCI_DMA_FROMDEVICE);
  284. dev_kfree_skb(rxq->pool[i].skb);
  285. }
  286. }
  287. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  288. rxq->dma_addr);
  289. pci_free_consistent(priv->pci_dev, sizeof(struct iwl_rb_status),
  290. rxq->rb_stts, rxq->rb_stts_dma);
  291. rxq->bd = NULL;
  292. rxq->rb_stts = NULL;
  293. }
  294. EXPORT_SYMBOL(iwl_rx_queue_free);
  295. int iwl_rx_queue_alloc(struct iwl_priv *priv)
  296. {
  297. struct iwl_rx_queue *rxq = &priv->rxq;
  298. struct pci_dev *dev = priv->pci_dev;
  299. int i;
  300. spin_lock_init(&rxq->lock);
  301. INIT_LIST_HEAD(&rxq->rx_free);
  302. INIT_LIST_HEAD(&rxq->rx_used);
  303. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  304. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  305. if (!rxq->bd)
  306. goto err_bd;
  307. rxq->rb_stts = pci_alloc_consistent(dev, sizeof(struct iwl_rb_status),
  308. &rxq->rb_stts_dma);
  309. if (!rxq->rb_stts)
  310. goto err_rb;
  311. /* Fill the rx_used queue with _all_ of the Rx buffers */
  312. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  313. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  314. /* Set us so that we have processed and used all buffers, but have
  315. * not restocked the Rx queue with fresh buffers */
  316. rxq->read = rxq->write = 0;
  317. rxq->free_count = 0;
  318. rxq->need_update = 0;
  319. return 0;
  320. err_rb:
  321. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  322. rxq->dma_addr);
  323. err_bd:
  324. return -ENOMEM;
  325. }
  326. EXPORT_SYMBOL(iwl_rx_queue_alloc);
  327. void iwl_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  328. {
  329. unsigned long flags;
  330. int i;
  331. spin_lock_irqsave(&rxq->lock, flags);
  332. INIT_LIST_HEAD(&rxq->rx_free);
  333. INIT_LIST_HEAD(&rxq->rx_used);
  334. /* Fill the rx_used queue with _all_ of the Rx buffers */
  335. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  336. /* In the reset function, these buffers may have been allocated
  337. * to an SKB, so we need to unmap and free potential storage */
  338. if (rxq->pool[i].skb != NULL) {
  339. pci_unmap_single(priv->pci_dev,
  340. rxq->pool[i].real_dma_addr,
  341. priv->hw_params.rx_buf_size + 256,
  342. PCI_DMA_FROMDEVICE);
  343. priv->alloc_rxb_skb--;
  344. dev_kfree_skb(rxq->pool[i].skb);
  345. rxq->pool[i].skb = NULL;
  346. }
  347. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  348. }
  349. /* Set us so that we have processed and used all buffers, but have
  350. * not restocked the Rx queue with fresh buffers */
  351. rxq->read = rxq->write = 0;
  352. rxq->free_count = 0;
  353. spin_unlock_irqrestore(&rxq->lock, flags);
  354. }
  355. EXPORT_SYMBOL(iwl_rx_queue_reset);
  356. int iwl_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  357. {
  358. int ret;
  359. unsigned long flags;
  360. u32 rb_size;
  361. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  362. const u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT why this stalls RX */
  363. spin_lock_irqsave(&priv->lock, flags);
  364. ret = iwl_grab_nic_access(priv);
  365. if (ret) {
  366. spin_unlock_irqrestore(&priv->lock, flags);
  367. return ret;
  368. }
  369. if (priv->cfg->mod_params->amsdu_size_8K)
  370. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  371. else
  372. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  373. /* Stop Rx DMA */
  374. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  375. /* Reset driver's Rx queue write index */
  376. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  377. /* Tell device where to find RBD circular buffer in DRAM */
  378. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  379. (u32)(rxq->dma_addr >> 8));
  380. /* Tell device where in DRAM to update its Rx status */
  381. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  382. rxq->rb_stts_dma >> 4);
  383. /* Enable Rx DMA
  384. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  385. * the credit mechanism in 5000 HW RX FIFO
  386. * Direct rx interrupts to hosts
  387. * Rx buffer size 4 or 8k
  388. * RB timeout 0x10
  389. * 256 RBDs
  390. */
  391. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  392. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  393. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  394. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  395. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  396. rb_size|
  397. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  398. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  399. iwl_release_nic_access(priv);
  400. iwl_write32(priv, CSR_INT_COALESCING, 0x40);
  401. spin_unlock_irqrestore(&priv->lock, flags);
  402. return 0;
  403. }
  404. int iwl_rxq_stop(struct iwl_priv *priv)
  405. {
  406. int ret;
  407. unsigned long flags;
  408. spin_lock_irqsave(&priv->lock, flags);
  409. ret = iwl_grab_nic_access(priv);
  410. if (unlikely(ret)) {
  411. spin_unlock_irqrestore(&priv->lock, flags);
  412. return ret;
  413. }
  414. /* stop Rx DMA */
  415. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  416. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  417. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  418. iwl_release_nic_access(priv);
  419. spin_unlock_irqrestore(&priv->lock, flags);
  420. return 0;
  421. }
  422. EXPORT_SYMBOL(iwl_rxq_stop);
  423. void iwl_rx_missed_beacon_notif(struct iwl_priv *priv,
  424. struct iwl_rx_mem_buffer *rxb)
  425. {
  426. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  427. struct iwl_missed_beacon_notif *missed_beacon;
  428. missed_beacon = &pkt->u.missed_beacon;
  429. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  430. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  431. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  432. le32_to_cpu(missed_beacon->total_missed_becons),
  433. le32_to_cpu(missed_beacon->num_recvd_beacons),
  434. le32_to_cpu(missed_beacon->num_expected_beacons));
  435. if (!test_bit(STATUS_SCANNING, &priv->status))
  436. iwl_init_sensitivity(priv);
  437. }
  438. }
  439. EXPORT_SYMBOL(iwl_rx_missed_beacon_notif);
  440. /* Calculate noise level, based on measurements during network silence just
  441. * before arriving beacon. This measurement can be done only if we know
  442. * exactly when to expect beacons, therefore only when we're associated. */
  443. static void iwl_rx_calc_noise(struct iwl_priv *priv)
  444. {
  445. struct statistics_rx_non_phy *rx_info
  446. = &(priv->statistics.rx.general);
  447. int num_active_rx = 0;
  448. int total_silence = 0;
  449. int bcn_silence_a =
  450. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  451. int bcn_silence_b =
  452. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  453. int bcn_silence_c =
  454. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  455. if (bcn_silence_a) {
  456. total_silence += bcn_silence_a;
  457. num_active_rx++;
  458. }
  459. if (bcn_silence_b) {
  460. total_silence += bcn_silence_b;
  461. num_active_rx++;
  462. }
  463. if (bcn_silence_c) {
  464. total_silence += bcn_silence_c;
  465. num_active_rx++;
  466. }
  467. /* Average among active antennas */
  468. if (num_active_rx)
  469. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  470. else
  471. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  472. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  473. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  474. priv->last_rx_noise);
  475. }
  476. #define REG_RECALIB_PERIOD (60)
  477. void iwl_rx_statistics(struct iwl_priv *priv,
  478. struct iwl_rx_mem_buffer *rxb)
  479. {
  480. int change;
  481. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  482. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  483. (int)sizeof(priv->statistics), pkt->len);
  484. change = ((priv->statistics.general.temperature !=
  485. pkt->u.stats.general.temperature) ||
  486. ((priv->statistics.flag &
  487. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  488. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  489. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  490. set_bit(STATUS_STATISTICS, &priv->status);
  491. /* Reschedule the statistics timer to occur in
  492. * REG_RECALIB_PERIOD seconds to ensure we get a
  493. * thermal update even if the uCode doesn't give
  494. * us one */
  495. mod_timer(&priv->statistics_periodic, jiffies +
  496. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  497. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  498. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  499. iwl_rx_calc_noise(priv);
  500. queue_work(priv->workqueue, &priv->run_time_calib_work);
  501. }
  502. iwl_leds_background(priv);
  503. if (priv->cfg->ops->lib->temperature && change)
  504. priv->cfg->ops->lib->temperature(priv);
  505. }
  506. EXPORT_SYMBOL(iwl_rx_statistics);
  507. #define PERFECT_RSSI (-20) /* dBm */
  508. #define WORST_RSSI (-95) /* dBm */
  509. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  510. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  511. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  512. * about formulas used below. */
  513. static int iwl_calc_sig_qual(int rssi_dbm, int noise_dbm)
  514. {
  515. int sig_qual;
  516. int degradation = PERFECT_RSSI - rssi_dbm;
  517. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  518. * as indicator; formula is (signal dbm - noise dbm).
  519. * SNR at or above 40 is a great signal (100%).
  520. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  521. * Weakest usable signal is usually 10 - 15 dB SNR. */
  522. if (noise_dbm) {
  523. if (rssi_dbm - noise_dbm >= 40)
  524. return 100;
  525. else if (rssi_dbm < noise_dbm)
  526. return 0;
  527. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  528. /* Else use just the signal level.
  529. * This formula is a least squares fit of data points collected and
  530. * compared with a reference system that had a percentage (%) display
  531. * for signal quality. */
  532. } else
  533. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  534. (15 * RSSI_RANGE + 62 * degradation)) /
  535. (RSSI_RANGE * RSSI_RANGE);
  536. if (sig_qual > 100)
  537. sig_qual = 100;
  538. else if (sig_qual < 1)
  539. sig_qual = 0;
  540. return sig_qual;
  541. }
  542. /* Calc max signal level (dBm) among 3 possible receivers */
  543. static inline int iwl_calc_rssi(struct iwl_priv *priv,
  544. struct iwl_rx_phy_res *rx_resp)
  545. {
  546. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  547. }
  548. #ifdef CONFIG_IWLWIFI_DEBUG
  549. /**
  550. * iwl_dbg_report_frame - dump frame to syslog during debug sessions
  551. *
  552. * You may hack this function to show different aspects of received frames,
  553. * including selective frame dumps.
  554. * group100 parameter selects whether to show 1 out of 100 good data frames.
  555. * All beacon and probe response frames are printed.
  556. */
  557. static void iwl_dbg_report_frame(struct iwl_priv *priv,
  558. struct iwl_rx_phy_res *phy_res, u16 length,
  559. struct ieee80211_hdr *header, int group100)
  560. {
  561. u32 to_us;
  562. u32 print_summary = 0;
  563. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  564. u32 hundred = 0;
  565. u32 dataframe = 0;
  566. __le16 fc;
  567. u16 seq_ctl;
  568. u16 channel;
  569. u16 phy_flags;
  570. u32 rate_n_flags;
  571. u32 tsf_low;
  572. int rssi;
  573. if (likely(!(priv->debug_level & IWL_DL_RX)))
  574. return;
  575. /* MAC header */
  576. fc = header->frame_control;
  577. seq_ctl = le16_to_cpu(header->seq_ctrl);
  578. /* metadata */
  579. channel = le16_to_cpu(phy_res->channel);
  580. phy_flags = le16_to_cpu(phy_res->phy_flags);
  581. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  582. /* signal statistics */
  583. rssi = iwl_calc_rssi(priv, phy_res);
  584. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  585. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  586. /* if data frame is to us and all is good,
  587. * (optionally) print summary for only 1 out of every 100 */
  588. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  589. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  590. dataframe = 1;
  591. if (!group100)
  592. print_summary = 1; /* print each frame */
  593. else if (priv->framecnt_to_us < 100) {
  594. priv->framecnt_to_us++;
  595. print_summary = 0;
  596. } else {
  597. priv->framecnt_to_us = 0;
  598. print_summary = 1;
  599. hundred = 1;
  600. }
  601. } else {
  602. /* print summary for all other frames */
  603. print_summary = 1;
  604. }
  605. if (print_summary) {
  606. char *title;
  607. int rate_idx;
  608. u32 bitrate;
  609. if (hundred)
  610. title = "100Frames";
  611. else if (ieee80211_has_retry(fc))
  612. title = "Retry";
  613. else if (ieee80211_is_assoc_resp(fc))
  614. title = "AscRsp";
  615. else if (ieee80211_is_reassoc_resp(fc))
  616. title = "RasRsp";
  617. else if (ieee80211_is_probe_resp(fc)) {
  618. title = "PrbRsp";
  619. print_dump = 1; /* dump frame contents */
  620. } else if (ieee80211_is_beacon(fc)) {
  621. title = "Beacon";
  622. print_dump = 1; /* dump frame contents */
  623. } else if (ieee80211_is_atim(fc))
  624. title = "ATIM";
  625. else if (ieee80211_is_auth(fc))
  626. title = "Auth";
  627. else if (ieee80211_is_deauth(fc))
  628. title = "DeAuth";
  629. else if (ieee80211_is_disassoc(fc))
  630. title = "DisAssoc";
  631. else
  632. title = "Frame";
  633. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  634. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  635. bitrate = 0;
  636. WARN_ON_ONCE(1);
  637. } else {
  638. bitrate = iwl_rates[rate_idx].ieee / 2;
  639. }
  640. /* print frame summary.
  641. * MAC addresses show just the last byte (for brevity),
  642. * but you can hack it to show more, if you'd like to. */
  643. if (dataframe)
  644. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  645. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  646. title, le16_to_cpu(fc), header->addr1[5],
  647. length, rssi, channel, bitrate);
  648. else {
  649. /* src/dst addresses assume managed mode */
  650. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  651. "len=%u, rssi=%d, tim=%lu usec, "
  652. "phy=0x%02x, chnl=%d\n",
  653. title, le16_to_cpu(fc), header->addr1[5],
  654. header->addr3[5], length, rssi,
  655. tsf_low - priv->scan_start_tsf,
  656. phy_flags, channel);
  657. }
  658. }
  659. if (print_dump)
  660. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  661. }
  662. #endif
  663. static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
  664. {
  665. /* 0 - mgmt, 1 - cnt, 2 - data */
  666. int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
  667. priv->rx_stats[idx].cnt++;
  668. priv->rx_stats[idx].bytes += len;
  669. }
  670. /*
  671. * returns non-zero if packet should be dropped
  672. */
  673. static int iwl_set_decrypted_flag(struct iwl_priv *priv,
  674. struct ieee80211_hdr *hdr,
  675. u32 decrypt_res,
  676. struct ieee80211_rx_status *stats)
  677. {
  678. u16 fc = le16_to_cpu(hdr->frame_control);
  679. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  680. return 0;
  681. if (!(fc & IEEE80211_FCTL_PROTECTED))
  682. return 0;
  683. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  684. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  685. case RX_RES_STATUS_SEC_TYPE_TKIP:
  686. /* The uCode has got a bad phase 1 Key, pushes the packet.
  687. * Decryption will be done in SW. */
  688. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  689. RX_RES_STATUS_BAD_KEY_TTAK)
  690. break;
  691. case RX_RES_STATUS_SEC_TYPE_WEP:
  692. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  693. RX_RES_STATUS_BAD_ICV_MIC) {
  694. /* bad ICV, the packet is destroyed since the
  695. * decryption is inplace, drop it */
  696. IWL_DEBUG_RX("Packet destroyed\n");
  697. return -1;
  698. }
  699. case RX_RES_STATUS_SEC_TYPE_CCMP:
  700. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  701. RX_RES_STATUS_DECRYPT_OK) {
  702. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  703. stats->flag |= RX_FLAG_DECRYPTED;
  704. }
  705. break;
  706. default:
  707. break;
  708. }
  709. return 0;
  710. }
  711. static u32 iwl_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  712. {
  713. u32 decrypt_out = 0;
  714. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  715. RX_RES_STATUS_STATION_FOUND)
  716. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  717. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  718. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  719. /* packet was not encrypted */
  720. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  721. RX_RES_STATUS_SEC_TYPE_NONE)
  722. return decrypt_out;
  723. /* packet was encrypted with unknown alg */
  724. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  725. RX_RES_STATUS_SEC_TYPE_ERR)
  726. return decrypt_out;
  727. /* decryption was not done in HW */
  728. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  729. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  730. return decrypt_out;
  731. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  732. case RX_RES_STATUS_SEC_TYPE_CCMP:
  733. /* alg is CCM: check MIC only */
  734. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  735. /* Bad MIC */
  736. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  737. else
  738. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  739. break;
  740. case RX_RES_STATUS_SEC_TYPE_TKIP:
  741. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  742. /* Bad TTAK */
  743. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  744. break;
  745. }
  746. /* fall through if TTAK OK */
  747. default:
  748. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  749. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  750. else
  751. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  752. break;
  753. };
  754. IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
  755. decrypt_in, decrypt_out);
  756. return decrypt_out;
  757. }
  758. static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv,
  759. int include_phy,
  760. struct iwl_rx_mem_buffer *rxb,
  761. struct ieee80211_rx_status *stats)
  762. {
  763. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  764. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  765. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  766. struct ieee80211_hdr *hdr;
  767. u16 len;
  768. __le32 *rx_end;
  769. unsigned int skblen;
  770. u32 ampdu_status;
  771. u32 ampdu_status_legacy;
  772. if (!include_phy && priv->last_phy_res[0])
  773. rx_start = (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  774. if (!rx_start) {
  775. IWL_ERROR("MPDU frame without a PHY data\n");
  776. return;
  777. }
  778. if (include_phy) {
  779. hdr = (struct ieee80211_hdr *)((u8 *) &rx_start[1] +
  780. rx_start->cfg_phy_cnt);
  781. len = le16_to_cpu(rx_start->byte_count);
  782. rx_end = (__le32 *)((u8 *) &pkt->u.raw[0] +
  783. sizeof(struct iwl_rx_phy_res) +
  784. rx_start->cfg_phy_cnt + len);
  785. } else {
  786. struct iwl4965_rx_mpdu_res_start *amsdu =
  787. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  788. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  789. sizeof(struct iwl4965_rx_mpdu_res_start));
  790. len = le16_to_cpu(amsdu->byte_count);
  791. rx_start->byte_count = amsdu->byte_count;
  792. rx_end = (__le32 *) (((u8 *) hdr) + len);
  793. }
  794. ampdu_status = le32_to_cpu(*rx_end);
  795. skblen = ((u8 *) rx_end - (u8 *) &pkt->u.raw[0]) + sizeof(u32);
  796. if (!include_phy) {
  797. /* New status scheme, need to translate */
  798. ampdu_status_legacy = ampdu_status;
  799. ampdu_status = iwl_translate_rx_status(priv, ampdu_status);
  800. }
  801. /* start from MAC */
  802. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  803. skb_put(rxb->skb, len); /* end where data ends */
  804. /* We only process data packets if the interface is open */
  805. if (unlikely(!priv->is_open)) {
  806. IWL_DEBUG_DROP_LIMIT
  807. ("Dropping packet while interface is not open.\n");
  808. return;
  809. }
  810. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  811. /* in case of HW accelerated crypto and bad decryption, drop */
  812. if (!priv->hw_params.sw_crypto &&
  813. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  814. return;
  815. iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
  816. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  817. priv->alloc_rxb_skb--;
  818. rxb->skb = NULL;
  819. }
  820. /* This is necessary only for a number of statistics, see the caller. */
  821. static int iwl_is_network_packet(struct iwl_priv *priv,
  822. struct ieee80211_hdr *header)
  823. {
  824. /* Filter incoming packets to determine if they are targeted toward
  825. * this network, discarding packets coming from ourselves */
  826. switch (priv->iw_mode) {
  827. case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
  828. /* packets to our IBSS update information */
  829. return !compare_ether_addr(header->addr3, priv->bssid);
  830. case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
  831. /* packets to our IBSS update information */
  832. return !compare_ether_addr(header->addr2, priv->bssid);
  833. default:
  834. return 1;
  835. }
  836. }
  837. /* Called for REPLY_RX (legacy ABG frames), or
  838. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  839. void iwl_rx_reply_rx(struct iwl_priv *priv,
  840. struct iwl_rx_mem_buffer *rxb)
  841. {
  842. struct ieee80211_hdr *header;
  843. struct ieee80211_rx_status rx_status;
  844. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  845. /* Use phy data (Rx signal strength, etc.) contained within
  846. * this rx packet for legacy frames,
  847. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  848. int include_phy = (pkt->hdr.cmd == REPLY_RX);
  849. struct iwl_rx_phy_res *rx_start = (include_phy) ?
  850. (struct iwl_rx_phy_res *)&(pkt->u.raw[0]) :
  851. (struct iwl_rx_phy_res *)&priv->last_phy_res[1];
  852. __le32 *rx_end;
  853. unsigned int len = 0;
  854. u16 fc;
  855. u8 network_packet;
  856. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  857. rx_status.freq =
  858. ieee80211_channel_to_frequency(le16_to_cpu(rx_start->channel));
  859. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  860. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  861. rx_status.rate_idx =
  862. iwl_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
  863. if (rx_status.band == IEEE80211_BAND_5GHZ)
  864. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  865. rx_status.flag = 0;
  866. /* TSF isn't reliable. In order to allow smooth user experience,
  867. * this W/A doesn't propagate it to the mac80211 */
  868. /*rx_status.flag |= RX_FLAG_TSFT;*/
  869. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  870. IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
  871. rx_start->cfg_phy_cnt);
  872. return;
  873. }
  874. if (!include_phy) {
  875. if (priv->last_phy_res[0])
  876. rx_start = (struct iwl_rx_phy_res *)
  877. &priv->last_phy_res[1];
  878. else
  879. rx_start = NULL;
  880. }
  881. if (!rx_start) {
  882. IWL_ERROR("MPDU frame without a PHY data\n");
  883. return;
  884. }
  885. if (include_phy) {
  886. header = (struct ieee80211_hdr *)((u8 *) &rx_start[1]
  887. + rx_start->cfg_phy_cnt);
  888. len = le16_to_cpu(rx_start->byte_count);
  889. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  890. sizeof(struct iwl_rx_phy_res) + len);
  891. } else {
  892. struct iwl4965_rx_mpdu_res_start *amsdu =
  893. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  894. header = (void *)(pkt->u.raw +
  895. sizeof(struct iwl4965_rx_mpdu_res_start));
  896. len = le16_to_cpu(amsdu->byte_count);
  897. rx_end = (__le32 *) (pkt->u.raw +
  898. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  899. }
  900. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  901. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  902. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  903. le32_to_cpu(*rx_end));
  904. return;
  905. }
  906. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  907. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  908. rx_status.signal = iwl_calc_rssi(priv, rx_start);
  909. /* Meaningful noise values are available only from beacon statistics,
  910. * which are gathered only when associated, and indicate noise
  911. * only for the associated network channel ...
  912. * Ignore these noise values while scanning (other channels) */
  913. if (iwl_is_associated(priv) &&
  914. !test_bit(STATUS_SCANNING, &priv->status)) {
  915. rx_status.noise = priv->last_rx_noise;
  916. rx_status.qual = iwl_calc_sig_qual(rx_status.signal,
  917. rx_status.noise);
  918. } else {
  919. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  920. rx_status.qual = iwl_calc_sig_qual(rx_status.signal, 0);
  921. }
  922. /* Reset beacon noise level if not associated. */
  923. if (!iwl_is_associated(priv))
  924. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  925. /* Set "1" to report good data frames in groups of 100 */
  926. #ifdef CONFIG_IWLWIFI_DEBUG
  927. if (unlikely(priv->debug_level & IWL_DL_RX))
  928. iwl_dbg_report_frame(priv, rx_start, len, header, 1);
  929. #endif
  930. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  931. rx_status.signal, rx_status.noise, rx_status.signal,
  932. (unsigned long long)rx_status.mactime);
  933. /*
  934. * "antenna number"
  935. *
  936. * It seems that the antenna field in the phy flags value
  937. * is actually a bit field. This is undefined by radiotap,
  938. * it wants an actual antenna number but I always get "7"
  939. * for most legacy frames I receive indicating that the
  940. * same frame was received on all three RX chains.
  941. *
  942. * I think this field should be removed in favor of a
  943. * new 802.11n radiotap field "RX chains" that is defined
  944. * as a bitmask.
  945. */
  946. rx_status.antenna = le16_to_cpu(rx_start->phy_flags &
  947. RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  948. /* set the preamble flag if appropriate */
  949. if (rx_start->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  950. rx_status.flag |= RX_FLAG_SHORTPRE;
  951. /* Take shortcut when only in monitor mode */
  952. if (priv->iw_mode == NL80211_IFTYPE_MONITOR) {
  953. iwl_pass_packet_to_mac80211(priv, include_phy,
  954. rxb, &rx_status);
  955. return;
  956. }
  957. network_packet = iwl_is_network_packet(priv, header);
  958. if (network_packet) {
  959. priv->last_rx_rssi = rx_status.signal;
  960. priv->last_beacon_time = priv->ucode_beacon_time;
  961. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  962. }
  963. fc = le16_to_cpu(header->frame_control);
  964. switch (fc & IEEE80211_FCTL_FTYPE) {
  965. case IEEE80211_FTYPE_MGMT:
  966. case IEEE80211_FTYPE_DATA:
  967. if (priv->iw_mode == NL80211_IFTYPE_AP)
  968. iwl_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  969. header->addr2);
  970. /* fall through */
  971. default:
  972. iwl_pass_packet_to_mac80211(priv, include_phy, rxb,
  973. &rx_status);
  974. break;
  975. }
  976. }
  977. EXPORT_SYMBOL(iwl_rx_reply_rx);
  978. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  979. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  980. void iwl_rx_reply_rx_phy(struct iwl_priv *priv,
  981. struct iwl_rx_mem_buffer *rxb)
  982. {
  983. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  984. priv->last_phy_res[0] = 1;
  985. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  986. sizeof(struct iwl_rx_phy_res));
  987. }
  988. EXPORT_SYMBOL(iwl_rx_reply_rx_phy);