pxa2xx_spi.c 47 KB

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  1. /*
  2. * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/device.h>
  21. #include <linux/ioport.h>
  22. #include <linux/errno.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/spi/pxa2xx_spi.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/spi/spi.h>
  28. #include <linux/workqueue.h>
  29. #include <linux/delay.h>
  30. #include <linux/gpio.h>
  31. #include <linux/slab.h>
  32. #include <asm/io.h>
  33. #include <asm/irq.h>
  34. #include <asm/delay.h>
  35. MODULE_AUTHOR("Stephen Street");
  36. MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
  37. MODULE_LICENSE("GPL");
  38. MODULE_ALIAS("platform:pxa2xx-spi");
  39. #define MAX_BUSES 3
  40. #define TIMOUT_DFLT 1000
  41. #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
  42. #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
  43. #define IS_DMA_ALIGNED(x) ((((u32)(x)) & 0x07) == 0)
  44. #define MAX_DMA_LEN 8191
  45. #define DMA_ALIGNMENT 8
  46. /*
  47. * for testing SSCR1 changes that require SSP restart, basically
  48. * everything except the service and interrupt enables, the pxa270 developer
  49. * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
  50. * list, but the PXA255 dev man says all bits without really meaning the
  51. * service and interrupt enables
  52. */
  53. #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
  54. | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  55. | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
  56. | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
  57. | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
  58. | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59. #define DEFINE_SSP_REG(reg, off) \
  60. static inline u32 read_##reg(void const __iomem *p) \
  61. { return __raw_readl(p + (off)); } \
  62. \
  63. static inline void write_##reg(u32 v, void __iomem *p) \
  64. { __raw_writel(v, p + (off)); }
  65. DEFINE_SSP_REG(SSCR0, 0x00)
  66. DEFINE_SSP_REG(SSCR1, 0x04)
  67. DEFINE_SSP_REG(SSSR, 0x08)
  68. DEFINE_SSP_REG(SSITR, 0x0c)
  69. DEFINE_SSP_REG(SSDR, 0x10)
  70. DEFINE_SSP_REG(SSTO, 0x28)
  71. DEFINE_SSP_REG(SSPSP, 0x2c)
  72. #define START_STATE ((void*)0)
  73. #define RUNNING_STATE ((void*)1)
  74. #define DONE_STATE ((void*)2)
  75. #define ERROR_STATE ((void*)-1)
  76. #define QUEUE_RUNNING 0
  77. #define QUEUE_STOPPED 1
  78. struct driver_data {
  79. /* Driver model hookup */
  80. struct platform_device *pdev;
  81. /* SSP Info */
  82. struct ssp_device *ssp;
  83. /* SPI framework hookup */
  84. enum pxa_ssp_type ssp_type;
  85. struct spi_master *master;
  86. /* PXA hookup */
  87. struct pxa2xx_spi_master *master_info;
  88. /* DMA setup stuff */
  89. int rx_channel;
  90. int tx_channel;
  91. u32 *null_dma_buf;
  92. /* SSP register addresses */
  93. void __iomem *ioaddr;
  94. u32 ssdr_physical;
  95. /* SSP masks*/
  96. u32 dma_cr1;
  97. u32 int_cr1;
  98. u32 clear_sr;
  99. u32 mask_sr;
  100. /* Driver message queue */
  101. struct workqueue_struct *workqueue;
  102. struct work_struct pump_messages;
  103. spinlock_t lock;
  104. struct list_head queue;
  105. int busy;
  106. int run;
  107. /* Message Transfer pump */
  108. struct tasklet_struct pump_transfers;
  109. /* Current message transfer state info */
  110. struct spi_message* cur_msg;
  111. struct spi_transfer* cur_transfer;
  112. struct chip_data *cur_chip;
  113. size_t len;
  114. void *tx;
  115. void *tx_end;
  116. void *rx;
  117. void *rx_end;
  118. int dma_mapped;
  119. dma_addr_t rx_dma;
  120. dma_addr_t tx_dma;
  121. size_t rx_map_len;
  122. size_t tx_map_len;
  123. u8 n_bytes;
  124. u32 dma_width;
  125. int (*write)(struct driver_data *drv_data);
  126. int (*read)(struct driver_data *drv_data);
  127. irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
  128. void (*cs_control)(u32 command);
  129. };
  130. struct chip_data {
  131. u32 cr0;
  132. u32 cr1;
  133. u32 psp;
  134. u32 timeout;
  135. u8 n_bytes;
  136. u32 dma_width;
  137. u32 dma_burst_size;
  138. u32 threshold;
  139. u32 dma_threshold;
  140. u8 enable_dma;
  141. u8 bits_per_word;
  142. u32 speed_hz;
  143. union {
  144. int gpio_cs;
  145. unsigned int frm;
  146. };
  147. int gpio_cs_inverted;
  148. int (*write)(struct driver_data *drv_data);
  149. int (*read)(struct driver_data *drv_data);
  150. void (*cs_control)(u32 command);
  151. };
  152. static void pump_messages(struct work_struct *work);
  153. static void cs_assert(struct driver_data *drv_data)
  154. {
  155. struct chip_data *chip = drv_data->cur_chip;
  156. if (drv_data->ssp_type == CE4100_SSP) {
  157. write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
  158. return;
  159. }
  160. if (chip->cs_control) {
  161. chip->cs_control(PXA2XX_CS_ASSERT);
  162. return;
  163. }
  164. if (gpio_is_valid(chip->gpio_cs))
  165. gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
  166. }
  167. static void cs_deassert(struct driver_data *drv_data)
  168. {
  169. struct chip_data *chip = drv_data->cur_chip;
  170. if (drv_data->ssp_type == CE4100_SSP)
  171. return;
  172. if (chip->cs_control) {
  173. chip->cs_control(PXA2XX_CS_DEASSERT);
  174. return;
  175. }
  176. if (gpio_is_valid(chip->gpio_cs))
  177. gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
  178. }
  179. static void write_SSSR_CS(struct driver_data *drv_data, u32 val)
  180. {
  181. void __iomem *reg = drv_data->ioaddr;
  182. if (drv_data->ssp_type == CE4100_SSP)
  183. val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
  184. write_SSSR(val, reg);
  185. }
  186. static int pxa25x_ssp_comp(struct driver_data *drv_data)
  187. {
  188. if (drv_data->ssp_type == PXA25x_SSP)
  189. return 1;
  190. if (drv_data->ssp_type == CE4100_SSP)
  191. return 1;
  192. return 0;
  193. }
  194. static int flush(struct driver_data *drv_data)
  195. {
  196. unsigned long limit = loops_per_jiffy << 1;
  197. void __iomem *reg = drv_data->ioaddr;
  198. do {
  199. while (read_SSSR(reg) & SSSR_RNE) {
  200. read_SSDR(reg);
  201. }
  202. } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
  203. write_SSSR_CS(drv_data, SSSR_ROR);
  204. return limit;
  205. }
  206. static int null_writer(struct driver_data *drv_data)
  207. {
  208. void __iomem *reg = drv_data->ioaddr;
  209. u8 n_bytes = drv_data->n_bytes;
  210. if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
  211. || (drv_data->tx == drv_data->tx_end))
  212. return 0;
  213. write_SSDR(0, reg);
  214. drv_data->tx += n_bytes;
  215. return 1;
  216. }
  217. static int null_reader(struct driver_data *drv_data)
  218. {
  219. void __iomem *reg = drv_data->ioaddr;
  220. u8 n_bytes = drv_data->n_bytes;
  221. while ((read_SSSR(reg) & SSSR_RNE)
  222. && (drv_data->rx < drv_data->rx_end)) {
  223. read_SSDR(reg);
  224. drv_data->rx += n_bytes;
  225. }
  226. return drv_data->rx == drv_data->rx_end;
  227. }
  228. static int u8_writer(struct driver_data *drv_data)
  229. {
  230. void __iomem *reg = drv_data->ioaddr;
  231. if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
  232. || (drv_data->tx == drv_data->tx_end))
  233. return 0;
  234. write_SSDR(*(u8 *)(drv_data->tx), reg);
  235. ++drv_data->tx;
  236. return 1;
  237. }
  238. static int u8_reader(struct driver_data *drv_data)
  239. {
  240. void __iomem *reg = drv_data->ioaddr;
  241. while ((read_SSSR(reg) & SSSR_RNE)
  242. && (drv_data->rx < drv_data->rx_end)) {
  243. *(u8 *)(drv_data->rx) = read_SSDR(reg);
  244. ++drv_data->rx;
  245. }
  246. return drv_data->rx == drv_data->rx_end;
  247. }
  248. static int u16_writer(struct driver_data *drv_data)
  249. {
  250. void __iomem *reg = drv_data->ioaddr;
  251. if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
  252. || (drv_data->tx == drv_data->tx_end))
  253. return 0;
  254. write_SSDR(*(u16 *)(drv_data->tx), reg);
  255. drv_data->tx += 2;
  256. return 1;
  257. }
  258. static int u16_reader(struct driver_data *drv_data)
  259. {
  260. void __iomem *reg = drv_data->ioaddr;
  261. while ((read_SSSR(reg) & SSSR_RNE)
  262. && (drv_data->rx < drv_data->rx_end)) {
  263. *(u16 *)(drv_data->rx) = read_SSDR(reg);
  264. drv_data->rx += 2;
  265. }
  266. return drv_data->rx == drv_data->rx_end;
  267. }
  268. static int u32_writer(struct driver_data *drv_data)
  269. {
  270. void __iomem *reg = drv_data->ioaddr;
  271. if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
  272. || (drv_data->tx == drv_data->tx_end))
  273. return 0;
  274. write_SSDR(*(u32 *)(drv_data->tx), reg);
  275. drv_data->tx += 4;
  276. return 1;
  277. }
  278. static int u32_reader(struct driver_data *drv_data)
  279. {
  280. void __iomem *reg = drv_data->ioaddr;
  281. while ((read_SSSR(reg) & SSSR_RNE)
  282. && (drv_data->rx < drv_data->rx_end)) {
  283. *(u32 *)(drv_data->rx) = read_SSDR(reg);
  284. drv_data->rx += 4;
  285. }
  286. return drv_data->rx == drv_data->rx_end;
  287. }
  288. static void *next_transfer(struct driver_data *drv_data)
  289. {
  290. struct spi_message *msg = drv_data->cur_msg;
  291. struct spi_transfer *trans = drv_data->cur_transfer;
  292. /* Move to next transfer */
  293. if (trans->transfer_list.next != &msg->transfers) {
  294. drv_data->cur_transfer =
  295. list_entry(trans->transfer_list.next,
  296. struct spi_transfer,
  297. transfer_list);
  298. return RUNNING_STATE;
  299. } else
  300. return DONE_STATE;
  301. }
  302. static int map_dma_buffers(struct driver_data *drv_data)
  303. {
  304. struct spi_message *msg = drv_data->cur_msg;
  305. struct device *dev = &msg->spi->dev;
  306. if (!drv_data->cur_chip->enable_dma)
  307. return 0;
  308. if (msg->is_dma_mapped)
  309. return drv_data->rx_dma && drv_data->tx_dma;
  310. if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
  311. return 0;
  312. /* Modify setup if rx buffer is null */
  313. if (drv_data->rx == NULL) {
  314. *drv_data->null_dma_buf = 0;
  315. drv_data->rx = drv_data->null_dma_buf;
  316. drv_data->rx_map_len = 4;
  317. } else
  318. drv_data->rx_map_len = drv_data->len;
  319. /* Modify setup if tx buffer is null */
  320. if (drv_data->tx == NULL) {
  321. *drv_data->null_dma_buf = 0;
  322. drv_data->tx = drv_data->null_dma_buf;
  323. drv_data->tx_map_len = 4;
  324. } else
  325. drv_data->tx_map_len = drv_data->len;
  326. /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
  327. * so we flush the cache *before* invalidating it, in case
  328. * the tx and rx buffers overlap.
  329. */
  330. drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
  331. drv_data->tx_map_len, DMA_TO_DEVICE);
  332. if (dma_mapping_error(dev, drv_data->tx_dma))
  333. return 0;
  334. /* Stream map the rx buffer */
  335. drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
  336. drv_data->rx_map_len, DMA_FROM_DEVICE);
  337. if (dma_mapping_error(dev, drv_data->rx_dma)) {
  338. dma_unmap_single(dev, drv_data->tx_dma,
  339. drv_data->tx_map_len, DMA_TO_DEVICE);
  340. return 0;
  341. }
  342. return 1;
  343. }
  344. static void unmap_dma_buffers(struct driver_data *drv_data)
  345. {
  346. struct device *dev;
  347. if (!drv_data->dma_mapped)
  348. return;
  349. if (!drv_data->cur_msg->is_dma_mapped) {
  350. dev = &drv_data->cur_msg->spi->dev;
  351. dma_unmap_single(dev, drv_data->rx_dma,
  352. drv_data->rx_map_len, DMA_FROM_DEVICE);
  353. dma_unmap_single(dev, drv_data->tx_dma,
  354. drv_data->tx_map_len, DMA_TO_DEVICE);
  355. }
  356. drv_data->dma_mapped = 0;
  357. }
  358. /* caller already set message->status; dma and pio irqs are blocked */
  359. static void giveback(struct driver_data *drv_data)
  360. {
  361. struct spi_transfer* last_transfer;
  362. unsigned long flags;
  363. struct spi_message *msg;
  364. spin_lock_irqsave(&drv_data->lock, flags);
  365. msg = drv_data->cur_msg;
  366. drv_data->cur_msg = NULL;
  367. drv_data->cur_transfer = NULL;
  368. queue_work(drv_data->workqueue, &drv_data->pump_messages);
  369. spin_unlock_irqrestore(&drv_data->lock, flags);
  370. last_transfer = list_entry(msg->transfers.prev,
  371. struct spi_transfer,
  372. transfer_list);
  373. /* Delay if requested before any change in chip select */
  374. if (last_transfer->delay_usecs)
  375. udelay(last_transfer->delay_usecs);
  376. /* Drop chip select UNLESS cs_change is true or we are returning
  377. * a message with an error, or next message is for another chip
  378. */
  379. if (!last_transfer->cs_change)
  380. cs_deassert(drv_data);
  381. else {
  382. struct spi_message *next_msg;
  383. /* Holding of cs was hinted, but we need to make sure
  384. * the next message is for the same chip. Don't waste
  385. * time with the following tests unless this was hinted.
  386. *
  387. * We cannot postpone this until pump_messages, because
  388. * after calling msg->complete (below) the driver that
  389. * sent the current message could be unloaded, which
  390. * could invalidate the cs_control() callback...
  391. */
  392. /* get a pointer to the next message, if any */
  393. spin_lock_irqsave(&drv_data->lock, flags);
  394. if (list_empty(&drv_data->queue))
  395. next_msg = NULL;
  396. else
  397. next_msg = list_entry(drv_data->queue.next,
  398. struct spi_message, queue);
  399. spin_unlock_irqrestore(&drv_data->lock, flags);
  400. /* see if the next and current messages point
  401. * to the same chip
  402. */
  403. if (next_msg && next_msg->spi != msg->spi)
  404. next_msg = NULL;
  405. if (!next_msg || msg->state == ERROR_STATE)
  406. cs_deassert(drv_data);
  407. }
  408. msg->state = NULL;
  409. if (msg->complete)
  410. msg->complete(msg->context);
  411. drv_data->cur_chip = NULL;
  412. }
  413. static int wait_ssp_rx_stall(void const __iomem *ioaddr)
  414. {
  415. unsigned long limit = loops_per_jiffy << 1;
  416. while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
  417. cpu_relax();
  418. return limit;
  419. }
  420. static int wait_dma_channel_stop(int channel)
  421. {
  422. unsigned long limit = loops_per_jiffy << 1;
  423. while (!(DCSR(channel) & DCSR_STOPSTATE) && --limit)
  424. cpu_relax();
  425. return limit;
  426. }
  427. static void dma_error_stop(struct driver_data *drv_data, const char *msg)
  428. {
  429. void __iomem *reg = drv_data->ioaddr;
  430. /* Stop and reset */
  431. DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
  432. DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
  433. write_SSSR_CS(drv_data, drv_data->clear_sr);
  434. write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
  435. if (!pxa25x_ssp_comp(drv_data))
  436. write_SSTO(0, reg);
  437. flush(drv_data);
  438. write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
  439. unmap_dma_buffers(drv_data);
  440. dev_err(&drv_data->pdev->dev, "%s\n", msg);
  441. drv_data->cur_msg->state = ERROR_STATE;
  442. tasklet_schedule(&drv_data->pump_transfers);
  443. }
  444. static void dma_transfer_complete(struct driver_data *drv_data)
  445. {
  446. void __iomem *reg = drv_data->ioaddr;
  447. struct spi_message *msg = drv_data->cur_msg;
  448. /* Clear and disable interrupts on SSP and DMA channels*/
  449. write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
  450. write_SSSR_CS(drv_data, drv_data->clear_sr);
  451. DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
  452. DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
  453. if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
  454. dev_err(&drv_data->pdev->dev,
  455. "dma_handler: dma rx channel stop failed\n");
  456. if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
  457. dev_err(&drv_data->pdev->dev,
  458. "dma_transfer: ssp rx stall failed\n");
  459. unmap_dma_buffers(drv_data);
  460. /* update the buffer pointer for the amount completed in dma */
  461. drv_data->rx += drv_data->len -
  462. (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
  463. /* read trailing data from fifo, it does not matter how many
  464. * bytes are in the fifo just read until buffer is full
  465. * or fifo is empty, which ever occurs first */
  466. drv_data->read(drv_data);
  467. /* return count of what was actually read */
  468. msg->actual_length += drv_data->len -
  469. (drv_data->rx_end - drv_data->rx);
  470. /* Transfer delays and chip select release are
  471. * handled in pump_transfers or giveback
  472. */
  473. /* Move to next transfer */
  474. msg->state = next_transfer(drv_data);
  475. /* Schedule transfer tasklet */
  476. tasklet_schedule(&drv_data->pump_transfers);
  477. }
  478. static void dma_handler(int channel, void *data)
  479. {
  480. struct driver_data *drv_data = data;
  481. u32 irq_status = DCSR(channel) & DMA_INT_MASK;
  482. if (irq_status & DCSR_BUSERR) {
  483. if (channel == drv_data->tx_channel)
  484. dma_error_stop(drv_data,
  485. "dma_handler: "
  486. "bad bus address on tx channel");
  487. else
  488. dma_error_stop(drv_data,
  489. "dma_handler: "
  490. "bad bus address on rx channel");
  491. return;
  492. }
  493. /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
  494. if ((channel == drv_data->tx_channel)
  495. && (irq_status & DCSR_ENDINTR)
  496. && (drv_data->ssp_type == PXA25x_SSP)) {
  497. /* Wait for rx to stall */
  498. if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
  499. dev_err(&drv_data->pdev->dev,
  500. "dma_handler: ssp rx stall failed\n");
  501. /* finish this transfer, start the next */
  502. dma_transfer_complete(drv_data);
  503. }
  504. }
  505. static irqreturn_t dma_transfer(struct driver_data *drv_data)
  506. {
  507. u32 irq_status;
  508. void __iomem *reg = drv_data->ioaddr;
  509. irq_status = read_SSSR(reg) & drv_data->mask_sr;
  510. if (irq_status & SSSR_ROR) {
  511. dma_error_stop(drv_data, "dma_transfer: fifo overrun");
  512. return IRQ_HANDLED;
  513. }
  514. /* Check for false positive timeout */
  515. if ((irq_status & SSSR_TINT)
  516. && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
  517. write_SSSR(SSSR_TINT, reg);
  518. return IRQ_HANDLED;
  519. }
  520. if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
  521. /* Clear and disable timeout interrupt, do the rest in
  522. * dma_transfer_complete */
  523. if (!pxa25x_ssp_comp(drv_data))
  524. write_SSTO(0, reg);
  525. /* finish this transfer, start the next */
  526. dma_transfer_complete(drv_data);
  527. return IRQ_HANDLED;
  528. }
  529. /* Opps problem detected */
  530. return IRQ_NONE;
  531. }
  532. static void int_error_stop(struct driver_data *drv_data, const char* msg)
  533. {
  534. void __iomem *reg = drv_data->ioaddr;
  535. /* Stop and reset SSP */
  536. write_SSSR_CS(drv_data, drv_data->clear_sr);
  537. write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
  538. if (!pxa25x_ssp_comp(drv_data))
  539. write_SSTO(0, reg);
  540. flush(drv_data);
  541. write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
  542. dev_err(&drv_data->pdev->dev, "%s\n", msg);
  543. drv_data->cur_msg->state = ERROR_STATE;
  544. tasklet_schedule(&drv_data->pump_transfers);
  545. }
  546. static void int_transfer_complete(struct driver_data *drv_data)
  547. {
  548. void __iomem *reg = drv_data->ioaddr;
  549. /* Stop SSP */
  550. write_SSSR_CS(drv_data, drv_data->clear_sr);
  551. write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
  552. if (!pxa25x_ssp_comp(drv_data))
  553. write_SSTO(0, reg);
  554. /* Update total byte transfered return count actual bytes read */
  555. drv_data->cur_msg->actual_length += drv_data->len -
  556. (drv_data->rx_end - drv_data->rx);
  557. /* Transfer delays and chip select release are
  558. * handled in pump_transfers or giveback
  559. */
  560. /* Move to next transfer */
  561. drv_data->cur_msg->state = next_transfer(drv_data);
  562. /* Schedule transfer tasklet */
  563. tasklet_schedule(&drv_data->pump_transfers);
  564. }
  565. static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
  566. {
  567. void __iomem *reg = drv_data->ioaddr;
  568. u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
  569. drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
  570. u32 irq_status = read_SSSR(reg) & irq_mask;
  571. if (irq_status & SSSR_ROR) {
  572. int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
  573. return IRQ_HANDLED;
  574. }
  575. if (irq_status & SSSR_TINT) {
  576. write_SSSR(SSSR_TINT, reg);
  577. if (drv_data->read(drv_data)) {
  578. int_transfer_complete(drv_data);
  579. return IRQ_HANDLED;
  580. }
  581. }
  582. /* Drain rx fifo, Fill tx fifo and prevent overruns */
  583. do {
  584. if (drv_data->read(drv_data)) {
  585. int_transfer_complete(drv_data);
  586. return IRQ_HANDLED;
  587. }
  588. } while (drv_data->write(drv_data));
  589. if (drv_data->read(drv_data)) {
  590. int_transfer_complete(drv_data);
  591. return IRQ_HANDLED;
  592. }
  593. if (drv_data->tx == drv_data->tx_end) {
  594. write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
  595. /* PXA25x_SSP has no timeout, read trailing bytes */
  596. if (pxa25x_ssp_comp(drv_data)) {
  597. if (!wait_ssp_rx_stall(reg))
  598. {
  599. int_error_stop(drv_data, "interrupt_transfer: "
  600. "rx stall failed");
  601. return IRQ_HANDLED;
  602. }
  603. if (!drv_data->read(drv_data))
  604. {
  605. int_error_stop(drv_data,
  606. "interrupt_transfer: "
  607. "trailing byte read failed");
  608. return IRQ_HANDLED;
  609. }
  610. int_transfer_complete(drv_data);
  611. }
  612. }
  613. /* We did something */
  614. return IRQ_HANDLED;
  615. }
  616. static irqreturn_t ssp_int(int irq, void *dev_id)
  617. {
  618. struct driver_data *drv_data = dev_id;
  619. void __iomem *reg = drv_data->ioaddr;
  620. u32 sccr1_reg = read_SSCR1(reg);
  621. u32 mask = drv_data->mask_sr;
  622. u32 status;
  623. status = read_SSSR(reg);
  624. /* Ignore possible writes if we don't need to write */
  625. if (!(sccr1_reg & SSCR1_TIE))
  626. mask &= ~SSSR_TFS;
  627. if (!(status & mask))
  628. return IRQ_NONE;
  629. if (!drv_data->cur_msg) {
  630. write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
  631. write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
  632. if (!pxa25x_ssp_comp(drv_data))
  633. write_SSTO(0, reg);
  634. write_SSSR_CS(drv_data, drv_data->clear_sr);
  635. dev_err(&drv_data->pdev->dev, "bad message state "
  636. "in interrupt handler\n");
  637. /* Never fail */
  638. return IRQ_HANDLED;
  639. }
  640. return drv_data->transfer_handler(drv_data);
  641. }
  642. static int set_dma_burst_and_threshold(struct chip_data *chip,
  643. struct spi_device *spi,
  644. u8 bits_per_word, u32 *burst_code,
  645. u32 *threshold)
  646. {
  647. struct pxa2xx_spi_chip *chip_info =
  648. (struct pxa2xx_spi_chip *)spi->controller_data;
  649. int bytes_per_word;
  650. int burst_bytes;
  651. int thresh_words;
  652. int req_burst_size;
  653. int retval = 0;
  654. /* Set the threshold (in registers) to equal the same amount of data
  655. * as represented by burst size (in bytes). The computation below
  656. * is (burst_size rounded up to nearest 8 byte, word or long word)
  657. * divided by (bytes/register); the tx threshold is the inverse of
  658. * the rx, so that there will always be enough data in the rx fifo
  659. * to satisfy a burst, and there will always be enough space in the
  660. * tx fifo to accept a burst (a tx burst will overwrite the fifo if
  661. * there is not enough space), there must always remain enough empty
  662. * space in the rx fifo for any data loaded to the tx fifo.
  663. * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
  664. * will be 8, or half the fifo;
  665. * The threshold can only be set to 2, 4 or 8, but not 16, because
  666. * to burst 16 to the tx fifo, the fifo would have to be empty;
  667. * however, the minimum fifo trigger level is 1, and the tx will
  668. * request service when the fifo is at this level, with only 15 spaces.
  669. */
  670. /* find bytes/word */
  671. if (bits_per_word <= 8)
  672. bytes_per_word = 1;
  673. else if (bits_per_word <= 16)
  674. bytes_per_word = 2;
  675. else
  676. bytes_per_word = 4;
  677. /* use struct pxa2xx_spi_chip->dma_burst_size if available */
  678. if (chip_info)
  679. req_burst_size = chip_info->dma_burst_size;
  680. else {
  681. switch (chip->dma_burst_size) {
  682. default:
  683. /* if the default burst size is not set,
  684. * do it now */
  685. chip->dma_burst_size = DCMD_BURST8;
  686. case DCMD_BURST8:
  687. req_burst_size = 8;
  688. break;
  689. case DCMD_BURST16:
  690. req_burst_size = 16;
  691. break;
  692. case DCMD_BURST32:
  693. req_burst_size = 32;
  694. break;
  695. }
  696. }
  697. if (req_burst_size <= 8) {
  698. *burst_code = DCMD_BURST8;
  699. burst_bytes = 8;
  700. } else if (req_burst_size <= 16) {
  701. if (bytes_per_word == 1) {
  702. /* don't burst more than 1/2 the fifo */
  703. *burst_code = DCMD_BURST8;
  704. burst_bytes = 8;
  705. retval = 1;
  706. } else {
  707. *burst_code = DCMD_BURST16;
  708. burst_bytes = 16;
  709. }
  710. } else {
  711. if (bytes_per_word == 1) {
  712. /* don't burst more than 1/2 the fifo */
  713. *burst_code = DCMD_BURST8;
  714. burst_bytes = 8;
  715. retval = 1;
  716. } else if (bytes_per_word == 2) {
  717. /* don't burst more than 1/2 the fifo */
  718. *burst_code = DCMD_BURST16;
  719. burst_bytes = 16;
  720. retval = 1;
  721. } else {
  722. *burst_code = DCMD_BURST32;
  723. burst_bytes = 32;
  724. }
  725. }
  726. thresh_words = burst_bytes / bytes_per_word;
  727. /* thresh_words will be between 2 and 8 */
  728. *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
  729. | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
  730. return retval;
  731. }
  732. static unsigned int ssp_get_clk_div(struct ssp_device *ssp, int rate)
  733. {
  734. unsigned long ssp_clk = clk_get_rate(ssp->clk);
  735. if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
  736. return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
  737. else
  738. return ((ssp_clk / rate - 1) & 0xfff) << 8;
  739. }
  740. static void pump_transfers(unsigned long data)
  741. {
  742. struct driver_data *drv_data = (struct driver_data *)data;
  743. struct spi_message *message = NULL;
  744. struct spi_transfer *transfer = NULL;
  745. struct spi_transfer *previous = NULL;
  746. struct chip_data *chip = NULL;
  747. struct ssp_device *ssp = drv_data->ssp;
  748. void __iomem *reg = drv_data->ioaddr;
  749. u32 clk_div = 0;
  750. u8 bits = 0;
  751. u32 speed = 0;
  752. u32 cr0;
  753. u32 cr1;
  754. u32 dma_thresh = drv_data->cur_chip->dma_threshold;
  755. u32 dma_burst = drv_data->cur_chip->dma_burst_size;
  756. /* Get current state information */
  757. message = drv_data->cur_msg;
  758. transfer = drv_data->cur_transfer;
  759. chip = drv_data->cur_chip;
  760. /* Handle for abort */
  761. if (message->state == ERROR_STATE) {
  762. message->status = -EIO;
  763. giveback(drv_data);
  764. return;
  765. }
  766. /* Handle end of message */
  767. if (message->state == DONE_STATE) {
  768. message->status = 0;
  769. giveback(drv_data);
  770. return;
  771. }
  772. /* Delay if requested at end of transfer before CS change */
  773. if (message->state == RUNNING_STATE) {
  774. previous = list_entry(transfer->transfer_list.prev,
  775. struct spi_transfer,
  776. transfer_list);
  777. if (previous->delay_usecs)
  778. udelay(previous->delay_usecs);
  779. /* Drop chip select only if cs_change is requested */
  780. if (previous->cs_change)
  781. cs_deassert(drv_data);
  782. }
  783. /* Check for transfers that need multiple DMA segments */
  784. if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
  785. /* reject already-mapped transfers; PIO won't always work */
  786. if (message->is_dma_mapped
  787. || transfer->rx_dma || transfer->tx_dma) {
  788. dev_err(&drv_data->pdev->dev,
  789. "pump_transfers: mapped transfer length "
  790. "of %u is greater than %d\n",
  791. transfer->len, MAX_DMA_LEN);
  792. message->status = -EINVAL;
  793. giveback(drv_data);
  794. return;
  795. }
  796. /* warn ... we force this to PIO mode */
  797. if (printk_ratelimit())
  798. dev_warn(&message->spi->dev, "pump_transfers: "
  799. "DMA disabled for transfer length %ld "
  800. "greater than %d\n",
  801. (long)drv_data->len, MAX_DMA_LEN);
  802. }
  803. /* Setup the transfer state based on the type of transfer */
  804. if (flush(drv_data) == 0) {
  805. dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
  806. message->status = -EIO;
  807. giveback(drv_data);
  808. return;
  809. }
  810. drv_data->n_bytes = chip->n_bytes;
  811. drv_data->dma_width = chip->dma_width;
  812. drv_data->tx = (void *)transfer->tx_buf;
  813. drv_data->tx_end = drv_data->tx + transfer->len;
  814. drv_data->rx = transfer->rx_buf;
  815. drv_data->rx_end = drv_data->rx + transfer->len;
  816. drv_data->rx_dma = transfer->rx_dma;
  817. drv_data->tx_dma = transfer->tx_dma;
  818. drv_data->len = transfer->len & DCMD_LENGTH;
  819. drv_data->write = drv_data->tx ? chip->write : null_writer;
  820. drv_data->read = drv_data->rx ? chip->read : null_reader;
  821. /* Change speed and bit per word on a per transfer */
  822. cr0 = chip->cr0;
  823. if (transfer->speed_hz || transfer->bits_per_word) {
  824. bits = chip->bits_per_word;
  825. speed = chip->speed_hz;
  826. if (transfer->speed_hz)
  827. speed = transfer->speed_hz;
  828. if (transfer->bits_per_word)
  829. bits = transfer->bits_per_word;
  830. clk_div = ssp_get_clk_div(ssp, speed);
  831. if (bits <= 8) {
  832. drv_data->n_bytes = 1;
  833. drv_data->dma_width = DCMD_WIDTH1;
  834. drv_data->read = drv_data->read != null_reader ?
  835. u8_reader : null_reader;
  836. drv_data->write = drv_data->write != null_writer ?
  837. u8_writer : null_writer;
  838. } else if (bits <= 16) {
  839. drv_data->n_bytes = 2;
  840. drv_data->dma_width = DCMD_WIDTH2;
  841. drv_data->read = drv_data->read != null_reader ?
  842. u16_reader : null_reader;
  843. drv_data->write = drv_data->write != null_writer ?
  844. u16_writer : null_writer;
  845. } else if (bits <= 32) {
  846. drv_data->n_bytes = 4;
  847. drv_data->dma_width = DCMD_WIDTH4;
  848. drv_data->read = drv_data->read != null_reader ?
  849. u32_reader : null_reader;
  850. drv_data->write = drv_data->write != null_writer ?
  851. u32_writer : null_writer;
  852. }
  853. /* if bits/word is changed in dma mode, then must check the
  854. * thresholds and burst also */
  855. if (chip->enable_dma) {
  856. if (set_dma_burst_and_threshold(chip, message->spi,
  857. bits, &dma_burst,
  858. &dma_thresh))
  859. if (printk_ratelimit())
  860. dev_warn(&message->spi->dev,
  861. "pump_transfers: "
  862. "DMA burst size reduced to "
  863. "match bits_per_word\n");
  864. }
  865. cr0 = clk_div
  866. | SSCR0_Motorola
  867. | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
  868. | SSCR0_SSE
  869. | (bits > 16 ? SSCR0_EDSS : 0);
  870. }
  871. message->state = RUNNING_STATE;
  872. /* Try to map dma buffer and do a dma transfer if successful, but
  873. * only if the length is non-zero and less than MAX_DMA_LEN.
  874. *
  875. * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
  876. * of PIO instead. Care is needed above because the transfer may
  877. * have have been passed with buffers that are already dma mapped.
  878. * A zero-length transfer in PIO mode will not try to write/read
  879. * to/from the buffers
  880. *
  881. * REVISIT large transfers are exactly where we most want to be
  882. * using DMA. If this happens much, split those transfers into
  883. * multiple DMA segments rather than forcing PIO.
  884. */
  885. drv_data->dma_mapped = 0;
  886. if (drv_data->len > 0 && drv_data->len <= MAX_DMA_LEN)
  887. drv_data->dma_mapped = map_dma_buffers(drv_data);
  888. if (drv_data->dma_mapped) {
  889. /* Ensure we have the correct interrupt handler */
  890. drv_data->transfer_handler = dma_transfer;
  891. /* Setup rx DMA Channel */
  892. DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
  893. DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
  894. DTADR(drv_data->rx_channel) = drv_data->rx_dma;
  895. if (drv_data->rx == drv_data->null_dma_buf)
  896. /* No target address increment */
  897. DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
  898. | drv_data->dma_width
  899. | dma_burst
  900. | drv_data->len;
  901. else
  902. DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
  903. | DCMD_FLOWSRC
  904. | drv_data->dma_width
  905. | dma_burst
  906. | drv_data->len;
  907. /* Setup tx DMA Channel */
  908. DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
  909. DSADR(drv_data->tx_channel) = drv_data->tx_dma;
  910. DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
  911. if (drv_data->tx == drv_data->null_dma_buf)
  912. /* No source address increment */
  913. DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
  914. | drv_data->dma_width
  915. | dma_burst
  916. | drv_data->len;
  917. else
  918. DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
  919. | DCMD_FLOWTRG
  920. | drv_data->dma_width
  921. | dma_burst
  922. | drv_data->len;
  923. /* Enable dma end irqs on SSP to detect end of transfer */
  924. if (drv_data->ssp_type == PXA25x_SSP)
  925. DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
  926. /* Clear status and start DMA engine */
  927. cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
  928. write_SSSR(drv_data->clear_sr, reg);
  929. DCSR(drv_data->rx_channel) |= DCSR_RUN;
  930. DCSR(drv_data->tx_channel) |= DCSR_RUN;
  931. } else {
  932. /* Ensure we have the correct interrupt handler */
  933. drv_data->transfer_handler = interrupt_transfer;
  934. /* Clear status */
  935. cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
  936. write_SSSR_CS(drv_data, drv_data->clear_sr);
  937. }
  938. /* see if we need to reload the config registers */
  939. if ((read_SSCR0(reg) != cr0)
  940. || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
  941. (cr1 & SSCR1_CHANGE_MASK)) {
  942. /* stop the SSP, and update the other bits */
  943. write_SSCR0(cr0 & ~SSCR0_SSE, reg);
  944. if (!pxa25x_ssp_comp(drv_data))
  945. write_SSTO(chip->timeout, reg);
  946. /* first set CR1 without interrupt and service enables */
  947. write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
  948. /* restart the SSP */
  949. write_SSCR0(cr0, reg);
  950. } else {
  951. if (!pxa25x_ssp_comp(drv_data))
  952. write_SSTO(chip->timeout, reg);
  953. }
  954. cs_assert(drv_data);
  955. /* after chip select, release the data by enabling service
  956. * requests and interrupts, without changing any mode bits */
  957. write_SSCR1(cr1, reg);
  958. }
  959. static void pump_messages(struct work_struct *work)
  960. {
  961. struct driver_data *drv_data =
  962. container_of(work, struct driver_data, pump_messages);
  963. unsigned long flags;
  964. /* Lock queue and check for queue work */
  965. spin_lock_irqsave(&drv_data->lock, flags);
  966. if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
  967. drv_data->busy = 0;
  968. spin_unlock_irqrestore(&drv_data->lock, flags);
  969. return;
  970. }
  971. /* Make sure we are not already running a message */
  972. if (drv_data->cur_msg) {
  973. spin_unlock_irqrestore(&drv_data->lock, flags);
  974. return;
  975. }
  976. /* Extract head of queue */
  977. drv_data->cur_msg = list_entry(drv_data->queue.next,
  978. struct spi_message, queue);
  979. list_del_init(&drv_data->cur_msg->queue);
  980. /* Initial message state*/
  981. drv_data->cur_msg->state = START_STATE;
  982. drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
  983. struct spi_transfer,
  984. transfer_list);
  985. /* prepare to setup the SSP, in pump_transfers, using the per
  986. * chip configuration */
  987. drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
  988. /* Mark as busy and launch transfers */
  989. tasklet_schedule(&drv_data->pump_transfers);
  990. drv_data->busy = 1;
  991. spin_unlock_irqrestore(&drv_data->lock, flags);
  992. }
  993. static int transfer(struct spi_device *spi, struct spi_message *msg)
  994. {
  995. struct driver_data *drv_data = spi_master_get_devdata(spi->master);
  996. unsigned long flags;
  997. spin_lock_irqsave(&drv_data->lock, flags);
  998. if (drv_data->run == QUEUE_STOPPED) {
  999. spin_unlock_irqrestore(&drv_data->lock, flags);
  1000. return -ESHUTDOWN;
  1001. }
  1002. msg->actual_length = 0;
  1003. msg->status = -EINPROGRESS;
  1004. msg->state = START_STATE;
  1005. list_add_tail(&msg->queue, &drv_data->queue);
  1006. if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
  1007. queue_work(drv_data->workqueue, &drv_data->pump_messages);
  1008. spin_unlock_irqrestore(&drv_data->lock, flags);
  1009. return 0;
  1010. }
  1011. static int setup_cs(struct spi_device *spi, struct chip_data *chip,
  1012. struct pxa2xx_spi_chip *chip_info)
  1013. {
  1014. int err = 0;
  1015. if (chip == NULL || chip_info == NULL)
  1016. return 0;
  1017. /* NOTE: setup() can be called multiple times, possibly with
  1018. * different chip_info, release previously requested GPIO
  1019. */
  1020. if (gpio_is_valid(chip->gpio_cs))
  1021. gpio_free(chip->gpio_cs);
  1022. /* If (*cs_control) is provided, ignore GPIO chip select */
  1023. if (chip_info->cs_control) {
  1024. chip->cs_control = chip_info->cs_control;
  1025. return 0;
  1026. }
  1027. if (gpio_is_valid(chip_info->gpio_cs)) {
  1028. err = gpio_request(chip_info->gpio_cs, "SPI_CS");
  1029. if (err) {
  1030. dev_err(&spi->dev, "failed to request chip select "
  1031. "GPIO%d\n", chip_info->gpio_cs);
  1032. return err;
  1033. }
  1034. chip->gpio_cs = chip_info->gpio_cs;
  1035. chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
  1036. err = gpio_direction_output(chip->gpio_cs,
  1037. !chip->gpio_cs_inverted);
  1038. }
  1039. return err;
  1040. }
  1041. static int setup(struct spi_device *spi)
  1042. {
  1043. struct pxa2xx_spi_chip *chip_info = NULL;
  1044. struct chip_data *chip;
  1045. struct driver_data *drv_data = spi_master_get_devdata(spi->master);
  1046. struct ssp_device *ssp = drv_data->ssp;
  1047. unsigned int clk_div;
  1048. uint tx_thres = TX_THRESH_DFLT;
  1049. uint rx_thres = RX_THRESH_DFLT;
  1050. if (!pxa25x_ssp_comp(drv_data)
  1051. && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
  1052. dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
  1053. "b/w not 4-32 for type non-PXA25x_SSP\n",
  1054. drv_data->ssp_type, spi->bits_per_word);
  1055. return -EINVAL;
  1056. } else if (pxa25x_ssp_comp(drv_data)
  1057. && (spi->bits_per_word < 4
  1058. || spi->bits_per_word > 16)) {
  1059. dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
  1060. "b/w not 4-16 for type PXA25x_SSP\n",
  1061. drv_data->ssp_type, spi->bits_per_word);
  1062. return -EINVAL;
  1063. }
  1064. /* Only alloc on first setup */
  1065. chip = spi_get_ctldata(spi);
  1066. if (!chip) {
  1067. chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
  1068. if (!chip) {
  1069. dev_err(&spi->dev,
  1070. "failed setup: can't allocate chip data\n");
  1071. return -ENOMEM;
  1072. }
  1073. if (drv_data->ssp_type == CE4100_SSP) {
  1074. if (spi->chip_select > 4) {
  1075. dev_err(&spi->dev, "failed setup: "
  1076. "cs number must not be > 4.\n");
  1077. kfree(chip);
  1078. return -EINVAL;
  1079. }
  1080. chip->frm = spi->chip_select;
  1081. } else
  1082. chip->gpio_cs = -1;
  1083. chip->enable_dma = 0;
  1084. chip->timeout = TIMOUT_DFLT;
  1085. chip->dma_burst_size = drv_data->master_info->enable_dma ?
  1086. DCMD_BURST8 : 0;
  1087. }
  1088. /* protocol drivers may change the chip settings, so...
  1089. * if chip_info exists, use it */
  1090. chip_info = spi->controller_data;
  1091. /* chip_info isn't always needed */
  1092. chip->cr1 = 0;
  1093. if (chip_info) {
  1094. if (chip_info->timeout)
  1095. chip->timeout = chip_info->timeout;
  1096. if (chip_info->tx_threshold)
  1097. tx_thres = chip_info->tx_threshold;
  1098. if (chip_info->rx_threshold)
  1099. rx_thres = chip_info->rx_threshold;
  1100. chip->enable_dma = drv_data->master_info->enable_dma;
  1101. chip->dma_threshold = 0;
  1102. if (chip_info->enable_loopback)
  1103. chip->cr1 = SSCR1_LBM;
  1104. }
  1105. chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
  1106. (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
  1107. /* set dma burst and threshold outside of chip_info path so that if
  1108. * chip_info goes away after setting chip->enable_dma, the
  1109. * burst and threshold can still respond to changes in bits_per_word */
  1110. if (chip->enable_dma) {
  1111. /* set up legal burst and threshold for dma */
  1112. if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
  1113. &chip->dma_burst_size,
  1114. &chip->dma_threshold)) {
  1115. dev_warn(&spi->dev, "in setup: DMA burst size reduced "
  1116. "to match bits_per_word\n");
  1117. }
  1118. }
  1119. clk_div = ssp_get_clk_div(ssp, spi->max_speed_hz);
  1120. chip->speed_hz = spi->max_speed_hz;
  1121. chip->cr0 = clk_div
  1122. | SSCR0_Motorola
  1123. | SSCR0_DataSize(spi->bits_per_word > 16 ?
  1124. spi->bits_per_word - 16 : spi->bits_per_word)
  1125. | SSCR0_SSE
  1126. | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
  1127. chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
  1128. chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
  1129. | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
  1130. /* NOTE: PXA25x_SSP _could_ use external clocking ... */
  1131. if (!pxa25x_ssp_comp(drv_data))
  1132. dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
  1133. clk_get_rate(ssp->clk)
  1134. / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
  1135. chip->enable_dma ? "DMA" : "PIO");
  1136. else
  1137. dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
  1138. clk_get_rate(ssp->clk) / 2
  1139. / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
  1140. chip->enable_dma ? "DMA" : "PIO");
  1141. if (spi->bits_per_word <= 8) {
  1142. chip->n_bytes = 1;
  1143. chip->dma_width = DCMD_WIDTH1;
  1144. chip->read = u8_reader;
  1145. chip->write = u8_writer;
  1146. } else if (spi->bits_per_word <= 16) {
  1147. chip->n_bytes = 2;
  1148. chip->dma_width = DCMD_WIDTH2;
  1149. chip->read = u16_reader;
  1150. chip->write = u16_writer;
  1151. } else if (spi->bits_per_word <= 32) {
  1152. chip->cr0 |= SSCR0_EDSS;
  1153. chip->n_bytes = 4;
  1154. chip->dma_width = DCMD_WIDTH4;
  1155. chip->read = u32_reader;
  1156. chip->write = u32_writer;
  1157. } else {
  1158. dev_err(&spi->dev, "invalid wordsize\n");
  1159. return -ENODEV;
  1160. }
  1161. chip->bits_per_word = spi->bits_per_word;
  1162. spi_set_ctldata(spi, chip);
  1163. if (drv_data->ssp_type == CE4100_SSP)
  1164. return 0;
  1165. return setup_cs(spi, chip, chip_info);
  1166. }
  1167. static void cleanup(struct spi_device *spi)
  1168. {
  1169. struct chip_data *chip = spi_get_ctldata(spi);
  1170. struct driver_data *drv_data = spi_master_get_devdata(spi->master);
  1171. if (!chip)
  1172. return;
  1173. if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
  1174. gpio_free(chip->gpio_cs);
  1175. kfree(chip);
  1176. }
  1177. static int __devinit init_queue(struct driver_data *drv_data)
  1178. {
  1179. INIT_LIST_HEAD(&drv_data->queue);
  1180. spin_lock_init(&drv_data->lock);
  1181. drv_data->run = QUEUE_STOPPED;
  1182. drv_data->busy = 0;
  1183. tasklet_init(&drv_data->pump_transfers,
  1184. pump_transfers, (unsigned long)drv_data);
  1185. INIT_WORK(&drv_data->pump_messages, pump_messages);
  1186. drv_data->workqueue = create_singlethread_workqueue(
  1187. dev_name(drv_data->master->dev.parent));
  1188. if (drv_data->workqueue == NULL)
  1189. return -EBUSY;
  1190. return 0;
  1191. }
  1192. static int start_queue(struct driver_data *drv_data)
  1193. {
  1194. unsigned long flags;
  1195. spin_lock_irqsave(&drv_data->lock, flags);
  1196. if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
  1197. spin_unlock_irqrestore(&drv_data->lock, flags);
  1198. return -EBUSY;
  1199. }
  1200. drv_data->run = QUEUE_RUNNING;
  1201. drv_data->cur_msg = NULL;
  1202. drv_data->cur_transfer = NULL;
  1203. drv_data->cur_chip = NULL;
  1204. spin_unlock_irqrestore(&drv_data->lock, flags);
  1205. queue_work(drv_data->workqueue, &drv_data->pump_messages);
  1206. return 0;
  1207. }
  1208. static int stop_queue(struct driver_data *drv_data)
  1209. {
  1210. unsigned long flags;
  1211. unsigned limit = 500;
  1212. int status = 0;
  1213. spin_lock_irqsave(&drv_data->lock, flags);
  1214. /* This is a bit lame, but is optimized for the common execution path.
  1215. * A wait_queue on the drv_data->busy could be used, but then the common
  1216. * execution path (pump_messages) would be required to call wake_up or
  1217. * friends on every SPI message. Do this instead */
  1218. drv_data->run = QUEUE_STOPPED;
  1219. while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
  1220. spin_unlock_irqrestore(&drv_data->lock, flags);
  1221. msleep(10);
  1222. spin_lock_irqsave(&drv_data->lock, flags);
  1223. }
  1224. if (!list_empty(&drv_data->queue) || drv_data->busy)
  1225. status = -EBUSY;
  1226. spin_unlock_irqrestore(&drv_data->lock, flags);
  1227. return status;
  1228. }
  1229. static int destroy_queue(struct driver_data *drv_data)
  1230. {
  1231. int status;
  1232. status = stop_queue(drv_data);
  1233. /* we are unloading the module or failing to load (only two calls
  1234. * to this routine), and neither call can handle a return value.
  1235. * However, destroy_workqueue calls flush_workqueue, and that will
  1236. * block until all work is done. If the reason that stop_queue
  1237. * timed out is that the work will never finish, then it does no
  1238. * good to call destroy_workqueue, so return anyway. */
  1239. if (status != 0)
  1240. return status;
  1241. destroy_workqueue(drv_data->workqueue);
  1242. return 0;
  1243. }
  1244. static int __devinit pxa2xx_spi_probe(struct platform_device *pdev)
  1245. {
  1246. struct device *dev = &pdev->dev;
  1247. struct pxa2xx_spi_master *platform_info;
  1248. struct spi_master *master;
  1249. struct driver_data *drv_data;
  1250. struct ssp_device *ssp;
  1251. int status;
  1252. platform_info = dev->platform_data;
  1253. ssp = pxa_ssp_request(pdev->id, pdev->name);
  1254. if (ssp == NULL) {
  1255. dev_err(&pdev->dev, "failed to request SSP%d\n", pdev->id);
  1256. return -ENODEV;
  1257. }
  1258. /* Allocate master with space for drv_data and null dma buffer */
  1259. master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
  1260. if (!master) {
  1261. dev_err(&pdev->dev, "cannot alloc spi_master\n");
  1262. pxa_ssp_free(ssp);
  1263. return -ENOMEM;
  1264. }
  1265. drv_data = spi_master_get_devdata(master);
  1266. drv_data->master = master;
  1267. drv_data->master_info = platform_info;
  1268. drv_data->pdev = pdev;
  1269. drv_data->ssp = ssp;
  1270. /* the spi->mode bits understood by this driver: */
  1271. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  1272. master->bus_num = pdev->id;
  1273. master->num_chipselect = platform_info->num_chipselect;
  1274. master->dma_alignment = DMA_ALIGNMENT;
  1275. master->cleanup = cleanup;
  1276. master->setup = setup;
  1277. master->transfer = transfer;
  1278. drv_data->ssp_type = ssp->type;
  1279. drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
  1280. sizeof(struct driver_data)), 8);
  1281. drv_data->ioaddr = ssp->mmio_base;
  1282. drv_data->ssdr_physical = ssp->phys_base + SSDR;
  1283. if (pxa25x_ssp_comp(drv_data)) {
  1284. drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
  1285. drv_data->dma_cr1 = 0;
  1286. drv_data->clear_sr = SSSR_ROR;
  1287. drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
  1288. } else {
  1289. drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
  1290. drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
  1291. drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
  1292. drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
  1293. }
  1294. status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
  1295. drv_data);
  1296. if (status < 0) {
  1297. dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
  1298. goto out_error_master_alloc;
  1299. }
  1300. /* Setup DMA if requested */
  1301. drv_data->tx_channel = -1;
  1302. drv_data->rx_channel = -1;
  1303. if (platform_info->enable_dma) {
  1304. /* Get two DMA channels (rx and tx) */
  1305. drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
  1306. DMA_PRIO_HIGH,
  1307. dma_handler,
  1308. drv_data);
  1309. if (drv_data->rx_channel < 0) {
  1310. dev_err(dev, "problem (%d) requesting rx channel\n",
  1311. drv_data->rx_channel);
  1312. status = -ENODEV;
  1313. goto out_error_irq_alloc;
  1314. }
  1315. drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
  1316. DMA_PRIO_MEDIUM,
  1317. dma_handler,
  1318. drv_data);
  1319. if (drv_data->tx_channel < 0) {
  1320. dev_err(dev, "problem (%d) requesting tx channel\n",
  1321. drv_data->tx_channel);
  1322. status = -ENODEV;
  1323. goto out_error_dma_alloc;
  1324. }
  1325. DRCMR(ssp->drcmr_rx) = DRCMR_MAPVLD | drv_data->rx_channel;
  1326. DRCMR(ssp->drcmr_tx) = DRCMR_MAPVLD | drv_data->tx_channel;
  1327. }
  1328. /* Enable SOC clock */
  1329. clk_enable(ssp->clk);
  1330. /* Load default SSP configuration */
  1331. write_SSCR0(0, drv_data->ioaddr);
  1332. write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
  1333. SSCR1_TxTresh(TX_THRESH_DFLT),
  1334. drv_data->ioaddr);
  1335. write_SSCR0(SSCR0_SCR(2)
  1336. | SSCR0_Motorola
  1337. | SSCR0_DataSize(8),
  1338. drv_data->ioaddr);
  1339. if (!pxa25x_ssp_comp(drv_data))
  1340. write_SSTO(0, drv_data->ioaddr);
  1341. write_SSPSP(0, drv_data->ioaddr);
  1342. /* Initial and start queue */
  1343. status = init_queue(drv_data);
  1344. if (status != 0) {
  1345. dev_err(&pdev->dev, "problem initializing queue\n");
  1346. goto out_error_clock_enabled;
  1347. }
  1348. status = start_queue(drv_data);
  1349. if (status != 0) {
  1350. dev_err(&pdev->dev, "problem starting queue\n");
  1351. goto out_error_clock_enabled;
  1352. }
  1353. /* Register with the SPI framework */
  1354. platform_set_drvdata(pdev, drv_data);
  1355. status = spi_register_master(master);
  1356. if (status != 0) {
  1357. dev_err(&pdev->dev, "problem registering spi master\n");
  1358. goto out_error_queue_alloc;
  1359. }
  1360. return status;
  1361. out_error_queue_alloc:
  1362. destroy_queue(drv_data);
  1363. out_error_clock_enabled:
  1364. clk_disable(ssp->clk);
  1365. out_error_dma_alloc:
  1366. if (drv_data->tx_channel != -1)
  1367. pxa_free_dma(drv_data->tx_channel);
  1368. if (drv_data->rx_channel != -1)
  1369. pxa_free_dma(drv_data->rx_channel);
  1370. out_error_irq_alloc:
  1371. free_irq(ssp->irq, drv_data);
  1372. out_error_master_alloc:
  1373. spi_master_put(master);
  1374. pxa_ssp_free(ssp);
  1375. return status;
  1376. }
  1377. static int pxa2xx_spi_remove(struct platform_device *pdev)
  1378. {
  1379. struct driver_data *drv_data = platform_get_drvdata(pdev);
  1380. struct ssp_device *ssp;
  1381. int status = 0;
  1382. if (!drv_data)
  1383. return 0;
  1384. ssp = drv_data->ssp;
  1385. /* Remove the queue */
  1386. status = destroy_queue(drv_data);
  1387. if (status != 0)
  1388. /* the kernel does not check the return status of this
  1389. * this routine (mod->exit, within the kernel). Therefore
  1390. * nothing is gained by returning from here, the module is
  1391. * going away regardless, and we should not leave any more
  1392. * resources allocated than necessary. We cannot free the
  1393. * message memory in drv_data->queue, but we can release the
  1394. * resources below. I think the kernel should honor -EBUSY
  1395. * returns but... */
  1396. dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
  1397. "complete, message memory not freed\n");
  1398. /* Disable the SSP at the peripheral and SOC level */
  1399. write_SSCR0(0, drv_data->ioaddr);
  1400. clk_disable(ssp->clk);
  1401. /* Release DMA */
  1402. if (drv_data->master_info->enable_dma) {
  1403. DRCMR(ssp->drcmr_rx) = 0;
  1404. DRCMR(ssp->drcmr_tx) = 0;
  1405. pxa_free_dma(drv_data->tx_channel);
  1406. pxa_free_dma(drv_data->rx_channel);
  1407. }
  1408. /* Release IRQ */
  1409. free_irq(ssp->irq, drv_data);
  1410. /* Release SSP */
  1411. pxa_ssp_free(ssp);
  1412. /* Disconnect from the SPI framework */
  1413. spi_unregister_master(drv_data->master);
  1414. /* Prevent double remove */
  1415. platform_set_drvdata(pdev, NULL);
  1416. return 0;
  1417. }
  1418. static void pxa2xx_spi_shutdown(struct platform_device *pdev)
  1419. {
  1420. int status = 0;
  1421. if ((status = pxa2xx_spi_remove(pdev)) != 0)
  1422. dev_err(&pdev->dev, "shutdown failed with %d\n", status);
  1423. }
  1424. #ifdef CONFIG_PM
  1425. static int pxa2xx_spi_suspend(struct device *dev)
  1426. {
  1427. struct driver_data *drv_data = dev_get_drvdata(dev);
  1428. struct ssp_device *ssp = drv_data->ssp;
  1429. int status = 0;
  1430. status = stop_queue(drv_data);
  1431. if (status != 0)
  1432. return status;
  1433. write_SSCR0(0, drv_data->ioaddr);
  1434. clk_disable(ssp->clk);
  1435. return 0;
  1436. }
  1437. static int pxa2xx_spi_resume(struct device *dev)
  1438. {
  1439. struct driver_data *drv_data = dev_get_drvdata(dev);
  1440. struct ssp_device *ssp = drv_data->ssp;
  1441. int status = 0;
  1442. if (drv_data->rx_channel != -1)
  1443. DRCMR(drv_data->ssp->drcmr_rx) =
  1444. DRCMR_MAPVLD | drv_data->rx_channel;
  1445. if (drv_data->tx_channel != -1)
  1446. DRCMR(drv_data->ssp->drcmr_tx) =
  1447. DRCMR_MAPVLD | drv_data->tx_channel;
  1448. /* Enable the SSP clock */
  1449. clk_enable(ssp->clk);
  1450. /* Start the queue running */
  1451. status = start_queue(drv_data);
  1452. if (status != 0) {
  1453. dev_err(dev, "problem starting queue (%d)\n", status);
  1454. return status;
  1455. }
  1456. return 0;
  1457. }
  1458. static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
  1459. .suspend = pxa2xx_spi_suspend,
  1460. .resume = pxa2xx_spi_resume,
  1461. };
  1462. #endif
  1463. static struct platform_driver driver = {
  1464. .driver = {
  1465. .name = "pxa2xx-spi",
  1466. .owner = THIS_MODULE,
  1467. #ifdef CONFIG_PM
  1468. .pm = &pxa2xx_spi_pm_ops,
  1469. #endif
  1470. },
  1471. .probe = pxa2xx_spi_probe,
  1472. .remove = pxa2xx_spi_remove,
  1473. .shutdown = pxa2xx_spi_shutdown,
  1474. };
  1475. static int __init pxa2xx_spi_init(void)
  1476. {
  1477. return platform_driver_register(&driver);
  1478. }
  1479. subsys_initcall(pxa2xx_spi_init);
  1480. static void __exit pxa2xx_spi_exit(void)
  1481. {
  1482. platform_driver_unregister(&driver);
  1483. }
  1484. module_exit(pxa2xx_spi_exit);