ice1712.c 82 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. NOTES:
  23. - spdif nonaudio consumer mode does not work (at least with my
  24. Sony STR-DB830)
  25. */
  26. /*
  27. * Changes:
  28. *
  29. * 2002.09.09 Takashi Iwai <tiwai@suse.de>
  30. * split the code to several files. each low-level routine
  31. * is stored in the local file and called from registration
  32. * function from card_info struct.
  33. *
  34. * 2002.11.26 James Stafford <jstafford@ampltd.com>
  35. * Added support for VT1724 (Envy24HT)
  36. * I have left out support for 176.4 and 192 KHz for the moment.
  37. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  38. *
  39. * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
  40. * Split vt1724 part to an independent driver.
  41. * The GPIO is accessed through the callback functions now.
  42. *
  43. * 2004.03.31 Doug McLain <nostar@comcast.net>
  44. * Added support for Event Electronics EZ8 card to hoontech.c.
  45. */
  46. #include <sound/driver.h>
  47. #include <asm/io.h>
  48. #include <linux/delay.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/init.h>
  51. #include <linux/pci.h>
  52. #include <linux/dma-mapping.h>
  53. #include <linux/slab.h>
  54. #include <linux/moduleparam.h>
  55. #include <linux/mutex.h>
  56. #include <sound/core.h>
  57. #include <sound/cs8427.h>
  58. #include <sound/info.h>
  59. #include <sound/initval.h>
  60. #include <sound/tlv.h>
  61. #include <sound/asoundef.h>
  62. #include "ice1712.h"
  63. /* lowlevel routines */
  64. #include "delta.h"
  65. #include "ews.h"
  66. #include "hoontech.h"
  67. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  68. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  69. MODULE_LICENSE("GPL");
  70. MODULE_SUPPORTED_DEVICE("{"
  71. HOONTECH_DEVICE_DESC
  72. DELTA_DEVICE_DESC
  73. EWS_DEVICE_DESC
  74. "{ICEnsemble,Generic ICE1712},"
  75. "{ICEnsemble,Generic Envy24}}");
  76. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  77. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  78. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  79. static char *model[SNDRV_CARDS];
  80. static int omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  81. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transciever reset timeout value in msec */
  82. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  83. module_param_array(index, int, NULL, 0444);
  84. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  85. module_param_array(id, charp, NULL, 0444);
  86. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  87. module_param_array(enable, bool, NULL, 0444);
  88. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  89. module_param_array(omni, bool, NULL, 0444);
  90. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  91. module_param_array(cs8427_timeout, int, NULL, 0444);
  92. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  93. module_param_array(model, charp, NULL, 0444);
  94. MODULE_PARM_DESC(model, "Use the given board model.");
  95. module_param_array(dxr_enable, int, NULL, 0444);
  96. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  97. static const struct pci_device_id snd_ice1712_ids[] = {
  98. { PCI_VENDOR_ID_ICE, PCI_DEVICE_ID_ICE_1712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICE1712 */
  99. { 0, }
  100. };
  101. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  102. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  103. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  104. static int PRO_RATE_LOCKED;
  105. static int PRO_RATE_RESET = 1;
  106. static unsigned int PRO_RATE_DEFAULT = 44100;
  107. /*
  108. * Basic I/O
  109. */
  110. /* check whether the clock mode is spdif-in */
  111. static inline int is_spdif_master(struct snd_ice1712 *ice)
  112. {
  113. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  114. }
  115. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  116. {
  117. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  118. }
  119. static inline void snd_ice1712_ds_write(struct snd_ice1712 * ice, u8 channel, u8 addr, u32 data)
  120. {
  121. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  122. outl(data, ICEDS(ice, DATA));
  123. }
  124. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 * ice, u8 channel, u8 addr)
  125. {
  126. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  127. return inl(ICEDS(ice, DATA));
  128. }
  129. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  130. unsigned short reg,
  131. unsigned short val)
  132. {
  133. struct snd_ice1712 *ice = ac97->private_data;
  134. int tm;
  135. unsigned char old_cmd = 0;
  136. for (tm = 0; tm < 0x10000; tm++) {
  137. old_cmd = inb(ICEREG(ice, AC97_CMD));
  138. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  139. continue;
  140. if (!(old_cmd & ICE1712_AC97_READY))
  141. continue;
  142. break;
  143. }
  144. outb(reg, ICEREG(ice, AC97_INDEX));
  145. outw(val, ICEREG(ice, AC97_DATA));
  146. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  147. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  148. for (tm = 0; tm < 0x10000; tm++)
  149. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  150. break;
  151. }
  152. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  153. unsigned short reg)
  154. {
  155. struct snd_ice1712 *ice = ac97->private_data;
  156. int tm;
  157. unsigned char old_cmd = 0;
  158. for (tm = 0; tm < 0x10000; tm++) {
  159. old_cmd = inb(ICEREG(ice, AC97_CMD));
  160. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  161. continue;
  162. if (!(old_cmd & ICE1712_AC97_READY))
  163. continue;
  164. break;
  165. }
  166. outb(reg, ICEREG(ice, AC97_INDEX));
  167. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  168. for (tm = 0; tm < 0x10000; tm++)
  169. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  170. break;
  171. if (tm >= 0x10000) /* timeout */
  172. return ~0;
  173. return inw(ICEREG(ice, AC97_DATA));
  174. }
  175. /*
  176. * pro ac97 section
  177. */
  178. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  179. unsigned short reg,
  180. unsigned short val)
  181. {
  182. struct snd_ice1712 *ice = ac97->private_data;
  183. int tm;
  184. unsigned char old_cmd = 0;
  185. for (tm = 0; tm < 0x10000; tm++) {
  186. old_cmd = inb(ICEMT(ice, AC97_CMD));
  187. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  188. continue;
  189. if (!(old_cmd & ICE1712_AC97_READY))
  190. continue;
  191. break;
  192. }
  193. outb(reg, ICEMT(ice, AC97_INDEX));
  194. outw(val, ICEMT(ice, AC97_DATA));
  195. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  196. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  197. for (tm = 0; tm < 0x10000; tm++)
  198. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  199. break;
  200. }
  201. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  202. unsigned short reg)
  203. {
  204. struct snd_ice1712 *ice = ac97->private_data;
  205. int tm;
  206. unsigned char old_cmd = 0;
  207. for (tm = 0; tm < 0x10000; tm++) {
  208. old_cmd = inb(ICEMT(ice, AC97_CMD));
  209. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  210. continue;
  211. if (!(old_cmd & ICE1712_AC97_READY))
  212. continue;
  213. break;
  214. }
  215. outb(reg, ICEMT(ice, AC97_INDEX));
  216. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  217. for (tm = 0; tm < 0x10000; tm++)
  218. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  219. break;
  220. if (tm >= 0x10000) /* timeout */
  221. return ~0;
  222. return inw(ICEMT(ice, AC97_DATA));
  223. }
  224. /*
  225. * consumer ac97 digital mix
  226. */
  227. #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
  228. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  229. {
  230. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  231. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  232. return 0;
  233. }
  234. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  235. {
  236. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  237. unsigned char val, nval;
  238. spin_lock_irq(&ice->reg_lock);
  239. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  240. nval = val & ~ICE1712_ROUTE_AC97;
  241. if (ucontrol->value.integer.value[0]) nval |= ICE1712_ROUTE_AC97;
  242. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  243. spin_unlock_irq(&ice->reg_lock);
  244. return val != nval;
  245. }
  246. static struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 __devinitdata = {
  247. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  248. .name = "Digital Mixer To AC97",
  249. .info = snd_ice1712_digmix_route_ac97_info,
  250. .get = snd_ice1712_digmix_route_ac97_get,
  251. .put = snd_ice1712_digmix_route_ac97_put,
  252. };
  253. /*
  254. * gpio operations
  255. */
  256. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  257. {
  258. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  259. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  260. }
  261. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  262. {
  263. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  264. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  265. }
  266. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  267. {
  268. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  269. }
  270. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  271. {
  272. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  273. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  274. }
  275. /*
  276. *
  277. * CS8427 interface
  278. *
  279. */
  280. /*
  281. * change the input clock selection
  282. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  283. */
  284. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  285. {
  286. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  287. unsigned char val, nval;
  288. int res = 0;
  289. snd_i2c_lock(ice->i2c);
  290. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  291. snd_i2c_unlock(ice->i2c);
  292. return -EIO;
  293. }
  294. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  295. snd_i2c_unlock(ice->i2c);
  296. return -EIO;
  297. }
  298. nval = val & 0xf0;
  299. if (spdif_clock)
  300. nval |= 0x01;
  301. else
  302. nval |= 0x04;
  303. if (val != nval) {
  304. reg[1] = nval;
  305. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  306. res = -EIO;
  307. } else {
  308. res++;
  309. }
  310. }
  311. snd_i2c_unlock(ice->i2c);
  312. return res;
  313. }
  314. /*
  315. * spdif callbacks
  316. */
  317. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  318. {
  319. snd_cs8427_iec958_active(ice->cs8427, 1);
  320. }
  321. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  322. {
  323. snd_cs8427_iec958_active(ice->cs8427, 0);
  324. }
  325. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  326. {
  327. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  328. }
  329. /*
  330. * create and initialize callbacks for cs8427 interface
  331. */
  332. int __devinit snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  333. {
  334. int err;
  335. if ((err = snd_cs8427_create(ice->i2c, addr,
  336. (ice->cs8427_timeout * HZ) / 1000,
  337. &ice->cs8427)) < 0) {
  338. snd_printk(KERN_ERR "CS8427 initialization failed\n");
  339. return err;
  340. }
  341. ice->spdif.ops.open = open_cs8427;
  342. ice->spdif.ops.close = close_cs8427;
  343. ice->spdif.ops.setup_rate = setup_cs8427;
  344. return 0;
  345. }
  346. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  347. {
  348. /* change CS8427 clock source too */
  349. if (ice->cs8427)
  350. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  351. /* notify ak4524 chip as well */
  352. if (spdif_is_master) {
  353. unsigned int i;
  354. for (i = 0; i < ice->akm_codecs; i++) {
  355. if (ice->akm[i].ops.set_rate_val)
  356. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  357. }
  358. }
  359. }
  360. /*
  361. * Interrupt handler
  362. */
  363. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  364. {
  365. struct snd_ice1712 *ice = dev_id;
  366. unsigned char status;
  367. int handled = 0;
  368. while (1) {
  369. status = inb(ICEREG(ice, IRQSTAT));
  370. if (status == 0)
  371. break;
  372. handled = 1;
  373. if (status & ICE1712_IRQ_MPU1) {
  374. if (ice->rmidi[0])
  375. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  376. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  377. status &= ~ICE1712_IRQ_MPU1;
  378. }
  379. if (status & ICE1712_IRQ_TIMER)
  380. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  381. if (status & ICE1712_IRQ_MPU2) {
  382. if (ice->rmidi[1])
  383. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  384. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  385. status &= ~ICE1712_IRQ_MPU2;
  386. }
  387. if (status & ICE1712_IRQ_PROPCM) {
  388. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  389. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  390. if (ice->playback_pro_substream)
  391. snd_pcm_period_elapsed(ice->playback_pro_substream);
  392. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  393. }
  394. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  395. if (ice->capture_pro_substream)
  396. snd_pcm_period_elapsed(ice->capture_pro_substream);
  397. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  398. }
  399. }
  400. if (status & ICE1712_IRQ_FM)
  401. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  402. if (status & ICE1712_IRQ_PBKDS) {
  403. u32 idx;
  404. u16 pbkstatus;
  405. struct snd_pcm_substream *substream;
  406. pbkstatus = inw(ICEDS(ice, INTSTAT));
  407. //printk("pbkstatus = 0x%x\n", pbkstatus);
  408. for (idx = 0; idx < 6; idx++) {
  409. if ((pbkstatus & (3 << (idx * 2))) == 0)
  410. continue;
  411. if ((substream = ice->playback_con_substream_ds[idx]) != NULL)
  412. snd_pcm_period_elapsed(substream);
  413. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  414. }
  415. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  416. }
  417. if (status & ICE1712_IRQ_CONCAP) {
  418. if (ice->capture_con_substream)
  419. snd_pcm_period_elapsed(ice->capture_con_substream);
  420. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  421. }
  422. if (status & ICE1712_IRQ_CONPBK) {
  423. if (ice->playback_con_substream)
  424. snd_pcm_period_elapsed(ice->playback_con_substream);
  425. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  426. }
  427. }
  428. return IRQ_RETVAL(handled);
  429. }
  430. /*
  431. * PCM part - misc
  432. */
  433. static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
  434. struct snd_pcm_hw_params *hw_params)
  435. {
  436. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  437. }
  438. static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
  439. {
  440. return snd_pcm_lib_free_pages(substream);
  441. }
  442. /*
  443. * PCM part - consumer I/O
  444. */
  445. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  446. int cmd)
  447. {
  448. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  449. int result = 0;
  450. u32 tmp;
  451. spin_lock(&ice->reg_lock);
  452. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  453. if (cmd == SNDRV_PCM_TRIGGER_START) {
  454. tmp |= 1;
  455. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  456. tmp &= ~1;
  457. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  458. tmp |= 2;
  459. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  460. tmp &= ~2;
  461. } else {
  462. result = -EINVAL;
  463. }
  464. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  465. spin_unlock(&ice->reg_lock);
  466. return result;
  467. }
  468. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  469. int cmd)
  470. {
  471. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  472. int result = 0;
  473. u32 tmp;
  474. spin_lock(&ice->reg_lock);
  475. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  476. if (cmd == SNDRV_PCM_TRIGGER_START) {
  477. tmp |= 1;
  478. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  479. tmp &= ~1;
  480. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  481. tmp |= 2;
  482. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  483. tmp &= ~2;
  484. } else {
  485. result = -EINVAL;
  486. }
  487. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  488. spin_unlock(&ice->reg_lock);
  489. return result;
  490. }
  491. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  492. int cmd)
  493. {
  494. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  495. int result = 0;
  496. u8 tmp;
  497. spin_lock(&ice->reg_lock);
  498. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  499. if (cmd == SNDRV_PCM_TRIGGER_START) {
  500. tmp |= 1;
  501. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  502. tmp &= ~1;
  503. } else {
  504. result = -EINVAL;
  505. }
  506. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  507. spin_unlock(&ice->reg_lock);
  508. return result;
  509. }
  510. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  511. {
  512. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  513. struct snd_pcm_runtime *runtime = substream->runtime;
  514. u32 period_size, buf_size, rate, tmp;
  515. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  516. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  517. tmp = 0x0000;
  518. if (snd_pcm_format_width(runtime->format) == 16)
  519. tmp |= 0x10;
  520. if (runtime->channels == 2)
  521. tmp |= 0x08;
  522. rate = (runtime->rate * 8192) / 375;
  523. if (rate > 0x000fffff)
  524. rate = 0x000fffff;
  525. spin_lock_irq(&ice->reg_lock);
  526. outb(0, ice->ddma_port + 15);
  527. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  528. outl(runtime->dma_addr, ice->ddma_port + 0);
  529. outw(buf_size, ice->ddma_port + 4);
  530. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  531. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  532. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  533. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  534. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  535. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  536. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  537. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  538. spin_unlock_irq(&ice->reg_lock);
  539. return 0;
  540. }
  541. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  542. {
  543. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  544. struct snd_pcm_runtime *runtime = substream->runtime;
  545. u32 period_size, buf_size, rate, tmp, chn;
  546. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  547. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  548. tmp = 0x0064;
  549. if (snd_pcm_format_width(runtime->format) == 16)
  550. tmp &= ~0x04;
  551. if (runtime->channels == 2)
  552. tmp |= 0x08;
  553. rate = (runtime->rate * 8192) / 375;
  554. if (rate > 0x000fffff)
  555. rate = 0x000fffff;
  556. ice->playback_con_active_buf[substream->number] = 0;
  557. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  558. chn = substream->number * 2;
  559. spin_lock_irq(&ice->reg_lock);
  560. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  561. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  562. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  563. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  564. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  565. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  566. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  567. if (runtime->channels == 2) {
  568. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  569. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  570. }
  571. spin_unlock_irq(&ice->reg_lock);
  572. return 0;
  573. }
  574. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  575. {
  576. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  577. struct snd_pcm_runtime *runtime = substream->runtime;
  578. u32 period_size, buf_size;
  579. u8 tmp;
  580. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  581. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  582. tmp = 0x06;
  583. if (snd_pcm_format_width(runtime->format) == 16)
  584. tmp &= ~0x04;
  585. if (runtime->channels == 2)
  586. tmp &= ~0x02;
  587. spin_lock_irq(&ice->reg_lock);
  588. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  589. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  590. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  591. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  592. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  593. spin_unlock_irq(&ice->reg_lock);
  594. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  595. return 0;
  596. }
  597. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  598. {
  599. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  600. struct snd_pcm_runtime *runtime = substream->runtime;
  601. size_t ptr;
  602. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  603. return 0;
  604. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  605. if (ptr == runtime->buffer_size)
  606. ptr = 0;
  607. return bytes_to_frames(substream->runtime, ptr);
  608. }
  609. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  610. {
  611. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  612. u8 addr;
  613. size_t ptr;
  614. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  615. return 0;
  616. if (ice->playback_con_active_buf[substream->number])
  617. addr = ICE1712_DSC_ADDR1;
  618. else
  619. addr = ICE1712_DSC_ADDR0;
  620. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  621. ice->playback_con_virt_addr[substream->number];
  622. if (ptr == substream->runtime->buffer_size)
  623. ptr = 0;
  624. return bytes_to_frames(substream->runtime, ptr);
  625. }
  626. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  627. {
  628. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  629. size_t ptr;
  630. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  631. return 0;
  632. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  633. if (ptr == substream->runtime->buffer_size)
  634. ptr = 0;
  635. return bytes_to_frames(substream->runtime, ptr);
  636. }
  637. static const struct snd_pcm_hardware snd_ice1712_playback =
  638. {
  639. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  640. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  641. SNDRV_PCM_INFO_MMAP_VALID |
  642. SNDRV_PCM_INFO_PAUSE),
  643. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  644. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  645. .rate_min = 4000,
  646. .rate_max = 48000,
  647. .channels_min = 1,
  648. .channels_max = 2,
  649. .buffer_bytes_max = (64*1024),
  650. .period_bytes_min = 64,
  651. .period_bytes_max = (64*1024),
  652. .periods_min = 1,
  653. .periods_max = 1024,
  654. .fifo_size = 0,
  655. };
  656. static const struct snd_pcm_hardware snd_ice1712_playback_ds =
  657. {
  658. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  659. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  660. SNDRV_PCM_INFO_MMAP_VALID |
  661. SNDRV_PCM_INFO_PAUSE),
  662. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  663. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  664. .rate_min = 4000,
  665. .rate_max = 48000,
  666. .channels_min = 1,
  667. .channels_max = 2,
  668. .buffer_bytes_max = (128*1024),
  669. .period_bytes_min = 64,
  670. .period_bytes_max = (128*1024),
  671. .periods_min = 2,
  672. .periods_max = 2,
  673. .fifo_size = 0,
  674. };
  675. static const struct snd_pcm_hardware snd_ice1712_capture =
  676. {
  677. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  678. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  679. SNDRV_PCM_INFO_MMAP_VALID),
  680. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  681. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  682. .rate_min = 4000,
  683. .rate_max = 48000,
  684. .channels_min = 1,
  685. .channels_max = 2,
  686. .buffer_bytes_max = (64*1024),
  687. .period_bytes_min = 64,
  688. .period_bytes_max = (64*1024),
  689. .periods_min = 1,
  690. .periods_max = 1024,
  691. .fifo_size = 0,
  692. };
  693. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  694. {
  695. struct snd_pcm_runtime *runtime = substream->runtime;
  696. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  697. ice->playback_con_substream = substream;
  698. runtime->hw = snd_ice1712_playback;
  699. return 0;
  700. }
  701. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  702. {
  703. struct snd_pcm_runtime *runtime = substream->runtime;
  704. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  705. u32 tmp;
  706. ice->playback_con_substream_ds[substream->number] = substream;
  707. runtime->hw = snd_ice1712_playback_ds;
  708. spin_lock_irq(&ice->reg_lock);
  709. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  710. outw(tmp, ICEDS(ice, INTMASK));
  711. spin_unlock_irq(&ice->reg_lock);
  712. return 0;
  713. }
  714. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  715. {
  716. struct snd_pcm_runtime *runtime = substream->runtime;
  717. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  718. ice->capture_con_substream = substream;
  719. runtime->hw = snd_ice1712_capture;
  720. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  721. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  722. runtime->hw.rate_min = 48000;
  723. return 0;
  724. }
  725. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  726. {
  727. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  728. ice->playback_con_substream = NULL;
  729. return 0;
  730. }
  731. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  732. {
  733. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  734. u32 tmp;
  735. spin_lock_irq(&ice->reg_lock);
  736. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  737. outw(tmp, ICEDS(ice, INTMASK));
  738. spin_unlock_irq(&ice->reg_lock);
  739. ice->playback_con_substream_ds[substream->number] = NULL;
  740. return 0;
  741. }
  742. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  743. {
  744. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  745. ice->capture_con_substream = NULL;
  746. return 0;
  747. }
  748. static struct snd_pcm_ops snd_ice1712_playback_ops = {
  749. .open = snd_ice1712_playback_open,
  750. .close = snd_ice1712_playback_close,
  751. .ioctl = snd_pcm_lib_ioctl,
  752. .hw_params = snd_ice1712_hw_params,
  753. .hw_free = snd_ice1712_hw_free,
  754. .prepare = snd_ice1712_playback_prepare,
  755. .trigger = snd_ice1712_playback_trigger,
  756. .pointer = snd_ice1712_playback_pointer,
  757. };
  758. static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  759. .open = snd_ice1712_playback_ds_open,
  760. .close = snd_ice1712_playback_ds_close,
  761. .ioctl = snd_pcm_lib_ioctl,
  762. .hw_params = snd_ice1712_hw_params,
  763. .hw_free = snd_ice1712_hw_free,
  764. .prepare = snd_ice1712_playback_ds_prepare,
  765. .trigger = snd_ice1712_playback_ds_trigger,
  766. .pointer = snd_ice1712_playback_ds_pointer,
  767. };
  768. static struct snd_pcm_ops snd_ice1712_capture_ops = {
  769. .open = snd_ice1712_capture_open,
  770. .close = snd_ice1712_capture_close,
  771. .ioctl = snd_pcm_lib_ioctl,
  772. .hw_params = snd_ice1712_hw_params,
  773. .hw_free = snd_ice1712_hw_free,
  774. .prepare = snd_ice1712_capture_prepare,
  775. .trigger = snd_ice1712_capture_trigger,
  776. .pointer = snd_ice1712_capture_pointer,
  777. };
  778. static int __devinit snd_ice1712_pcm(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  779. {
  780. struct snd_pcm *pcm;
  781. int err;
  782. if (rpcm)
  783. *rpcm = NULL;
  784. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  785. if (err < 0)
  786. return err;
  787. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  788. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  789. pcm->private_data = ice;
  790. pcm->info_flags = 0;
  791. strcpy(pcm->name, "ICE1712 consumer");
  792. ice->pcm = pcm;
  793. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  794. snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
  795. if (rpcm)
  796. *rpcm = pcm;
  797. printk(KERN_WARNING "Consumer PCM code does not work well at the moment --jk\n");
  798. return 0;
  799. }
  800. static int __devinit snd_ice1712_pcm_ds(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  801. {
  802. struct snd_pcm *pcm;
  803. int err;
  804. if (rpcm)
  805. *rpcm = NULL;
  806. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  807. if (err < 0)
  808. return err;
  809. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  810. pcm->private_data = ice;
  811. pcm->info_flags = 0;
  812. strcpy(pcm->name, "ICE1712 consumer (DS)");
  813. ice->pcm_ds = pcm;
  814. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  815. snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
  816. if (rpcm)
  817. *rpcm = pcm;
  818. return 0;
  819. }
  820. /*
  821. * PCM code - professional part (multitrack)
  822. */
  823. static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  824. 32000, 44100, 48000, 64000, 88200, 96000 };
  825. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  826. .count = ARRAY_SIZE(rates),
  827. .list = rates,
  828. .mask = 0,
  829. };
  830. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  831. int cmd)
  832. {
  833. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  834. switch (cmd) {
  835. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  836. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  837. {
  838. unsigned int what;
  839. unsigned int old;
  840. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  841. return -EINVAL;
  842. what = ICE1712_PLAYBACK_PAUSE;
  843. snd_pcm_trigger_done(substream, substream);
  844. spin_lock(&ice->reg_lock);
  845. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  846. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  847. old |= what;
  848. else
  849. old &= ~what;
  850. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  851. spin_unlock(&ice->reg_lock);
  852. break;
  853. }
  854. case SNDRV_PCM_TRIGGER_START:
  855. case SNDRV_PCM_TRIGGER_STOP:
  856. {
  857. unsigned int what = 0;
  858. unsigned int old;
  859. struct snd_pcm_substream *s;
  860. snd_pcm_group_for_each_entry(s, substream) {
  861. if (s == ice->playback_pro_substream) {
  862. what |= ICE1712_PLAYBACK_START;
  863. snd_pcm_trigger_done(s, substream);
  864. } else if (s == ice->capture_pro_substream) {
  865. what |= ICE1712_CAPTURE_START_SHADOW;
  866. snd_pcm_trigger_done(s, substream);
  867. }
  868. }
  869. spin_lock(&ice->reg_lock);
  870. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  871. if (cmd == SNDRV_PCM_TRIGGER_START)
  872. old |= what;
  873. else
  874. old &= ~what;
  875. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  876. spin_unlock(&ice->reg_lock);
  877. break;
  878. }
  879. default:
  880. return -EINVAL;
  881. }
  882. return 0;
  883. }
  884. /*
  885. */
  886. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  887. {
  888. unsigned long flags;
  889. unsigned char val, old;
  890. unsigned int i;
  891. switch (rate) {
  892. case 8000: val = 6; break;
  893. case 9600: val = 3; break;
  894. case 11025: val = 10; break;
  895. case 12000: val = 2; break;
  896. case 16000: val = 5; break;
  897. case 22050: val = 9; break;
  898. case 24000: val = 1; break;
  899. case 32000: val = 4; break;
  900. case 44100: val = 8; break;
  901. case 48000: val = 0; break;
  902. case 64000: val = 15; break;
  903. case 88200: val = 11; break;
  904. case 96000: val = 7; break;
  905. default:
  906. snd_BUG();
  907. val = 0;
  908. rate = 48000;
  909. break;
  910. }
  911. spin_lock_irqsave(&ice->reg_lock, flags);
  912. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  913. ICE1712_PLAYBACK_PAUSE|
  914. ICE1712_PLAYBACK_START)) {
  915. __out:
  916. spin_unlock_irqrestore(&ice->reg_lock, flags);
  917. return;
  918. }
  919. if (!force && is_pro_rate_locked(ice))
  920. goto __out;
  921. old = inb(ICEMT(ice, RATE));
  922. if (!force && old == val)
  923. goto __out;
  924. outb(val, ICEMT(ice, RATE));
  925. spin_unlock_irqrestore(&ice->reg_lock, flags);
  926. if (ice->gpio.set_pro_rate)
  927. ice->gpio.set_pro_rate(ice, rate);
  928. for (i = 0; i < ice->akm_codecs; i++) {
  929. if (ice->akm[i].ops.set_rate_val)
  930. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  931. }
  932. if (ice->spdif.ops.setup_rate)
  933. ice->spdif.ops.setup_rate(ice, rate);
  934. }
  935. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  936. {
  937. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  938. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  939. spin_lock_irq(&ice->reg_lock);
  940. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  941. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  942. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  943. spin_unlock_irq(&ice->reg_lock);
  944. return 0;
  945. }
  946. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  947. struct snd_pcm_hw_params *hw_params)
  948. {
  949. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  950. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  951. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  952. }
  953. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  954. {
  955. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  956. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  957. spin_lock_irq(&ice->reg_lock);
  958. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  959. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  960. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  961. spin_unlock_irq(&ice->reg_lock);
  962. return 0;
  963. }
  964. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  965. struct snd_pcm_hw_params *hw_params)
  966. {
  967. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  968. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  969. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  970. }
  971. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  972. {
  973. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  974. size_t ptr;
  975. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  976. return 0;
  977. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  978. if (ptr == substream->runtime->buffer_size)
  979. ptr = 0;
  980. return bytes_to_frames(substream->runtime, ptr);
  981. }
  982. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  983. {
  984. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  985. size_t ptr;
  986. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  987. return 0;
  988. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  989. if (ptr == substream->runtime->buffer_size)
  990. ptr = 0;
  991. return bytes_to_frames(substream->runtime, ptr);
  992. }
  993. static const struct snd_pcm_hardware snd_ice1712_playback_pro =
  994. {
  995. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  996. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  997. SNDRV_PCM_INFO_MMAP_VALID |
  998. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  999. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1000. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1001. .rate_min = 4000,
  1002. .rate_max = 96000,
  1003. .channels_min = 10,
  1004. .channels_max = 10,
  1005. .buffer_bytes_max = (256*1024),
  1006. .period_bytes_min = 10 * 4 * 2,
  1007. .period_bytes_max = 131040,
  1008. .periods_min = 1,
  1009. .periods_max = 1024,
  1010. .fifo_size = 0,
  1011. };
  1012. static const struct snd_pcm_hardware snd_ice1712_capture_pro =
  1013. {
  1014. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1015. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1016. SNDRV_PCM_INFO_MMAP_VALID |
  1017. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1018. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1019. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1020. .rate_min = 4000,
  1021. .rate_max = 96000,
  1022. .channels_min = 12,
  1023. .channels_max = 12,
  1024. .buffer_bytes_max = (256*1024),
  1025. .period_bytes_min = 12 * 4 * 2,
  1026. .period_bytes_max = 131040,
  1027. .periods_min = 1,
  1028. .periods_max = 1024,
  1029. .fifo_size = 0,
  1030. };
  1031. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  1032. {
  1033. struct snd_pcm_runtime *runtime = substream->runtime;
  1034. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1035. ice->playback_pro_substream = substream;
  1036. runtime->hw = snd_ice1712_playback_pro;
  1037. snd_pcm_set_sync(substream);
  1038. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1039. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1040. if (ice->spdif.ops.open)
  1041. ice->spdif.ops.open(ice, substream);
  1042. return 0;
  1043. }
  1044. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1045. {
  1046. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1047. struct snd_pcm_runtime *runtime = substream->runtime;
  1048. ice->capture_pro_substream = substream;
  1049. runtime->hw = snd_ice1712_capture_pro;
  1050. snd_pcm_set_sync(substream);
  1051. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1052. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1053. return 0;
  1054. }
  1055. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1056. {
  1057. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1058. if (PRO_RATE_RESET)
  1059. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1060. ice->playback_pro_substream = NULL;
  1061. if (ice->spdif.ops.close)
  1062. ice->spdif.ops.close(ice, substream);
  1063. return 0;
  1064. }
  1065. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1066. {
  1067. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1068. if (PRO_RATE_RESET)
  1069. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1070. ice->capture_pro_substream = NULL;
  1071. return 0;
  1072. }
  1073. static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1074. .open = snd_ice1712_playback_pro_open,
  1075. .close = snd_ice1712_playback_pro_close,
  1076. .ioctl = snd_pcm_lib_ioctl,
  1077. .hw_params = snd_ice1712_playback_pro_hw_params,
  1078. .hw_free = snd_ice1712_hw_free,
  1079. .prepare = snd_ice1712_playback_pro_prepare,
  1080. .trigger = snd_ice1712_pro_trigger,
  1081. .pointer = snd_ice1712_playback_pro_pointer,
  1082. };
  1083. static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1084. .open = snd_ice1712_capture_pro_open,
  1085. .close = snd_ice1712_capture_pro_close,
  1086. .ioctl = snd_pcm_lib_ioctl,
  1087. .hw_params = snd_ice1712_capture_pro_hw_params,
  1088. .hw_free = snd_ice1712_hw_free,
  1089. .prepare = snd_ice1712_capture_pro_prepare,
  1090. .trigger = snd_ice1712_pro_trigger,
  1091. .pointer = snd_ice1712_capture_pro_pointer,
  1092. };
  1093. static int __devinit snd_ice1712_pcm_profi(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  1094. {
  1095. struct snd_pcm *pcm;
  1096. int err;
  1097. if (rpcm)
  1098. *rpcm = NULL;
  1099. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1100. if (err < 0)
  1101. return err;
  1102. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1103. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1104. pcm->private_data = ice;
  1105. pcm->info_flags = 0;
  1106. strcpy(pcm->name, "ICE1712 multi");
  1107. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1108. snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
  1109. ice->pcm_pro = pcm;
  1110. if (rpcm)
  1111. *rpcm = pcm;
  1112. if (ice->cs8427) {
  1113. /* assign channels to iec958 */
  1114. err = snd_cs8427_iec958_build(ice->cs8427,
  1115. pcm->streams[0].substream,
  1116. pcm->streams[1].substream);
  1117. if (err < 0)
  1118. return err;
  1119. }
  1120. if ((err = snd_ice1712_build_pro_mixer(ice)) < 0)
  1121. return err;
  1122. return 0;
  1123. }
  1124. /*
  1125. * Mixer section
  1126. */
  1127. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1128. {
  1129. unsigned int vol = ice->pro_volumes[index];
  1130. unsigned short val = 0;
  1131. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1132. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1133. outb(index, ICEMT(ice, MONITOR_INDEX));
  1134. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1135. }
  1136. #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
  1137. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1138. {
  1139. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1140. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1141. spin_lock_irq(&ice->reg_lock);
  1142. ucontrol->value.integer.value[0] = !((ice->pro_volumes[index] >> 15) & 1);
  1143. ucontrol->value.integer.value[1] = !((ice->pro_volumes[index] >> 31) & 1);
  1144. spin_unlock_irq(&ice->reg_lock);
  1145. return 0;
  1146. }
  1147. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1148. {
  1149. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1150. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1151. unsigned int nval, change;
  1152. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1153. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1154. spin_lock_irq(&ice->reg_lock);
  1155. nval |= ice->pro_volumes[index] & ~0x80008000;
  1156. change = nval != ice->pro_volumes[index];
  1157. ice->pro_volumes[index] = nval;
  1158. snd_ice1712_update_volume(ice, index);
  1159. spin_unlock_irq(&ice->reg_lock);
  1160. return change;
  1161. }
  1162. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1163. {
  1164. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1165. uinfo->count = 2;
  1166. uinfo->value.integer.min = 0;
  1167. uinfo->value.integer.max = 96;
  1168. return 0;
  1169. }
  1170. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1171. {
  1172. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1173. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1174. spin_lock_irq(&ice->reg_lock);
  1175. ucontrol->value.integer.value[0] = (ice->pro_volumes[index] >> 0) & 127;
  1176. ucontrol->value.integer.value[1] = (ice->pro_volumes[index] >> 16) & 127;
  1177. spin_unlock_irq(&ice->reg_lock);
  1178. return 0;
  1179. }
  1180. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1181. {
  1182. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1183. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1184. unsigned int nval, change;
  1185. nval = (ucontrol->value.integer.value[0] & 127) |
  1186. ((ucontrol->value.integer.value[1] & 127) << 16);
  1187. spin_lock_irq(&ice->reg_lock);
  1188. nval |= ice->pro_volumes[index] & ~0x007f007f;
  1189. change = nval != ice->pro_volumes[index];
  1190. ice->pro_volumes[index] = nval;
  1191. snd_ice1712_update_volume(ice, index);
  1192. spin_unlock_irq(&ice->reg_lock);
  1193. return change;
  1194. }
  1195. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1196. static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] __devinitdata = {
  1197. {
  1198. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1199. .name = "Multi Playback Switch",
  1200. .info = snd_ice1712_pro_mixer_switch_info,
  1201. .get = snd_ice1712_pro_mixer_switch_get,
  1202. .put = snd_ice1712_pro_mixer_switch_put,
  1203. .private_value = 0,
  1204. .count = 10,
  1205. },
  1206. {
  1207. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1208. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1209. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1210. .name = "Multi Playback Volume",
  1211. .info = snd_ice1712_pro_mixer_volume_info,
  1212. .get = snd_ice1712_pro_mixer_volume_get,
  1213. .put = snd_ice1712_pro_mixer_volume_put,
  1214. .private_value = 0,
  1215. .count = 10,
  1216. .tlv = { .p = db_scale_playback }
  1217. },
  1218. };
  1219. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch __devinitdata = {
  1220. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1221. .name = "H/W Multi Capture Switch",
  1222. .info = snd_ice1712_pro_mixer_switch_info,
  1223. .get = snd_ice1712_pro_mixer_switch_get,
  1224. .put = snd_ice1712_pro_mixer_switch_put,
  1225. .private_value = 10,
  1226. };
  1227. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch __devinitdata = {
  1228. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1229. .name = SNDRV_CTL_NAME_IEC958("Multi ",CAPTURE,SWITCH),
  1230. .info = snd_ice1712_pro_mixer_switch_info,
  1231. .get = snd_ice1712_pro_mixer_switch_get,
  1232. .put = snd_ice1712_pro_mixer_switch_put,
  1233. .private_value = 18,
  1234. .count = 2,
  1235. };
  1236. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume __devinitdata = {
  1237. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1238. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1239. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1240. .name = "H/W Multi Capture Volume",
  1241. .info = snd_ice1712_pro_mixer_volume_info,
  1242. .get = snd_ice1712_pro_mixer_volume_get,
  1243. .put = snd_ice1712_pro_mixer_volume_put,
  1244. .private_value = 10,
  1245. .tlv = { .p = db_scale_playback }
  1246. };
  1247. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume __devinitdata = {
  1248. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1249. .name = SNDRV_CTL_NAME_IEC958("Multi ",CAPTURE,VOLUME),
  1250. .info = snd_ice1712_pro_mixer_volume_info,
  1251. .get = snd_ice1712_pro_mixer_volume_get,
  1252. .put = snd_ice1712_pro_mixer_volume_put,
  1253. .private_value = 18,
  1254. .count = 2,
  1255. };
  1256. static int __devinit snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1257. {
  1258. struct snd_card *card = ice->card;
  1259. unsigned int idx;
  1260. int err;
  1261. /* multi-channel mixer */
  1262. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1263. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1264. if (err < 0)
  1265. return err;
  1266. }
  1267. if (ice->num_total_adcs > 0) {
  1268. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1269. tmp.count = ice->num_total_adcs;
  1270. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1271. if (err < 0)
  1272. return err;
  1273. }
  1274. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1275. if (err < 0)
  1276. return err;
  1277. if (ice->num_total_adcs > 0) {
  1278. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1279. tmp.count = ice->num_total_adcs;
  1280. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1281. if (err < 0)
  1282. return err;
  1283. }
  1284. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1285. if (err < 0)
  1286. return err;
  1287. /* initialize volumes */
  1288. for (idx = 0; idx < 10; idx++) {
  1289. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1290. snd_ice1712_update_volume(ice, idx);
  1291. }
  1292. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1293. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1294. snd_ice1712_update_volume(ice, idx);
  1295. }
  1296. for (idx = 18; idx < 20; idx++) {
  1297. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1298. snd_ice1712_update_volume(ice, idx);
  1299. }
  1300. return 0;
  1301. }
  1302. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1303. {
  1304. struct snd_ice1712 *ice = ac97->private_data;
  1305. ice->ac97 = NULL;
  1306. }
  1307. static int __devinit snd_ice1712_ac97_mixer(struct snd_ice1712 * ice)
  1308. {
  1309. int err, bus_num = 0;
  1310. struct snd_ac97_template ac97;
  1311. struct snd_ac97_bus *pbus;
  1312. static struct snd_ac97_bus_ops con_ops = {
  1313. .write = snd_ice1712_ac97_write,
  1314. .read = snd_ice1712_ac97_read,
  1315. };
  1316. static struct snd_ac97_bus_ops pro_ops = {
  1317. .write = snd_ice1712_pro_ac97_write,
  1318. .read = snd_ice1712_pro_ac97_read,
  1319. };
  1320. if (ice_has_con_ac97(ice)) {
  1321. if ((err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus)) < 0)
  1322. return err;
  1323. memset(&ac97, 0, sizeof(ac97));
  1324. ac97.private_data = ice;
  1325. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1326. if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0)
  1327. printk(KERN_WARNING "ice1712: cannot initialize ac97 for consumer, skipped\n");
  1328. else {
  1329. if ((err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice))) < 0)
  1330. return err;
  1331. return 0;
  1332. }
  1333. }
  1334. if (! (ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1335. if ((err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus)) < 0)
  1336. return err;
  1337. memset(&ac97, 0, sizeof(ac97));
  1338. ac97.private_data = ice;
  1339. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1340. if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0)
  1341. printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n");
  1342. else
  1343. return 0;
  1344. }
  1345. /* I2S mixer only */
  1346. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1347. return 0;
  1348. }
  1349. /*
  1350. *
  1351. */
  1352. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1353. {
  1354. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1355. }
  1356. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1357. struct snd_info_buffer *buffer)
  1358. {
  1359. struct snd_ice1712 *ice = entry->private_data;
  1360. unsigned int idx;
  1361. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1362. snd_iprintf(buffer, "EEPROM:\n");
  1363. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1364. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1365. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1366. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1367. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1368. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1369. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1370. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1371. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1372. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1373. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1374. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1375. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1376. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1377. for (idx = 0; idx < 4; idx++)
  1378. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1379. for (idx = 0; idx < 4; idx++)
  1380. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1381. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1382. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1383. snd_iprintf(buffer, "\nRegisters:\n");
  1384. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1385. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1386. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1387. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1388. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1389. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1390. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1391. }
  1392. static void __devinit snd_ice1712_proc_init(struct snd_ice1712 * ice)
  1393. {
  1394. struct snd_info_entry *entry;
  1395. if (! snd_card_proc_new(ice->card, "ice1712", &entry))
  1396. snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
  1397. }
  1398. /*
  1399. *
  1400. */
  1401. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1402. struct snd_ctl_elem_info *uinfo)
  1403. {
  1404. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1405. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1406. return 0;
  1407. }
  1408. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1409. struct snd_ctl_elem_value *ucontrol)
  1410. {
  1411. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1412. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1413. return 0;
  1414. }
  1415. static struct snd_kcontrol_new snd_ice1712_eeprom __devinitdata = {
  1416. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1417. .name = "ICE1712 EEPROM",
  1418. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1419. .info = snd_ice1712_eeprom_info,
  1420. .get = snd_ice1712_eeprom_get
  1421. };
  1422. /*
  1423. */
  1424. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1425. struct snd_ctl_elem_info *uinfo)
  1426. {
  1427. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1428. uinfo->count = 1;
  1429. return 0;
  1430. }
  1431. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1432. struct snd_ctl_elem_value *ucontrol)
  1433. {
  1434. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1435. if (ice->spdif.ops.default_get)
  1436. ice->spdif.ops.default_get(ice, ucontrol);
  1437. return 0;
  1438. }
  1439. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1440. struct snd_ctl_elem_value *ucontrol)
  1441. {
  1442. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1443. if (ice->spdif.ops.default_put)
  1444. return ice->spdif.ops.default_put(ice, ucontrol);
  1445. return 0;
  1446. }
  1447. static struct snd_kcontrol_new snd_ice1712_spdif_default __devinitdata =
  1448. {
  1449. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1450. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1451. .info = snd_ice1712_spdif_info,
  1452. .get = snd_ice1712_spdif_default_get,
  1453. .put = snd_ice1712_spdif_default_put
  1454. };
  1455. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1456. struct snd_ctl_elem_value *ucontrol)
  1457. {
  1458. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1459. if (ice->spdif.ops.default_get) {
  1460. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1461. IEC958_AES0_PROFESSIONAL |
  1462. IEC958_AES0_CON_NOT_COPYRIGHT |
  1463. IEC958_AES0_CON_EMPHASIS;
  1464. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1465. IEC958_AES1_CON_CATEGORY;
  1466. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1467. } else {
  1468. ucontrol->value.iec958.status[0] = 0xff;
  1469. ucontrol->value.iec958.status[1] = 0xff;
  1470. ucontrol->value.iec958.status[2] = 0xff;
  1471. ucontrol->value.iec958.status[3] = 0xff;
  1472. ucontrol->value.iec958.status[4] = 0xff;
  1473. }
  1474. return 0;
  1475. }
  1476. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1477. struct snd_ctl_elem_value *ucontrol)
  1478. {
  1479. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1480. if (ice->spdif.ops.default_get) {
  1481. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1482. IEC958_AES0_PROFESSIONAL |
  1483. IEC958_AES0_PRO_FS |
  1484. IEC958_AES0_PRO_EMPHASIS;
  1485. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1486. } else {
  1487. ucontrol->value.iec958.status[0] = 0xff;
  1488. ucontrol->value.iec958.status[1] = 0xff;
  1489. ucontrol->value.iec958.status[2] = 0xff;
  1490. ucontrol->value.iec958.status[3] = 0xff;
  1491. ucontrol->value.iec958.status[4] = 0xff;
  1492. }
  1493. return 0;
  1494. }
  1495. static struct snd_kcontrol_new snd_ice1712_spdif_maskc __devinitdata =
  1496. {
  1497. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1498. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1499. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1500. .info = snd_ice1712_spdif_info,
  1501. .get = snd_ice1712_spdif_maskc_get,
  1502. };
  1503. static struct snd_kcontrol_new snd_ice1712_spdif_maskp __devinitdata =
  1504. {
  1505. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1506. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1507. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
  1508. .info = snd_ice1712_spdif_info,
  1509. .get = snd_ice1712_spdif_maskp_get,
  1510. };
  1511. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1512. struct snd_ctl_elem_value *ucontrol)
  1513. {
  1514. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1515. if (ice->spdif.ops.stream_get)
  1516. ice->spdif.ops.stream_get(ice, ucontrol);
  1517. return 0;
  1518. }
  1519. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1520. struct snd_ctl_elem_value *ucontrol)
  1521. {
  1522. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1523. if (ice->spdif.ops.stream_put)
  1524. return ice->spdif.ops.stream_put(ice, ucontrol);
  1525. return 0;
  1526. }
  1527. static struct snd_kcontrol_new snd_ice1712_spdif_stream __devinitdata =
  1528. {
  1529. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1530. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1531. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1532. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1533. .info = snd_ice1712_spdif_info,
  1534. .get = snd_ice1712_spdif_stream_get,
  1535. .put = snd_ice1712_spdif_stream_put
  1536. };
  1537. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1538. struct snd_ctl_elem_value *ucontrol)
  1539. {
  1540. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1541. unsigned char mask = kcontrol->private_value & 0xff;
  1542. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1543. snd_ice1712_save_gpio_status(ice);
  1544. ucontrol->value.integer.value[0] =
  1545. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1546. snd_ice1712_restore_gpio_status(ice);
  1547. return 0;
  1548. }
  1549. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1550. struct snd_ctl_elem_value *ucontrol)
  1551. {
  1552. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1553. unsigned char mask = kcontrol->private_value & 0xff;
  1554. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1555. unsigned int val, nval;
  1556. if (kcontrol->private_value & (1 << 31))
  1557. return -EPERM;
  1558. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1559. snd_ice1712_save_gpio_status(ice);
  1560. val = snd_ice1712_gpio_read(ice);
  1561. nval |= val & ~mask;
  1562. if (val != nval)
  1563. snd_ice1712_gpio_write(ice, nval);
  1564. snd_ice1712_restore_gpio_status(ice);
  1565. return val != nval;
  1566. }
  1567. /*
  1568. * rate
  1569. */
  1570. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1571. struct snd_ctl_elem_info *uinfo)
  1572. {
  1573. static const char * const texts[] = {
  1574. "8000", /* 0: 6 */
  1575. "9600", /* 1: 3 */
  1576. "11025", /* 2: 10 */
  1577. "12000", /* 3: 2 */
  1578. "16000", /* 4: 5 */
  1579. "22050", /* 5: 9 */
  1580. "24000", /* 6: 1 */
  1581. "32000", /* 7: 4 */
  1582. "44100", /* 8: 8 */
  1583. "48000", /* 9: 0 */
  1584. "64000", /* 10: 15 */
  1585. "88200", /* 11: 11 */
  1586. "96000", /* 12: 7 */
  1587. "IEC958 Input", /* 13: -- */
  1588. };
  1589. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1590. uinfo->count = 1;
  1591. uinfo->value.enumerated.items = 14;
  1592. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1593. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1594. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1595. return 0;
  1596. }
  1597. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1598. struct snd_ctl_elem_value *ucontrol)
  1599. {
  1600. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1601. static const unsigned char xlate[16] = {
  1602. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1603. };
  1604. unsigned char val;
  1605. spin_lock_irq(&ice->reg_lock);
  1606. if (is_spdif_master(ice)) {
  1607. ucontrol->value.enumerated.item[0] = 13;
  1608. } else {
  1609. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1610. if (val == 255) {
  1611. snd_BUG();
  1612. val = 0;
  1613. }
  1614. ucontrol->value.enumerated.item[0] = val;
  1615. }
  1616. spin_unlock_irq(&ice->reg_lock);
  1617. return 0;
  1618. }
  1619. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1620. struct snd_ctl_elem_value *ucontrol)
  1621. {
  1622. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1623. static const unsigned int xrate[13] = {
  1624. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1625. 32000, 44100, 48000, 64000, 88200, 96000
  1626. };
  1627. unsigned char oval;
  1628. int change = 0;
  1629. spin_lock_irq(&ice->reg_lock);
  1630. oval = inb(ICEMT(ice, RATE));
  1631. if (ucontrol->value.enumerated.item[0] == 13) {
  1632. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1633. } else {
  1634. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1635. spin_unlock_irq(&ice->reg_lock);
  1636. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1637. spin_lock_irq(&ice->reg_lock);
  1638. }
  1639. change = inb(ICEMT(ice, RATE)) != oval;
  1640. spin_unlock_irq(&ice->reg_lock);
  1641. if ((oval & ICE1712_SPDIF_MASTER) !=
  1642. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1643. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1644. return change;
  1645. }
  1646. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock __devinitdata = {
  1647. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1648. .name = "Multi Track Internal Clock",
  1649. .info = snd_ice1712_pro_internal_clock_info,
  1650. .get = snd_ice1712_pro_internal_clock_get,
  1651. .put = snd_ice1712_pro_internal_clock_put
  1652. };
  1653. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1654. struct snd_ctl_elem_info *uinfo)
  1655. {
  1656. static const char * const texts[] = {
  1657. "8000", /* 0: 6 */
  1658. "9600", /* 1: 3 */
  1659. "11025", /* 2: 10 */
  1660. "12000", /* 3: 2 */
  1661. "16000", /* 4: 5 */
  1662. "22050", /* 5: 9 */
  1663. "24000", /* 6: 1 */
  1664. "32000", /* 7: 4 */
  1665. "44100", /* 8: 8 */
  1666. "48000", /* 9: 0 */
  1667. "64000", /* 10: 15 */
  1668. "88200", /* 11: 11 */
  1669. "96000", /* 12: 7 */
  1670. // "IEC958 Input", /* 13: -- */
  1671. };
  1672. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1673. uinfo->count = 1;
  1674. uinfo->value.enumerated.items = 13;
  1675. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1676. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1677. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1678. return 0;
  1679. }
  1680. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1681. struct snd_ctl_elem_value *ucontrol)
  1682. {
  1683. int val;
  1684. static const unsigned int xrate[13] = {
  1685. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1686. 32000, 44100, 48000, 64000, 88200, 96000
  1687. };
  1688. for (val = 0; val < 13; val++) {
  1689. if (xrate[val] == PRO_RATE_DEFAULT)
  1690. break;
  1691. }
  1692. ucontrol->value.enumerated.item[0] = val;
  1693. return 0;
  1694. }
  1695. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1696. struct snd_ctl_elem_value *ucontrol)
  1697. {
  1698. static const unsigned int xrate[13] = {
  1699. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1700. 32000, 44100, 48000, 64000, 88200, 96000
  1701. };
  1702. unsigned char oval;
  1703. int change = 0;
  1704. oval = PRO_RATE_DEFAULT;
  1705. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1706. change = PRO_RATE_DEFAULT != oval;
  1707. return change;
  1708. }
  1709. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default __devinitdata = {
  1710. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1711. .name = "Multi Track Internal Clock Default",
  1712. .info = snd_ice1712_pro_internal_clock_default_info,
  1713. .get = snd_ice1712_pro_internal_clock_default_get,
  1714. .put = snd_ice1712_pro_internal_clock_default_put
  1715. };
  1716. #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
  1717. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1718. struct snd_ctl_elem_value *ucontrol)
  1719. {
  1720. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1721. return 0;
  1722. }
  1723. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1724. struct snd_ctl_elem_value *ucontrol)
  1725. {
  1726. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1727. int change = 0, nval;
  1728. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1729. spin_lock_irq(&ice->reg_lock);
  1730. change = PRO_RATE_LOCKED != nval;
  1731. PRO_RATE_LOCKED = nval;
  1732. spin_unlock_irq(&ice->reg_lock);
  1733. return change;
  1734. }
  1735. static struct snd_kcontrol_new snd_ice1712_pro_rate_locking __devinitdata = {
  1736. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1737. .name = "Multi Track Rate Locking",
  1738. .info = snd_ice1712_pro_rate_locking_info,
  1739. .get = snd_ice1712_pro_rate_locking_get,
  1740. .put = snd_ice1712_pro_rate_locking_put
  1741. };
  1742. #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
  1743. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1744. struct snd_ctl_elem_value *ucontrol)
  1745. {
  1746. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1747. return 0;
  1748. }
  1749. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1750. struct snd_ctl_elem_value *ucontrol)
  1751. {
  1752. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1753. int change = 0, nval;
  1754. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1755. spin_lock_irq(&ice->reg_lock);
  1756. change = PRO_RATE_RESET != nval;
  1757. PRO_RATE_RESET = nval;
  1758. spin_unlock_irq(&ice->reg_lock);
  1759. return change;
  1760. }
  1761. static struct snd_kcontrol_new snd_ice1712_pro_rate_reset __devinitdata = {
  1762. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1763. .name = "Multi Track Rate Reset",
  1764. .info = snd_ice1712_pro_rate_reset_info,
  1765. .get = snd_ice1712_pro_rate_reset_get,
  1766. .put = snd_ice1712_pro_rate_reset_put
  1767. };
  1768. /*
  1769. * routing
  1770. */
  1771. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1772. struct snd_ctl_elem_info *uinfo)
  1773. {
  1774. static const char * const texts[] = {
  1775. "PCM Out", /* 0 */
  1776. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1777. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1778. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1779. "Digital Mixer", /* 11 - optional */
  1780. };
  1781. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1782. uinfo->count = 1;
  1783. uinfo->value.enumerated.items =
  1784. snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1785. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1786. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1787. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1788. return 0;
  1789. }
  1790. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1791. struct snd_ctl_elem_value *ucontrol)
  1792. {
  1793. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1794. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1795. unsigned int val, cval;
  1796. spin_lock_irq(&ice->reg_lock);
  1797. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1798. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1799. spin_unlock_irq(&ice->reg_lock);
  1800. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1801. val &= 3;
  1802. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1803. if (val == 1 && idx < 2)
  1804. ucontrol->value.enumerated.item[0] = 11;
  1805. else if (val == 2)
  1806. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1807. else if (val == 3)
  1808. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1809. else
  1810. ucontrol->value.enumerated.item[0] = 0;
  1811. return 0;
  1812. }
  1813. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1814. struct snd_ctl_elem_value *ucontrol)
  1815. {
  1816. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1817. int change, shift;
  1818. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1819. unsigned int val, old_val, nval;
  1820. /* update PSDOUT */
  1821. if (ucontrol->value.enumerated.item[0] >= 11)
  1822. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1823. else if (ucontrol->value.enumerated.item[0] >= 9)
  1824. nval = 3; /* spdif in */
  1825. else if (ucontrol->value.enumerated.item[0] >= 1)
  1826. nval = 2; /* analog in */
  1827. else
  1828. nval = 0; /* pcm */
  1829. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1830. spin_lock_irq(&ice->reg_lock);
  1831. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1832. val &= ~(0x03 << shift);
  1833. val |= nval << shift;
  1834. change = val != old_val;
  1835. if (change)
  1836. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1837. spin_unlock_irq(&ice->reg_lock);
  1838. if (nval < 2) /* dig mixer of pcm */
  1839. return change;
  1840. /* update CAPTURE */
  1841. spin_lock_irq(&ice->reg_lock);
  1842. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1843. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1844. if (nval == 2) { /* analog in */
  1845. nval = ucontrol->value.enumerated.item[0] - 1;
  1846. val &= ~(0x07 << shift);
  1847. val |= nval << shift;
  1848. } else { /* spdif in */
  1849. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1850. val &= ~(0x08 << shift);
  1851. val |= nval << shift;
  1852. }
  1853. if (val != old_val) {
  1854. change = 1;
  1855. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1856. }
  1857. spin_unlock_irq(&ice->reg_lock);
  1858. return change;
  1859. }
  1860. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1861. struct snd_ctl_elem_value *ucontrol)
  1862. {
  1863. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1864. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1865. unsigned int val, cval;
  1866. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1867. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1868. val = (val >> (idx * 2)) & 0x03;
  1869. if (val == 1)
  1870. ucontrol->value.enumerated.item[0] = 11;
  1871. else if (val == 2)
  1872. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1873. else if (val == 3)
  1874. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1875. else
  1876. ucontrol->value.enumerated.item[0] = 0;
  1877. return 0;
  1878. }
  1879. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1880. struct snd_ctl_elem_value *ucontrol)
  1881. {
  1882. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1883. int change, shift;
  1884. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1885. unsigned int val, old_val, nval;
  1886. /* update SPDOUT */
  1887. spin_lock_irq(&ice->reg_lock);
  1888. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1889. if (ucontrol->value.enumerated.item[0] >= 11)
  1890. nval = 1;
  1891. else if (ucontrol->value.enumerated.item[0] >= 9)
  1892. nval = 3;
  1893. else if (ucontrol->value.enumerated.item[0] >= 1)
  1894. nval = 2;
  1895. else
  1896. nval = 0;
  1897. shift = idx * 2;
  1898. val &= ~(0x03 << shift);
  1899. val |= nval << shift;
  1900. shift = idx * 4 + 8;
  1901. if (nval == 2) {
  1902. nval = ucontrol->value.enumerated.item[0] - 1;
  1903. val &= ~(0x07 << shift);
  1904. val |= nval << shift;
  1905. } else if (nval == 3) {
  1906. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1907. val &= ~(0x08 << shift);
  1908. val |= nval << shift;
  1909. }
  1910. change = val != old_val;
  1911. if (change)
  1912. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1913. spin_unlock_irq(&ice->reg_lock);
  1914. return change;
  1915. }
  1916. static struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route __devinitdata = {
  1917. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1918. .name = "H/W Playback Route",
  1919. .info = snd_ice1712_pro_route_info,
  1920. .get = snd_ice1712_pro_route_analog_get,
  1921. .put = snd_ice1712_pro_route_analog_put,
  1922. };
  1923. static struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route __devinitdata = {
  1924. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1925. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Route",
  1926. .info = snd_ice1712_pro_route_info,
  1927. .get = snd_ice1712_pro_route_spdif_get,
  1928. .put = snd_ice1712_pro_route_spdif_put,
  1929. .count = 2,
  1930. };
  1931. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1932. struct snd_ctl_elem_info *uinfo)
  1933. {
  1934. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1935. uinfo->count = 1;
  1936. uinfo->value.integer.min = 0;
  1937. uinfo->value.integer.max = 255;
  1938. return 0;
  1939. }
  1940. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1941. struct snd_ctl_elem_value *ucontrol)
  1942. {
  1943. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1944. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1945. return 0;
  1946. }
  1947. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1948. struct snd_ctl_elem_value *ucontrol)
  1949. {
  1950. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1951. int change;
  1952. spin_lock_irq(&ice->reg_lock);
  1953. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1954. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1955. spin_unlock_irq(&ice->reg_lock);
  1956. return change;
  1957. }
  1958. static struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate __devinitdata = {
  1959. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1960. .name = "Multi Track Volume Rate",
  1961. .info = snd_ice1712_pro_volume_rate_info,
  1962. .get = snd_ice1712_pro_volume_rate_get,
  1963. .put = snd_ice1712_pro_volume_rate_put
  1964. };
  1965. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  1966. struct snd_ctl_elem_info *uinfo)
  1967. {
  1968. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1969. uinfo->count = 22;
  1970. uinfo->value.integer.min = 0;
  1971. uinfo->value.integer.max = 255;
  1972. return 0;
  1973. }
  1974. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  1975. struct snd_ctl_elem_value *ucontrol)
  1976. {
  1977. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1978. int idx;
  1979. spin_lock_irq(&ice->reg_lock);
  1980. for (idx = 0; idx < 22; idx++) {
  1981. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  1982. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  1983. }
  1984. spin_unlock_irq(&ice->reg_lock);
  1985. return 0;
  1986. }
  1987. static struct snd_kcontrol_new snd_ice1712_mixer_pro_peak __devinitdata = {
  1988. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1989. .name = "Multi Track Peak",
  1990. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1991. .info = snd_ice1712_pro_peak_info,
  1992. .get = snd_ice1712_pro_peak_get
  1993. };
  1994. /*
  1995. *
  1996. */
  1997. /*
  1998. * list of available boards
  1999. */
  2000. static struct snd_ice1712_card_info *card_tables[] __devinitdata = {
  2001. snd_ice1712_hoontech_cards,
  2002. snd_ice1712_delta_cards,
  2003. snd_ice1712_ews_cards,
  2004. NULL,
  2005. };
  2006. static unsigned char __devinit snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  2007. unsigned char dev,
  2008. unsigned char addr)
  2009. {
  2010. long t = 0x10000;
  2011. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  2012. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  2013. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  2014. return inb(ICEREG(ice, I2C_DATA));
  2015. }
  2016. static int __devinit snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  2017. const char *modelname)
  2018. {
  2019. int dev = 0xa0; /* EEPROM device address */
  2020. unsigned int i, size;
  2021. struct snd_ice1712_card_info * const *tbl, *c;
  2022. if (! modelname || ! *modelname) {
  2023. ice->eeprom.subvendor = 0;
  2024. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  2025. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  2026. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  2027. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  2028. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  2029. if (ice->eeprom.subvendor == 0 ||
  2030. ice->eeprom.subvendor == (unsigned int)-1) {
  2031. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  2032. u16 vendor, device;
  2033. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  2034. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2035. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2036. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  2037. printk(KERN_ERR "ice1712: No valid ID is found\n");
  2038. return -ENXIO;
  2039. }
  2040. }
  2041. }
  2042. for (tbl = card_tables; *tbl; tbl++) {
  2043. for (c = *tbl; c->subvendor; c++) {
  2044. if (modelname && c->model && ! strcmp(modelname, c->model)) {
  2045. printk(KERN_INFO "ice1712: Using board model %s\n", c->name);
  2046. ice->eeprom.subvendor = c->subvendor;
  2047. } else if (c->subvendor != ice->eeprom.subvendor)
  2048. continue;
  2049. if (! c->eeprom_size || ! c->eeprom_data)
  2050. goto found;
  2051. /* if the EEPROM is given by the driver, use it */
  2052. snd_printdd("using the defined eeprom..\n");
  2053. ice->eeprom.version = 1;
  2054. ice->eeprom.size = c->eeprom_size + 6;
  2055. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2056. goto read_skipped;
  2057. }
  2058. }
  2059. printk(KERN_WARNING "ice1712: No matching model found for ID 0x%x\n",
  2060. ice->eeprom.subvendor);
  2061. found:
  2062. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2063. if (ice->eeprom.size < 6)
  2064. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2065. else if (ice->eeprom.size > 32) {
  2066. snd_printk(KERN_ERR "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2067. return -EIO;
  2068. }
  2069. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2070. if (ice->eeprom.version != 1) {
  2071. snd_printk(KERN_ERR "invalid EEPROM version %i\n",
  2072. ice->eeprom.version);
  2073. /* return -EIO; */
  2074. }
  2075. size = ice->eeprom.size - 6;
  2076. for (i = 0; i < size; i++)
  2077. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2078. read_skipped:
  2079. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2080. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2081. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2082. return 0;
  2083. }
  2084. static int __devinit snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2085. {
  2086. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2087. udelay(200);
  2088. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2089. udelay(200);
  2090. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2091. !ice->dxr_enable)
  2092. /* Set eeprom value to limit active ADCs and DACs to 6;
  2093. * Also disable AC97 as no hardware in standard 6fire card/box
  2094. * Note: DXR extensions are not currently supported
  2095. */
  2096. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2097. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2098. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2099. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2100. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2101. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
  2102. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2103. ice->gpio.direction = ice->eeprom.gpiodir;
  2104. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2105. ice->eeprom.gpiomask);
  2106. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2107. ice->eeprom.gpiodir);
  2108. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2109. ice->eeprom.gpiostate);
  2110. } else {
  2111. ice->gpio.write_mask = 0xc0;
  2112. ice->gpio.direction = 0xff;
  2113. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2114. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2115. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2116. ICE1712_STDSP24_CLOCK_BIT);
  2117. }
  2118. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2119. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2120. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2121. udelay(100);
  2122. outb(0, ICEREG(ice, AC97_CMD));
  2123. udelay(200);
  2124. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2125. }
  2126. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2127. return 0;
  2128. }
  2129. int __devinit snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2130. {
  2131. int err;
  2132. struct snd_kcontrol *kctl;
  2133. snd_assert(ice->pcm_pro != NULL, return -EIO);
  2134. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
  2135. if (err < 0)
  2136. return err;
  2137. kctl->id.device = ice->pcm_pro->device;
  2138. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
  2139. if (err < 0)
  2140. return err;
  2141. kctl->id.device = ice->pcm_pro->device;
  2142. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
  2143. if (err < 0)
  2144. return err;
  2145. kctl->id.device = ice->pcm_pro->device;
  2146. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
  2147. if (err < 0)
  2148. return err;
  2149. kctl->id.device = ice->pcm_pro->device;
  2150. ice->spdif.stream_ctl = kctl;
  2151. return 0;
  2152. }
  2153. static int __devinit snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2154. {
  2155. int err;
  2156. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2157. if (err < 0)
  2158. return err;
  2159. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2160. if (err < 0)
  2161. return err;
  2162. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2163. if (err < 0)
  2164. return err;
  2165. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2166. if (err < 0)
  2167. return err;
  2168. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2169. if (err < 0)
  2170. return err;
  2171. if (ice->num_total_dacs > 0) {
  2172. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2173. tmp.count = ice->num_total_dacs;
  2174. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2175. if (err < 0)
  2176. return err;
  2177. }
  2178. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2179. if (err < 0)
  2180. return err;
  2181. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2182. if (err < 0)
  2183. return err;
  2184. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2185. if (err < 0)
  2186. return err;
  2187. return 0;
  2188. }
  2189. static int snd_ice1712_free(struct snd_ice1712 *ice)
  2190. {
  2191. if (! ice->port)
  2192. goto __hw_end;
  2193. /* mask all interrupts */
  2194. outb(0xc0, ICEMT(ice, IRQ));
  2195. outb(0xff, ICEREG(ice, IRQMASK));
  2196. /* --- */
  2197. __hw_end:
  2198. if (ice->irq >= 0) {
  2199. synchronize_irq(ice->irq);
  2200. free_irq(ice->irq, ice);
  2201. }
  2202. if (ice->port)
  2203. pci_release_regions(ice->pci);
  2204. snd_ice1712_akm4xxx_free(ice);
  2205. pci_disable_device(ice->pci);
  2206. kfree(ice);
  2207. return 0;
  2208. }
  2209. static int snd_ice1712_dev_free(struct snd_device *device)
  2210. {
  2211. struct snd_ice1712 *ice = device->device_data;
  2212. return snd_ice1712_free(ice);
  2213. }
  2214. static int __devinit snd_ice1712_create(struct snd_card *card,
  2215. struct pci_dev *pci,
  2216. const char *modelname,
  2217. int omni,
  2218. int cs8427_timeout,
  2219. int dxr_enable,
  2220. struct snd_ice1712 ** r_ice1712)
  2221. {
  2222. struct snd_ice1712 *ice;
  2223. int err;
  2224. static struct snd_device_ops ops = {
  2225. .dev_free = snd_ice1712_dev_free,
  2226. };
  2227. *r_ice1712 = NULL;
  2228. /* enable PCI device */
  2229. if ((err = pci_enable_device(pci)) < 0)
  2230. return err;
  2231. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2232. if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
  2233. pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
  2234. snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
  2235. pci_disable_device(pci);
  2236. return -ENXIO;
  2237. }
  2238. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2239. if (ice == NULL) {
  2240. pci_disable_device(pci);
  2241. return -ENOMEM;
  2242. }
  2243. ice->omni = omni ? 1 : 0;
  2244. if (cs8427_timeout < 1)
  2245. cs8427_timeout = 1;
  2246. else if (cs8427_timeout > 1000)
  2247. cs8427_timeout = 1000;
  2248. ice->cs8427_timeout = cs8427_timeout;
  2249. ice->dxr_enable = dxr_enable;
  2250. spin_lock_init(&ice->reg_lock);
  2251. mutex_init(&ice->gpio_mutex);
  2252. mutex_init(&ice->i2c_mutex);
  2253. mutex_init(&ice->open_mutex);
  2254. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2255. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2256. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2257. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2258. ice->spdif.cs8403_bits =
  2259. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2260. 0x10 | /* no emphasis */
  2261. 0x20); /* PCM encoder/decoder */
  2262. ice->card = card;
  2263. ice->pci = pci;
  2264. ice->irq = -1;
  2265. pci_set_master(pci);
  2266. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2267. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2268. snd_ice1712_proc_init(ice);
  2269. synchronize_irq(pci->irq);
  2270. if ((err = pci_request_regions(pci, "ICE1712")) < 0) {
  2271. kfree(ice);
  2272. pci_disable_device(pci);
  2273. return err;
  2274. }
  2275. ice->port = pci_resource_start(pci, 0);
  2276. ice->ddma_port = pci_resource_start(pci, 1);
  2277. ice->dmapath_port = pci_resource_start(pci, 2);
  2278. ice->profi_port = pci_resource_start(pci, 3);
  2279. if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
  2280. "ICE1712", ice)) {
  2281. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2282. snd_ice1712_free(ice);
  2283. return -EIO;
  2284. }
  2285. ice->irq = pci->irq;
  2286. if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
  2287. snd_ice1712_free(ice);
  2288. return -EIO;
  2289. }
  2290. if (snd_ice1712_chip_init(ice) < 0) {
  2291. snd_ice1712_free(ice);
  2292. return -EIO;
  2293. }
  2294. /* unmask used interrupts */
  2295. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2296. ICE1712_IRQ_MPU2 : 0) |
  2297. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2298. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2299. ICEREG(ice, IRQMASK));
  2300. outb(0x00, ICEMT(ice, IRQ));
  2301. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops)) < 0) {
  2302. snd_ice1712_free(ice);
  2303. return err;
  2304. }
  2305. snd_card_set_dev(card, &pci->dev);
  2306. *r_ice1712 = ice;
  2307. return 0;
  2308. }
  2309. /*
  2310. *
  2311. * Registration
  2312. *
  2313. */
  2314. static struct snd_ice1712_card_info no_matched __devinitdata;
  2315. static int __devinit snd_ice1712_probe(struct pci_dev *pci,
  2316. const struct pci_device_id *pci_id)
  2317. {
  2318. static int dev;
  2319. struct snd_card *card;
  2320. struct snd_ice1712 *ice;
  2321. int pcm_dev = 0, err;
  2322. struct snd_ice1712_card_info * const *tbl, *c;
  2323. if (dev >= SNDRV_CARDS)
  2324. return -ENODEV;
  2325. if (!enable[dev]) {
  2326. dev++;
  2327. return -ENOENT;
  2328. }
  2329. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  2330. if (card == NULL)
  2331. return -ENOMEM;
  2332. strcpy(card->driver, "ICE1712");
  2333. strcpy(card->shortname, "ICEnsemble ICE1712");
  2334. if ((err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2335. cs8427_timeout[dev], dxr_enable[dev],
  2336. &ice)) < 0) {
  2337. snd_card_free(card);
  2338. return err;
  2339. }
  2340. for (tbl = card_tables; *tbl; tbl++) {
  2341. for (c = *tbl; c->subvendor; c++) {
  2342. if (c->subvendor == ice->eeprom.subvendor) {
  2343. strcpy(card->shortname, c->name);
  2344. if (c->driver) /* specific driver? */
  2345. strcpy(card->driver, c->driver);
  2346. if (c->chip_init) {
  2347. if ((err = c->chip_init(ice)) < 0) {
  2348. snd_card_free(card);
  2349. return err;
  2350. }
  2351. }
  2352. goto __found;
  2353. }
  2354. }
  2355. }
  2356. c = &no_matched;
  2357. __found:
  2358. if ((err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL)) < 0) {
  2359. snd_card_free(card);
  2360. return err;
  2361. }
  2362. if (ice_has_con_ac97(ice))
  2363. if ((err = snd_ice1712_pcm(ice, pcm_dev++, NULL)) < 0) {
  2364. snd_card_free(card);
  2365. return err;
  2366. }
  2367. if ((err = snd_ice1712_ac97_mixer(ice)) < 0) {
  2368. snd_card_free(card);
  2369. return err;
  2370. }
  2371. if ((err = snd_ice1712_build_controls(ice)) < 0) {
  2372. snd_card_free(card);
  2373. return err;
  2374. }
  2375. if (c->build_controls) {
  2376. if ((err = c->build_controls(ice)) < 0) {
  2377. snd_card_free(card);
  2378. return err;
  2379. }
  2380. }
  2381. if (ice_has_con_ac97(ice))
  2382. if ((err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL)) < 0) {
  2383. snd_card_free(card);
  2384. return err;
  2385. }
  2386. if (! c->no_mpu401) {
  2387. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2388. ICEREG(ice, MPU1_CTRL),
  2389. (c->mpu401_1_info_flags |
  2390. MPU401_INFO_INTEGRATED),
  2391. ice->irq, 0,
  2392. &ice->rmidi[0])) < 0) {
  2393. snd_card_free(card);
  2394. return err;
  2395. }
  2396. if (c->mpu401_1_name)
  2397. /* Prefered name available in card_info */
  2398. snprintf(ice->rmidi[0]->name,
  2399. sizeof(ice->rmidi[0]->name),
  2400. "%s %d", c->mpu401_1_name, card->number);
  2401. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2402. /* 2nd port used */
  2403. if ((err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2404. ICEREG(ice, MPU2_CTRL),
  2405. (c->mpu401_2_info_flags |
  2406. MPU401_INFO_INTEGRATED),
  2407. ice->irq, 0,
  2408. &ice->rmidi[1])) < 0) {
  2409. snd_card_free(card);
  2410. return err;
  2411. }
  2412. if (c->mpu401_2_name)
  2413. /* Prefered name available in card_info */
  2414. snprintf(ice->rmidi[1]->name,
  2415. sizeof(ice->rmidi[1]->name),
  2416. "%s %d", c->mpu401_2_name,
  2417. card->number);
  2418. }
  2419. }
  2420. snd_ice1712_set_input_clock_source(ice, 0);
  2421. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2422. card->shortname, ice->port, ice->irq);
  2423. if ((err = snd_card_register(card)) < 0) {
  2424. snd_card_free(card);
  2425. return err;
  2426. }
  2427. pci_set_drvdata(pci, card);
  2428. dev++;
  2429. return 0;
  2430. }
  2431. static void __devexit snd_ice1712_remove(struct pci_dev *pci)
  2432. {
  2433. snd_card_free(pci_get_drvdata(pci));
  2434. pci_set_drvdata(pci, NULL);
  2435. }
  2436. static struct pci_driver driver = {
  2437. .name = "ICE1712",
  2438. .id_table = snd_ice1712_ids,
  2439. .probe = snd_ice1712_probe,
  2440. .remove = __devexit_p(snd_ice1712_remove),
  2441. };
  2442. static int __init alsa_card_ice1712_init(void)
  2443. {
  2444. return pci_register_driver(&driver);
  2445. }
  2446. static void __exit alsa_card_ice1712_exit(void)
  2447. {
  2448. pci_unregister_driver(&driver);
  2449. }
  2450. module_init(alsa_card_ice1712_init)
  2451. module_exit(alsa_card_ice1712_exit)