blackfin.h 5.5 KB

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  1. /*
  2. * File: include/asm-blackfin/mach-bf548/blackfin.h
  3. * Based on:
  4. * Author:
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Rev:
  10. *
  11. * Modified:
  12. *
  13. *
  14. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  15. *
  16. * This program is free software; you can redistribute it and/or modify
  17. * it under the terms of the GNU General Public License as published by
  18. * the Free Software Foundation; either version 2, or (at your option)
  19. * any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; see the file COPYING.
  28. * If not, write to the Free Software Foundation,
  29. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30. */
  31. #ifndef _MACH_BLACKFIN_H_
  32. #define _MACH_BLACKFIN_H_
  33. #define BF548_FAMILY
  34. #include "bf548.h"
  35. #include "mem_map.h"
  36. #include "anomaly.h"
  37. #ifdef CONFIG_BF542
  38. #include "defBF542.h"
  39. #endif
  40. #ifdef CONFIG_BF544
  41. #include "defBF544.h"
  42. #endif
  43. #ifdef CONFIG_BF548
  44. #include "defBF548.h"
  45. #endif
  46. #ifdef CONFIG_BF549
  47. #include "defBF549.h"
  48. #endif
  49. #if !defined(__ASSEMBLY__)
  50. #ifdef CONFIG_BF542
  51. #include "cdefBF542.h"
  52. #endif
  53. #ifdef CONFIG_BF544
  54. #include "cdefBF544.h"
  55. #endif
  56. #ifdef CONFIG_BF548
  57. #include "cdefBF548.h"
  58. #endif
  59. #ifdef CONFIG_BF549
  60. #include "cdefBF549.h"
  61. #endif
  62. /* UART 1*/
  63. #define bfin_read_UART_THR() bfin_read_UART1_THR()
  64. #define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
  65. #define bfin_read_UART_RBR() bfin_read_UART1_RBR()
  66. #define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
  67. #define bfin_read_UART_DLL() bfin_read_UART1_DLL()
  68. #define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
  69. #define bfin_read_UART_IER() bfin_read_UART1_IER()
  70. #define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
  71. #define bfin_read_UART_DLH() bfin_read_UART1_DLH()
  72. #define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
  73. #define bfin_read_UART_IIR() bfin_read_UART1_IIR()
  74. #define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
  75. #define bfin_read_UART_LCR() bfin_read_UART1_LCR()
  76. #define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
  77. #define bfin_read_UART_MCR() bfin_read_UART1_MCR()
  78. #define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
  79. #define bfin_read_UART_LSR() bfin_read_UART1_LSR()
  80. #define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
  81. #define bfin_read_UART_SCR() bfin_read_UART1_SCR()
  82. #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
  83. #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
  84. #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
  85. #endif
  86. /* MAP used DEFINES from BF533 to BF54x - so we don't need to change
  87. * them in the driver, kernel, etc. */
  88. /* UART_IIR Register */
  89. #define STATUS(x) ((x << 1) & 0x06)
  90. #define STATUS_P1 0x02
  91. #define STATUS_P0 0x01
  92. /* UART 0*/
  93. /* DMA Channnel */
  94. #define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
  95. #define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
  96. #define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
  97. #define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val)
  98. #define CH_UART_RX CH_UART1_RX
  99. #define CH_UART_TX CH_UART1_TX
  100. /* System Interrupt Controller */
  101. #define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX()
  102. #define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val)
  103. #define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX()
  104. #define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val)
  105. #define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR()
  106. #define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val)
  107. #define IRQ_UART_RX IRQ_UART1_RX
  108. #define IRQ_UART_TX IRQ_UART1_TX
  109. #define IRQ_UART_ERROR IRQ_UART1_ERROR
  110. /* MMR Registers*/
  111. #define bfin_read_UART_THR() bfin_read_UART1_THR()
  112. #define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
  113. #define bfin_read_UART_RBR() bfin_read_UART1_RBR()
  114. #define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
  115. #define bfin_read_UART_DLL() bfin_read_UART1_DLL()
  116. #define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
  117. #define bfin_read_UART_IER() bfin_read_UART1_IER()
  118. #define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
  119. #define bfin_read_UART_DLH() bfin_read_UART1_DLH()
  120. #define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
  121. #define bfin_read_UART_IIR() bfin_read_UART1_IIR()
  122. #define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
  123. #define bfin_read_UART_LCR() bfin_read_UART1_LCR()
  124. #define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
  125. #define bfin_read_UART_MCR() bfin_read_UART1_MCR()
  126. #define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
  127. #define bfin_read_UART_LSR() bfin_read_UART1_LSR()
  128. #define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
  129. #define bfin_read_UART_SCR() bfin_read_UART1_SCR()
  130. #define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
  131. #define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
  132. #define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
  133. #define UART_THR UART1_THR
  134. #define UART_RBR UART1_RBR
  135. #define UART_DLL UART1_DLL
  136. #define UART_IER UART1_IER
  137. #define UART_DLH UART1_DLH
  138. #define UART_IIR UART1_IIR
  139. #define UART_LCR UART1_LCR
  140. #define UART_MCR UART1_MCR
  141. #define UART_LSR UART1_LSR
  142. #define UART_SCR UART1_SCR
  143. #define UART_GCTL UART1_GCTL
  144. /* PLL_DIV Masks */
  145. #define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
  146. #define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
  147. #define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
  148. #define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
  149. #endif