cplbinit.h 2.9 KB

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  1. /*
  2. * File: include/asm-blackfin/cplbinit.h
  3. * Based on:
  4. * Author:
  5. *
  6. * Created:
  7. * Description:
  8. *
  9. * Modified:
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <asm/blackfin.h>
  30. #include <asm/cplb.h>
  31. #define INITIAL_T 0x1
  32. #define SWITCH_T 0x2
  33. #define I_CPLB 0x4
  34. #define D_CPLB 0x8
  35. #define IN_KERNEL 1
  36. enum
  37. {ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
  38. struct cplb_desc {
  39. u32 start; /* start address */
  40. u32 end; /* end address */
  41. u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
  42. u16 attr;/* attributes */
  43. u16 i_conf;/* I-CPLB DATA */
  44. u16 d_conf;/* D-CPLB DATA */
  45. u16 valid;/* valid */
  46. const s8 name[30];/* name */
  47. };
  48. struct cplb_tab {
  49. u_long *tab;
  50. u16 pos;
  51. u16 size;
  52. };
  53. extern u_long icplb_table[MAX_CPLBS+1];
  54. extern u_long dcplb_table[MAX_CPLBS+1];
  55. /* Till here we are discussing about the static memory management model.
  56. * However, the operating envoronments commonly define more CPLB
  57. * descriptors to cover the entire addressable memory than will fit into
  58. * the available on-chip 16 CPLB MMRs. When this happens, the below table
  59. * will be used which will hold all the potentially required CPLB descriptors
  60. *
  61. * This is how Page descriptor Table is implemented in uClinux/Blackfin.
  62. */
  63. #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  64. extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
  65. extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
  66. #ifdef CONFIG_CPLB_INFO
  67. extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
  68. extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
  69. #endif /* CONFIG_CPLB_INFO */
  70. #else
  71. extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
  72. extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
  73. #ifdef CONFIG_CPLB_INFO
  74. extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
  75. extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
  76. #endif /* CONFIG_CPLB_INFO */
  77. #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
  78. extern unsigned long reserved_mem_dcache_on;
  79. extern unsigned long reserved_mem_icache_on;
  80. extern void generate_cpl_tables(void);