system.h 2.1 KB

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  1. /* linux/include/asm-arm/arch-s3c2410/system.h
  2. *
  3. * Copyright (c) 2003 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 - System function defines and includes
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <asm/hardware.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/map.h>
  15. #include <asm/arch/idle.h>
  16. #include <asm/arch/reset.h>
  17. #include <asm/plat-s3c/regs-watchdog.h>
  18. #include <asm/arch/regs-clock.h>
  19. void (*s3c24xx_idle)(void);
  20. void (*s3c24xx_reset_hook)(void);
  21. void s3c24xx_default_idle(void)
  22. {
  23. unsigned long tmp;
  24. int i;
  25. /* idle the system by using the idle mode which will wait for an
  26. * interrupt to happen before restarting the system.
  27. */
  28. /* Warning: going into idle state upsets jtag scanning */
  29. __raw_writel(__raw_readl(S3C2410_CLKCON) | S3C2410_CLKCON_IDLE,
  30. S3C2410_CLKCON);
  31. /* the samsung port seems to do a loop and then unset idle.. */
  32. for (i = 0; i < 50; i++) {
  33. tmp += __raw_readl(S3C2410_CLKCON); /* ensure loop not optimised out */
  34. }
  35. /* this bit is not cleared on re-start... */
  36. __raw_writel(__raw_readl(S3C2410_CLKCON) & ~S3C2410_CLKCON_IDLE,
  37. S3C2410_CLKCON);
  38. }
  39. static void arch_idle(void)
  40. {
  41. if (s3c24xx_idle != NULL)
  42. (s3c24xx_idle)();
  43. else
  44. s3c24xx_default_idle();
  45. }
  46. static void
  47. arch_reset(char mode)
  48. {
  49. if (mode == 's') {
  50. cpu_reset(0);
  51. }
  52. if (s3c24xx_reset_hook)
  53. s3c24xx_reset_hook();
  54. printk("arch_reset: attempting watchdog reset\n");
  55. __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
  56. /* put initial values into count and data */
  57. __raw_writel(0x100, S3C2410_WTCNT);
  58. __raw_writel(0x100, S3C2410_WTDAT);
  59. /* set the watchdog to go and reset... */
  60. __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
  61. S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
  62. /* wait for reset to assert... */
  63. mdelay(5000);
  64. printk(KERN_ERR "Watchdog reset failed to assert reset\n");
  65. /* we'll take a jump through zero as a poor second */
  66. cpu_reset(0);
  67. }