xilinxfb.c 14 KB

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  1. /*
  2. * xilinxfb.c
  3. *
  4. * Xilinx TFT LCD frame buffer driver
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * source@mvista.com
  8. *
  9. * 2002-2007 (c) MontaVista Software, Inc.
  10. * 2007 (c) Secret Lab Technologies, Ltd.
  11. *
  12. * This file is licensed under the terms of the GNU General Public License
  13. * version 2. This program is licensed "as is" without any warranty of any
  14. * kind, whether express or implied.
  15. */
  16. /*
  17. * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
  18. * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
  19. * was based on skeletonfb.c, Skeleton for a frame buffer device by
  20. * Geert Uytterhoeven.
  21. */
  22. #include <linux/device.h>
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/version.h>
  26. #include <linux/errno.h>
  27. #include <linux/string.h>
  28. #include <linux/mm.h>
  29. #include <linux/fb.h>
  30. #include <linux/init.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/platform_device.h>
  33. #if defined(CONFIG_OF)
  34. #include <linux/of_device.h>
  35. #include <linux/of_platform.h>
  36. #endif
  37. #include <asm/io.h>
  38. #include <linux/xilinxfb.h>
  39. #define DRIVER_NAME "xilinxfb"
  40. #define DRIVER_DESCRIPTION "Xilinx TFT LCD frame buffer driver"
  41. /*
  42. * Xilinx calls it "PLB TFT LCD Controller" though it can also be used for
  43. * the VGA port on the Xilinx ML40x board. This is a hardware display controller
  44. * for a 640x480 resolution TFT or VGA screen.
  45. *
  46. * The interface to the framebuffer is nice and simple. There are two
  47. * control registers. The first tells the LCD interface where in memory
  48. * the frame buffer is (only the 11 most significant bits are used, so
  49. * don't start thinking about scrolling). The second allows the LCD to
  50. * be turned on or off as well as rotated 180 degrees.
  51. */
  52. #define NUM_REGS 2
  53. #define REG_FB_ADDR 0
  54. #define REG_CTRL 1
  55. #define REG_CTRL_ENABLE 0x0001
  56. #define REG_CTRL_ROTATE 0x0002
  57. /*
  58. * The hardware only handles a single mode: 640x480 24 bit true
  59. * color. Each pixel gets a word (32 bits) of memory. Within each word,
  60. * the 8 most significant bits are ignored, the next 8 bits are the red
  61. * level, the next 8 bits are the green level and the 8 least
  62. * significant bits are the blue level. Each row of the LCD uses 1024
  63. * words, but only the first 640 pixels are displayed with the other 384
  64. * words being ignored. There are 480 rows.
  65. */
  66. #define BYTES_PER_PIXEL 4
  67. #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
  68. #define RED_SHIFT 16
  69. #define GREEN_SHIFT 8
  70. #define BLUE_SHIFT 0
  71. #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
  72. /*
  73. * Default xilinxfb configuration
  74. */
  75. static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
  76. .xres = 640,
  77. .yres = 480,
  78. .xvirt = 1024,
  79. .yvirt = 480,
  80. };
  81. /*
  82. * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
  83. */
  84. static struct fb_fix_screeninfo xilinx_fb_fix = {
  85. .id = "Xilinx",
  86. .type = FB_TYPE_PACKED_PIXELS,
  87. .visual = FB_VISUAL_TRUECOLOR,
  88. .accel = FB_ACCEL_NONE
  89. };
  90. static struct fb_var_screeninfo xilinx_fb_var = {
  91. .bits_per_pixel = BITS_PER_PIXEL,
  92. .red = { RED_SHIFT, 8, 0 },
  93. .green = { GREEN_SHIFT, 8, 0 },
  94. .blue = { BLUE_SHIFT, 8, 0 },
  95. .transp = { 0, 0, 0 },
  96. .activate = FB_ACTIVATE_NOW
  97. };
  98. struct xilinxfb_drvdata {
  99. struct fb_info info; /* FB driver info record */
  100. u32 regs_phys; /* phys. address of the control registers */
  101. u32 __iomem *regs; /* virt. address of the control registers */
  102. void *fb_virt; /* virt. address of the frame buffer */
  103. dma_addr_t fb_phys; /* phys. address of the frame buffer */
  104. int fb_alloced; /* Flag, was the fb memory alloced? */
  105. u32 reg_ctrl_default;
  106. u32 pseudo_palette[PALETTE_ENTRIES_NO];
  107. /* Fake palette of 16 colors */
  108. };
  109. #define to_xilinxfb_drvdata(_info) \
  110. container_of(_info, struct xilinxfb_drvdata, info)
  111. /*
  112. * The LCD controller has DCR interface to its registers, but all
  113. * the boards and configurations the driver has been tested with
  114. * use opb2dcr bridge. So the registers are seen as memory mapped.
  115. * This macro is to make it simple to add the direct DCR access
  116. * when it's needed.
  117. */
  118. #define xilinx_fb_out_be32(driverdata, offset, val) \
  119. out_be32(driverdata->regs + offset, val)
  120. static int
  121. xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
  122. unsigned transp, struct fb_info *fbi)
  123. {
  124. u32 *palette = fbi->pseudo_palette;
  125. if (regno >= PALETTE_ENTRIES_NO)
  126. return -EINVAL;
  127. if (fbi->var.grayscale) {
  128. /* Convert color to grayscale.
  129. * grayscale = 0.30*R + 0.59*G + 0.11*B */
  130. red = green = blue =
  131. (red * 77 + green * 151 + blue * 28 + 127) >> 8;
  132. }
  133. /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
  134. /* We only handle 8 bits of each color. */
  135. red >>= 8;
  136. green >>= 8;
  137. blue >>= 8;
  138. palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
  139. (blue << BLUE_SHIFT);
  140. return 0;
  141. }
  142. static int
  143. xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
  144. {
  145. struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
  146. switch (blank_mode) {
  147. case FB_BLANK_UNBLANK:
  148. /* turn on panel */
  149. xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
  150. break;
  151. case FB_BLANK_NORMAL:
  152. case FB_BLANK_VSYNC_SUSPEND:
  153. case FB_BLANK_HSYNC_SUSPEND:
  154. case FB_BLANK_POWERDOWN:
  155. /* turn off panel */
  156. xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
  157. default:
  158. break;
  159. }
  160. return 0; /* success */
  161. }
  162. static struct fb_ops xilinxfb_ops =
  163. {
  164. .owner = THIS_MODULE,
  165. .fb_setcolreg = xilinx_fb_setcolreg,
  166. .fb_blank = xilinx_fb_blank,
  167. .fb_fillrect = cfb_fillrect,
  168. .fb_copyarea = cfb_copyarea,
  169. .fb_imageblit = cfb_imageblit,
  170. };
  171. /* ---------------------------------------------------------------------
  172. * Bus independent setup/teardown
  173. */
  174. static int xilinxfb_assign(struct device *dev, unsigned long physaddr,
  175. struct xilinxfb_platform_data *pdata)
  176. {
  177. struct xilinxfb_drvdata *drvdata;
  178. int rc;
  179. int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
  180. /* Allocate the driver data region */
  181. drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
  182. if (!drvdata) {
  183. dev_err(dev, "Couldn't allocate device private record\n");
  184. return -ENOMEM;
  185. }
  186. dev_set_drvdata(dev, drvdata);
  187. /* Map the control registers in */
  188. if (!request_mem_region(physaddr, 8, DRIVER_NAME)) {
  189. dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
  190. physaddr);
  191. rc = -ENODEV;
  192. goto err_region;
  193. }
  194. drvdata->regs_phys = physaddr;
  195. drvdata->regs = ioremap(physaddr, 8);
  196. if (!drvdata->regs) {
  197. dev_err(dev, "Couldn't lock memory region at 0x%08lX\n",
  198. physaddr);
  199. rc = -ENODEV;
  200. goto err_map;
  201. }
  202. /* Allocate the framebuffer memory */
  203. if (pdata->fb_phys) {
  204. drvdata->fb_phys = pdata->fb_phys;
  205. drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
  206. } else {
  207. drvdata->fb_alloced = 1;
  208. drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
  209. &drvdata->fb_phys, GFP_KERNEL);
  210. }
  211. if (!drvdata->fb_virt) {
  212. dev_err(dev, "Could not allocate frame buffer memory\n");
  213. rc = -ENOMEM;
  214. goto err_fbmem;
  215. }
  216. /* Clear (turn to black) the framebuffer */
  217. memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
  218. /* Tell the hardware where the frame buffer is */
  219. xilinx_fb_out_be32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
  220. /* Turn on the display */
  221. drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
  222. if (pdata->rotate_screen)
  223. drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
  224. xilinx_fb_out_be32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
  225. /* Fill struct fb_info */
  226. drvdata->info.device = dev;
  227. drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
  228. drvdata->info.fbops = &xilinxfb_ops;
  229. drvdata->info.fix = xilinx_fb_fix;
  230. drvdata->info.fix.smem_start = drvdata->fb_phys;
  231. drvdata->info.fix.smem_len = fbsize;
  232. drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
  233. drvdata->info.pseudo_palette = drvdata->pseudo_palette;
  234. drvdata->info.flags = FBINFO_DEFAULT;
  235. drvdata->info.var = xilinx_fb_var;
  236. drvdata->info.var.height = pdata->screen_height_mm;
  237. drvdata->info.var.width = pdata->screen_width_mm;
  238. drvdata->info.var.xres = pdata->xres;
  239. drvdata->info.var.yres = pdata->yres;
  240. drvdata->info.var.xres_virtual = pdata->xvirt;
  241. drvdata->info.var.yres_virtual = pdata->yvirt;
  242. /* Allocate a colour map */
  243. rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
  244. if (rc) {
  245. dev_err(dev, "Fail to allocate colormap (%d entries)\n",
  246. PALETTE_ENTRIES_NO);
  247. goto err_cmap;
  248. }
  249. /* Register new frame buffer */
  250. rc = register_framebuffer(&drvdata->info);
  251. if (rc) {
  252. dev_err(dev, "Could not register frame buffer\n");
  253. goto err_regfb;
  254. }
  255. /* Put a banner in the log (for DEBUG) */
  256. dev_dbg(dev, "regs: phys=%lx, virt=%p\n", physaddr, drvdata->regs);
  257. dev_dbg(dev, "fb: phys=%p, virt=%p, size=%x\n",
  258. (void*)drvdata->fb_phys, drvdata->fb_virt, fbsize);
  259. return 0; /* success */
  260. err_regfb:
  261. fb_dealloc_cmap(&drvdata->info.cmap);
  262. err_cmap:
  263. if (drvdata->fb_alloced)
  264. dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
  265. drvdata->fb_phys);
  266. /* Turn off the display */
  267. xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
  268. err_fbmem:
  269. iounmap(drvdata->regs);
  270. err_map:
  271. release_mem_region(physaddr, 8);
  272. err_region:
  273. kfree(drvdata);
  274. dev_set_drvdata(dev, NULL);
  275. return rc;
  276. }
  277. static int xilinxfb_release(struct device *dev)
  278. {
  279. struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
  280. #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
  281. xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
  282. #endif
  283. unregister_framebuffer(&drvdata->info);
  284. fb_dealloc_cmap(&drvdata->info.cmap);
  285. if (drvdata->fb_alloced)
  286. dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
  287. drvdata->fb_virt, drvdata->fb_phys);
  288. /* Turn off the display */
  289. xilinx_fb_out_be32(drvdata, REG_CTRL, 0);
  290. iounmap(drvdata->regs);
  291. release_mem_region(drvdata->regs_phys, 8);
  292. kfree(drvdata);
  293. dev_set_drvdata(dev, NULL);
  294. return 0;
  295. }
  296. /* ---------------------------------------------------------------------
  297. * Platform bus binding
  298. */
  299. static int
  300. xilinxfb_platform_probe(struct platform_device *pdev)
  301. {
  302. struct xilinxfb_platform_data *pdata;
  303. struct resource *res;
  304. /* Find the registers address */
  305. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  306. if (!res) {
  307. dev_err(&pdev->dev, "Couldn't get registers resource\n");
  308. return -ENODEV;
  309. }
  310. /* If a pdata structure is provided, then extract the parameters */
  311. pdata = &xilinx_fb_default_pdata;
  312. if (pdev->dev.platform_data) {
  313. pdata = pdev->dev.platform_data;
  314. if (!pdata->xres)
  315. pdata->xres = xilinx_fb_default_pdata.xres;
  316. if (!pdata->yres)
  317. pdata->yres = xilinx_fb_default_pdata.yres;
  318. if (!pdata->xvirt)
  319. pdata->xvirt = xilinx_fb_default_pdata.xvirt;
  320. if (!pdata->yvirt)
  321. pdata->yvirt = xilinx_fb_default_pdata.yvirt;
  322. }
  323. return xilinxfb_assign(&pdev->dev, res->start, pdata);
  324. }
  325. static int
  326. xilinxfb_platform_remove(struct platform_device *pdev)
  327. {
  328. return xilinxfb_release(&pdev->dev);
  329. }
  330. static struct platform_driver xilinxfb_platform_driver = {
  331. .probe = xilinxfb_platform_probe,
  332. .remove = xilinxfb_platform_remove,
  333. .driver = {
  334. .owner = THIS_MODULE,
  335. .name = DRIVER_NAME,
  336. },
  337. };
  338. /* ---------------------------------------------------------------------
  339. * OF bus binding
  340. */
  341. #if defined(CONFIG_OF)
  342. static int __devinit
  343. xilinxfb_of_probe(struct of_device *op, const struct of_device_id *match)
  344. {
  345. struct resource res;
  346. const u32 *prop;
  347. struct xilinxfb_platform_data pdata;
  348. int size, rc;
  349. /* Copy with the default pdata (not a ptr reference!) */
  350. pdata = xilinx_fb_default_pdata;
  351. dev_dbg(&op->dev, "xilinxfb_of_probe(%p, %p)\n", op, match);
  352. rc = of_address_to_resource(op->node, 0, &res);
  353. if (rc) {
  354. dev_err(&op->dev, "invalid address\n");
  355. return rc;
  356. }
  357. prop = of_get_property(op->node, "phys-size", &size);
  358. if ((prop) && (size >= sizeof(u32)*2)) {
  359. pdata.screen_width_mm = prop[0];
  360. pdata.screen_height_mm = prop[1];
  361. }
  362. prop = of_get_property(op->node, "resolution", &size);
  363. if ((prop) && (size >= sizeof(u32)*2)) {
  364. pdata.xres = prop[0];
  365. pdata.yres = prop[1];
  366. }
  367. prop = of_get_property(op->node, "virtual-resolution", &size);
  368. if ((prop) && (size >= sizeof(u32)*2)) {
  369. pdata.xvirt = prop[0];
  370. pdata.yvirt = prop[1];
  371. }
  372. if (of_find_property(op->node, "rotate-display", NULL))
  373. pdata.rotate_screen = 1;
  374. return xilinxfb_assign(&op->dev, res.start, &pdata);
  375. }
  376. static int __devexit xilinxfb_of_remove(struct of_device *op)
  377. {
  378. return xilinxfb_release(&op->dev);
  379. }
  380. /* Match table for of_platform binding */
  381. static struct of_device_id __devinit xilinxfb_of_match[] = {
  382. { .compatible = "xilinx,ml300-fb", },
  383. {},
  384. };
  385. MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
  386. static struct of_platform_driver xilinxfb_of_driver = {
  387. .owner = THIS_MODULE,
  388. .name = DRIVER_NAME,
  389. .match_table = xilinxfb_of_match,
  390. .probe = xilinxfb_of_probe,
  391. .remove = __devexit_p(xilinxfb_of_remove),
  392. .driver = {
  393. .name = DRIVER_NAME,
  394. },
  395. };
  396. /* Registration helpers to keep the number of #ifdefs to a minimum */
  397. static inline int __init xilinxfb_of_register(void)
  398. {
  399. pr_debug("xilinxfb: calling of_register_platform_driver()\n");
  400. return of_register_platform_driver(&xilinxfb_of_driver);
  401. }
  402. static inline void __exit xilinxfb_of_unregister(void)
  403. {
  404. of_unregister_platform_driver(&xilinxfb_of_driver);
  405. }
  406. #else /* CONFIG_OF */
  407. /* CONFIG_OF not enabled; do nothing helpers */
  408. static inline int __init xilinxfb_of_register(void) { return 0; }
  409. static inline void __exit xilinxfb_of_unregister(void) { }
  410. #endif /* CONFIG_OF */
  411. /* ---------------------------------------------------------------------
  412. * Module setup and teardown
  413. */
  414. static int __init
  415. xilinxfb_init(void)
  416. {
  417. int rc;
  418. rc = xilinxfb_of_register();
  419. if (rc)
  420. return rc;
  421. rc = platform_driver_register(&xilinxfb_platform_driver);
  422. if (rc)
  423. xilinxfb_of_unregister();
  424. return rc;
  425. }
  426. static void __exit
  427. xilinxfb_cleanup(void)
  428. {
  429. platform_driver_unregister(&xilinxfb_platform_driver);
  430. xilinxfb_of_unregister();
  431. }
  432. module_init(xilinxfb_init);
  433. module_exit(xilinxfb_cleanup);
  434. MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
  435. MODULE_DESCRIPTION(DRIVER_DESCRIPTION);
  436. MODULE_LICENSE("GPL");