ohci-pci.c 10 KB

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  1. /*
  2. * OHCI HCD (Host Controller Driver) for USB.
  3. *
  4. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  5. * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
  6. *
  7. * [ Initialisation is based on Linus' ]
  8. * [ uhci code and gregs ohci fragments ]
  9. * [ (C) Copyright 1999 Linus Torvalds ]
  10. * [ (C) Copyright 1999 Gregory P. Smith]
  11. *
  12. * PCI Bus Glue
  13. *
  14. * This file is licenced under the GPL.
  15. */
  16. #ifndef CONFIG_PCI
  17. #error "This file is PCI bus glue. CONFIG_PCI must be defined."
  18. #endif
  19. /*-------------------------------------------------------------------------*/
  20. static int broken_suspend(struct usb_hcd *hcd)
  21. {
  22. device_init_wakeup(&hcd->self.root_hub->dev, 0);
  23. return 0;
  24. }
  25. /* AMD 756, for most chips (early revs), corrupts register
  26. * values on read ... so enable the vendor workaround.
  27. */
  28. static int ohci_quirk_amd756(struct usb_hcd *hcd)
  29. {
  30. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  31. ohci->flags = OHCI_QUIRK_AMD756;
  32. ohci_dbg (ohci, "AMD756 erratum 4 workaround\n");
  33. /* also erratum 10 (suspend/resume issues) */
  34. return broken_suspend(hcd);
  35. }
  36. /* Apple's OHCI driver has a lot of bizarre workarounds
  37. * for this chip. Evidently control and bulk lists
  38. * can get confused. (B&W G3 models, and ...)
  39. */
  40. static int ohci_quirk_opti(struct usb_hcd *hcd)
  41. {
  42. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  43. ohci_dbg (ohci, "WARNING: OPTi workarounds unavailable\n");
  44. return 0;
  45. }
  46. /* Check for NSC87560. We have to look at the bridge (fn1) to
  47. * identify the USB (fn2). This quirk might apply to more or
  48. * even all NSC stuff.
  49. */
  50. static int ohci_quirk_ns(struct usb_hcd *hcd)
  51. {
  52. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  53. struct pci_dev *b;
  54. b = pci_get_slot (pdev->bus, PCI_DEVFN (PCI_SLOT (pdev->devfn), 1));
  55. if (b && b->device == PCI_DEVICE_ID_NS_87560_LIO
  56. && b->vendor == PCI_VENDOR_ID_NS) {
  57. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  58. ohci->flags |= OHCI_QUIRK_SUPERIO;
  59. ohci_dbg (ohci, "Using NSC SuperIO setup\n");
  60. }
  61. pci_dev_put(b);
  62. return 0;
  63. }
  64. /* Check for Compaq's ZFMicro chipset, which needs short
  65. * delays before control or bulk queues get re-activated
  66. * in finish_unlinks()
  67. */
  68. static int ohci_quirk_zfmicro(struct usb_hcd *hcd)
  69. {
  70. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  71. ohci->flags |= OHCI_QUIRK_ZFMICRO;
  72. ohci_dbg(ohci, "enabled Compaq ZFMicro chipset quirks\n");
  73. return 0;
  74. }
  75. /* Check for Toshiba SCC OHCI which has big endian registers
  76. * and little endian in memory data structures
  77. */
  78. static int ohci_quirk_toshiba_scc(struct usb_hcd *hcd)
  79. {
  80. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  81. /* That chip is only present in the southbridge of some
  82. * cell based platforms which are supposed to select
  83. * CONFIG_USB_OHCI_BIG_ENDIAN_MMIO. We verify here if
  84. * that was the case though.
  85. */
  86. #ifdef CONFIG_USB_OHCI_BIG_ENDIAN_MMIO
  87. ohci->flags |= OHCI_QUIRK_BE_MMIO;
  88. ohci_dbg (ohci, "enabled big endian Toshiba quirk\n");
  89. return 0;
  90. #else
  91. ohci_err (ohci, "unsupported big endian Toshiba quirk\n");
  92. return -ENXIO;
  93. #endif
  94. }
  95. /* Check for NEC chip and apply quirk for allegedly lost interrupts.
  96. */
  97. static void ohci_quirk_nec_worker(struct work_struct *work)
  98. {
  99. struct ohci_hcd *ohci = container_of(work, struct ohci_hcd, nec_work);
  100. int status;
  101. status = ohci_init(ohci);
  102. if (status != 0) {
  103. ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
  104. "ohci_init", status);
  105. return;
  106. }
  107. status = ohci_restart(ohci);
  108. if (status != 0)
  109. ohci_err(ohci, "Restarting NEC controller failed in %s, %d\n",
  110. "ohci_restart", status);
  111. }
  112. static int ohci_quirk_nec(struct usb_hcd *hcd)
  113. {
  114. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  115. ohci->flags |= OHCI_QUIRK_NEC;
  116. INIT_WORK(&ohci->nec_work, ohci_quirk_nec_worker);
  117. ohci_dbg (ohci, "enabled NEC chipset lost interrupt quirk\n");
  118. return 0;
  119. }
  120. /* List of quirks for OHCI */
  121. static const struct pci_device_id ohci_pci_quirks[] = {
  122. {
  123. PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x740c),
  124. .driver_data = (unsigned long)ohci_quirk_amd756,
  125. },
  126. {
  127. PCI_DEVICE(PCI_VENDOR_ID_OPTI, 0xc861),
  128. .driver_data = (unsigned long)ohci_quirk_opti,
  129. },
  130. {
  131. PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_ANY_ID),
  132. .driver_data = (unsigned long)ohci_quirk_ns,
  133. },
  134. {
  135. PCI_DEVICE(PCI_VENDOR_ID_COMPAQ, 0xa0f8),
  136. .driver_data = (unsigned long)ohci_quirk_zfmicro,
  137. },
  138. {
  139. PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, 0x01b6),
  140. .driver_data = (unsigned long)ohci_quirk_toshiba_scc,
  141. },
  142. {
  143. PCI_DEVICE(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB),
  144. .driver_data = (unsigned long)ohci_quirk_nec,
  145. },
  146. {
  147. /* Toshiba portege 4000 */
  148. .vendor = PCI_VENDOR_ID_AL,
  149. .device = 0x5237,
  150. .subvendor = PCI_VENDOR_ID_TOSHIBA,
  151. .subdevice = 0x0004,
  152. .driver_data = (unsigned long) broken_suspend,
  153. },
  154. {
  155. PCI_DEVICE(PCI_VENDOR_ID_ITE, 0x8152),
  156. .driver_data = (unsigned long) broken_suspend,
  157. },
  158. /* FIXME for some of the early AMD 760 southbridges, OHCI
  159. * won't work at all. blacklist them.
  160. */
  161. {},
  162. };
  163. static int ohci_pci_reset (struct usb_hcd *hcd)
  164. {
  165. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  166. int ret = 0;
  167. if (hcd->self.controller) {
  168. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  169. const struct pci_device_id *quirk_id;
  170. quirk_id = pci_match_id(ohci_pci_quirks, pdev);
  171. if (quirk_id != NULL) {
  172. int (*quirk)(struct usb_hcd *ohci);
  173. quirk = (void *)quirk_id->driver_data;
  174. ret = quirk(hcd);
  175. }
  176. }
  177. if (ret == 0) {
  178. ohci_hcd_init (ohci);
  179. return ohci_init (ohci);
  180. }
  181. return ret;
  182. }
  183. static int __devinit ohci_pci_start (struct usb_hcd *hcd)
  184. {
  185. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  186. int ret;
  187. #ifdef CONFIG_PM /* avoid warnings about unused pdev */
  188. if (hcd->self.controller) {
  189. struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
  190. /* RWC may not be set for add-in PCI cards, since boot
  191. * firmware probably ignored them. This transfers PCI
  192. * PM wakeup capabilities (once the PCI layer is fixed).
  193. */
  194. if (device_may_wakeup(&pdev->dev))
  195. ohci->hc_control |= OHCI_CTRL_RWC;
  196. }
  197. #endif /* CONFIG_PM */
  198. ret = ohci_run (ohci);
  199. if (ret < 0) {
  200. ohci_err (ohci, "can't start\n");
  201. ohci_stop (hcd);
  202. }
  203. return ret;
  204. }
  205. #if defined(CONFIG_USB_PERSIST) && (defined(CONFIG_USB_EHCI_HCD) || \
  206. defined(CONFIG_USB_EHCI_HCD_MODULE))
  207. /* Following a power loss, we must prepare to regain control of the ports
  208. * we used to own. This means turning on the port power before ehci-hcd
  209. * tries to switch ownership.
  210. *
  211. * This isn't a 100% perfect solution. On most systems the OHCI controllers
  212. * lie at lower PCI addresses than the EHCI controller, so they will be
  213. * discovered (and hence resumed) first. But there is no guarantee things
  214. * will always work this way. If the EHCI controller is resumed first and
  215. * the OHCI ports are unpowered, then the handover will fail.
  216. */
  217. static void prepare_for_handover(struct usb_hcd *hcd)
  218. {
  219. struct ohci_hcd *ohci = hcd_to_ohci(hcd);
  220. int port;
  221. /* Here we "know" root ports should always stay powered */
  222. ohci_dbg(ohci, "powerup ports\n");
  223. for (port = 0; port < ohci->num_ports; port++)
  224. ohci_writel(ohci, RH_PS_PPS,
  225. &ohci->regs->roothub.portstatus[port]);
  226. /* Flush those writes */
  227. ohci_readl(ohci, &ohci->regs->control);
  228. msleep(20);
  229. }
  230. #else
  231. static inline void prepare_for_handover(struct usb_hcd *hcd)
  232. { }
  233. #endif /* CONFIG_USB_PERSIST etc. */
  234. #ifdef CONFIG_PM
  235. static int ohci_pci_suspend (struct usb_hcd *hcd, pm_message_t message)
  236. {
  237. struct ohci_hcd *ohci = hcd_to_ohci (hcd);
  238. unsigned long flags;
  239. int rc = 0;
  240. /* Root hub was already suspended. Disable irq emission and
  241. * mark HW unaccessible, bail out if RH has been resumed. Use
  242. * the spinlock to properly synchronize with possible pending
  243. * RH suspend or resume activity.
  244. *
  245. * This is still racy as hcd->state is manipulated outside of
  246. * any locks =P But that will be a different fix.
  247. */
  248. spin_lock_irqsave (&ohci->lock, flags);
  249. if (hcd->state != HC_STATE_SUSPENDED) {
  250. rc = -EINVAL;
  251. goto bail;
  252. }
  253. ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
  254. (void)ohci_readl(ohci, &ohci->regs->intrdisable);
  255. /* make sure snapshot being resumed re-enumerates everything */
  256. if (message.event == PM_EVENT_PRETHAW)
  257. ohci_usb_reset(ohci);
  258. clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  259. bail:
  260. spin_unlock_irqrestore (&ohci->lock, flags);
  261. return rc;
  262. }
  263. static int ohci_pci_resume (struct usb_hcd *hcd)
  264. {
  265. set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
  266. /* FIXME: we should try to detect loss of VBUS power here */
  267. prepare_for_handover(hcd);
  268. return 0;
  269. }
  270. #endif /* CONFIG_PM */
  271. /*-------------------------------------------------------------------------*/
  272. static const struct hc_driver ohci_pci_hc_driver = {
  273. .description = hcd_name,
  274. .product_desc = "OHCI Host Controller",
  275. .hcd_priv_size = sizeof(struct ohci_hcd),
  276. /*
  277. * generic hardware linkage
  278. */
  279. .irq = ohci_irq,
  280. .flags = HCD_MEMORY | HCD_USB11,
  281. /*
  282. * basic lifecycle operations
  283. */
  284. .reset = ohci_pci_reset,
  285. .start = ohci_pci_start,
  286. .stop = ohci_stop,
  287. .shutdown = ohci_shutdown,
  288. #ifdef CONFIG_PM
  289. /* these suspend/resume entries are for upstream PCI glue ONLY */
  290. .suspend = ohci_pci_suspend,
  291. .resume = ohci_pci_resume,
  292. #endif
  293. /*
  294. * managing i/o requests and associated device resources
  295. */
  296. .urb_enqueue = ohci_urb_enqueue,
  297. .urb_dequeue = ohci_urb_dequeue,
  298. .endpoint_disable = ohci_endpoint_disable,
  299. /*
  300. * scheduling support
  301. */
  302. .get_frame_number = ohci_get_frame,
  303. /*
  304. * root hub support
  305. */
  306. .hub_status_data = ohci_hub_status_data,
  307. .hub_control = ohci_hub_control,
  308. .hub_irq_enable = ohci_rhsc_enable,
  309. #ifdef CONFIG_PM
  310. .bus_suspend = ohci_bus_suspend,
  311. .bus_resume = ohci_bus_resume,
  312. #endif
  313. .start_port_reset = ohci_start_port_reset,
  314. };
  315. /*-------------------------------------------------------------------------*/
  316. static const struct pci_device_id pci_ids [] = { {
  317. /* handle any USB OHCI controller */
  318. PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_OHCI, ~0),
  319. .driver_data = (unsigned long) &ohci_pci_hc_driver,
  320. }, { /* end: all zeroes */ }
  321. };
  322. MODULE_DEVICE_TABLE (pci, pci_ids);
  323. /* pci driver glue; this is a "new style" PCI driver module */
  324. static struct pci_driver ohci_pci_driver = {
  325. .name = (char *) hcd_name,
  326. .id_table = pci_ids,
  327. .probe = usb_hcd_pci_probe,
  328. .remove = usb_hcd_pci_remove,
  329. #ifdef CONFIG_PM
  330. .suspend = usb_hcd_pci_suspend,
  331. .resume = usb_hcd_pci_resume,
  332. #endif
  333. .shutdown = usb_hcd_pci_shutdown,
  334. };