ehci-dbg.c 22 KB

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  1. /*
  2. * Copyright (c) 2001-2002 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. #define ehci_dbg(ehci, fmt, args...) \
  20. dev_dbg (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  21. #define ehci_err(ehci, fmt, args...) \
  22. dev_err (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  23. #define ehci_info(ehci, fmt, args...) \
  24. dev_info (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  25. #define ehci_warn(ehci, fmt, args...) \
  26. dev_warn (ehci_to_hcd(ehci)->self.controller , fmt , ## args )
  27. #ifdef EHCI_VERBOSE_DEBUG
  28. # define vdbg dbg
  29. # define ehci_vdbg ehci_dbg
  30. #else
  31. # define vdbg(fmt,args...) do { } while (0)
  32. # define ehci_vdbg(ehci, fmt, args...) do { } while (0)
  33. #endif
  34. #ifdef DEBUG
  35. /* check the values in the HCSPARAMS register
  36. * (host controller _Structural_ parameters)
  37. * see EHCI spec, Table 2-4 for each value
  38. */
  39. static void dbg_hcs_params (struct ehci_hcd *ehci, char *label)
  40. {
  41. u32 params = ehci_readl(ehci, &ehci->caps->hcs_params);
  42. ehci_dbg (ehci,
  43. "%s hcs_params 0x%x dbg=%d%s cc=%d pcc=%d%s%s ports=%d\n",
  44. label, params,
  45. HCS_DEBUG_PORT (params),
  46. HCS_INDICATOR (params) ? " ind" : "",
  47. HCS_N_CC (params),
  48. HCS_N_PCC (params),
  49. HCS_PORTROUTED (params) ? "" : " ordered",
  50. HCS_PPC (params) ? "" : " !ppc",
  51. HCS_N_PORTS (params)
  52. );
  53. /* Port routing, per EHCI 0.95 Spec, Section 2.2.5 */
  54. if (HCS_PORTROUTED (params)) {
  55. int i;
  56. char buf [46], tmp [7], byte;
  57. buf[0] = 0;
  58. for (i = 0; i < HCS_N_PORTS (params); i++) {
  59. // FIXME MIPS won't readb() ...
  60. byte = readb (&ehci->caps->portroute[(i>>1)]);
  61. sprintf(tmp, "%d ",
  62. ((i & 0x1) ? ((byte)&0xf) : ((byte>>4)&0xf)));
  63. strcat(buf, tmp);
  64. }
  65. ehci_dbg (ehci, "%s portroute %s\n",
  66. label, buf);
  67. }
  68. }
  69. #else
  70. static inline void dbg_hcs_params (struct ehci_hcd *ehci, char *label) {}
  71. #endif
  72. #ifdef DEBUG
  73. /* check the values in the HCCPARAMS register
  74. * (host controller _Capability_ parameters)
  75. * see EHCI Spec, Table 2-5 for each value
  76. * */
  77. static void dbg_hcc_params (struct ehci_hcd *ehci, char *label)
  78. {
  79. u32 params = ehci_readl(ehci, &ehci->caps->hcc_params);
  80. if (HCC_ISOC_CACHE (params)) {
  81. ehci_dbg (ehci,
  82. "%s hcc_params %04x caching frame %s%s%s\n",
  83. label, params,
  84. HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
  85. HCC_CANPARK(params) ? " park" : "",
  86. HCC_64BIT_ADDR(params) ? " 64 bit addr" : "");
  87. } else {
  88. ehci_dbg (ehci,
  89. "%s hcc_params %04x thresh %d uframes %s%s%s\n",
  90. label,
  91. params,
  92. HCC_ISOC_THRES(params),
  93. HCC_PGM_FRAMELISTLEN(params) ? "256/512/1024" : "1024",
  94. HCC_CANPARK(params) ? " park" : "",
  95. HCC_64BIT_ADDR(params) ? " 64 bit addr" : "");
  96. }
  97. }
  98. #else
  99. static inline void dbg_hcc_params (struct ehci_hcd *ehci, char *label) {}
  100. #endif
  101. #ifdef DEBUG
  102. static void __maybe_unused
  103. dbg_qtd (const char *label, struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  104. {
  105. ehci_dbg(ehci, "%s td %p n%08x %08x t%08x p0=%08x\n", label, qtd,
  106. hc32_to_cpup(ehci, &qtd->hw_next),
  107. hc32_to_cpup(ehci, &qtd->hw_alt_next),
  108. hc32_to_cpup(ehci, &qtd->hw_token),
  109. hc32_to_cpup(ehci, &qtd->hw_buf [0]));
  110. if (qtd->hw_buf [1])
  111. ehci_dbg(ehci, " p1=%08x p2=%08x p3=%08x p4=%08x\n",
  112. hc32_to_cpup(ehci, &qtd->hw_buf[1]),
  113. hc32_to_cpup(ehci, &qtd->hw_buf[2]),
  114. hc32_to_cpup(ehci, &qtd->hw_buf[3]),
  115. hc32_to_cpup(ehci, &qtd->hw_buf[4]));
  116. }
  117. static void __maybe_unused
  118. dbg_qh (const char *label, struct ehci_hcd *ehci, struct ehci_qh *qh)
  119. {
  120. ehci_dbg (ehci, "%s qh %p n%08x info %x %x qtd %x\n", label,
  121. qh, qh->hw_next, qh->hw_info1, qh->hw_info2,
  122. qh->hw_current);
  123. dbg_qtd ("overlay", ehci, (struct ehci_qtd *) &qh->hw_qtd_next);
  124. }
  125. static void __maybe_unused
  126. dbg_itd (const char *label, struct ehci_hcd *ehci, struct ehci_itd *itd)
  127. {
  128. ehci_dbg (ehci, "%s [%d] itd %p, next %08x, urb %p\n",
  129. label, itd->frame, itd, hc32_to_cpu(ehci, itd->hw_next),
  130. itd->urb);
  131. ehci_dbg (ehci,
  132. " trans: %08x %08x %08x %08x %08x %08x %08x %08x\n",
  133. hc32_to_cpu(ehci, itd->hw_transaction[0]),
  134. hc32_to_cpu(ehci, itd->hw_transaction[1]),
  135. hc32_to_cpu(ehci, itd->hw_transaction[2]),
  136. hc32_to_cpu(ehci, itd->hw_transaction[3]),
  137. hc32_to_cpu(ehci, itd->hw_transaction[4]),
  138. hc32_to_cpu(ehci, itd->hw_transaction[5]),
  139. hc32_to_cpu(ehci, itd->hw_transaction[6]),
  140. hc32_to_cpu(ehci, itd->hw_transaction[7]));
  141. ehci_dbg (ehci,
  142. " buf: %08x %08x %08x %08x %08x %08x %08x\n",
  143. hc32_to_cpu(ehci, itd->hw_bufp[0]),
  144. hc32_to_cpu(ehci, itd->hw_bufp[1]),
  145. hc32_to_cpu(ehci, itd->hw_bufp[2]),
  146. hc32_to_cpu(ehci, itd->hw_bufp[3]),
  147. hc32_to_cpu(ehci, itd->hw_bufp[4]),
  148. hc32_to_cpu(ehci, itd->hw_bufp[5]),
  149. hc32_to_cpu(ehci, itd->hw_bufp[6]));
  150. ehci_dbg (ehci, " index: %d %d %d %d %d %d %d %d\n",
  151. itd->index[0], itd->index[1], itd->index[2],
  152. itd->index[3], itd->index[4], itd->index[5],
  153. itd->index[6], itd->index[7]);
  154. }
  155. static void __maybe_unused
  156. dbg_sitd (const char *label, struct ehci_hcd *ehci, struct ehci_sitd *sitd)
  157. {
  158. ehci_dbg (ehci, "%s [%d] sitd %p, next %08x, urb %p\n",
  159. label, sitd->frame, sitd, hc32_to_cpu(ehci, sitd->hw_next),
  160. sitd->urb);
  161. ehci_dbg (ehci,
  162. " addr %08x sched %04x result %08x buf %08x %08x\n",
  163. hc32_to_cpu(ehci, sitd->hw_fullspeed_ep),
  164. hc32_to_cpu(ehci, sitd->hw_uframe),
  165. hc32_to_cpu(ehci, sitd->hw_results),
  166. hc32_to_cpu(ehci, sitd->hw_buf[0]),
  167. hc32_to_cpu(ehci, sitd->hw_buf[1]));
  168. }
  169. static int __maybe_unused
  170. dbg_status_buf (char *buf, unsigned len, const char *label, u32 status)
  171. {
  172. return scnprintf (buf, len,
  173. "%s%sstatus %04x%s%s%s%s%s%s%s%s%s%s",
  174. label, label [0] ? " " : "", status,
  175. (status & STS_ASS) ? " Async" : "",
  176. (status & STS_PSS) ? " Periodic" : "",
  177. (status & STS_RECL) ? " Recl" : "",
  178. (status & STS_HALT) ? " Halt" : "",
  179. (status & STS_IAA) ? " IAA" : "",
  180. (status & STS_FATAL) ? " FATAL" : "",
  181. (status & STS_FLR) ? " FLR" : "",
  182. (status & STS_PCD) ? " PCD" : "",
  183. (status & STS_ERR) ? " ERR" : "",
  184. (status & STS_INT) ? " INT" : ""
  185. );
  186. }
  187. static int __maybe_unused
  188. dbg_intr_buf (char *buf, unsigned len, const char *label, u32 enable)
  189. {
  190. return scnprintf (buf, len,
  191. "%s%sintrenable %02x%s%s%s%s%s%s",
  192. label, label [0] ? " " : "", enable,
  193. (enable & STS_IAA) ? " IAA" : "",
  194. (enable & STS_FATAL) ? " FATAL" : "",
  195. (enable & STS_FLR) ? " FLR" : "",
  196. (enable & STS_PCD) ? " PCD" : "",
  197. (enable & STS_ERR) ? " ERR" : "",
  198. (enable & STS_INT) ? " INT" : ""
  199. );
  200. }
  201. static const char *const fls_strings [] =
  202. { "1024", "512", "256", "??" };
  203. static int
  204. dbg_command_buf (char *buf, unsigned len, const char *label, u32 command)
  205. {
  206. return scnprintf (buf, len,
  207. "%s%scommand %06x %s=%d ithresh=%d%s%s%s%s period=%s%s %s",
  208. label, label [0] ? " " : "", command,
  209. (command & CMD_PARK) ? "park" : "(park)",
  210. CMD_PARK_CNT (command),
  211. (command >> 16) & 0x3f,
  212. (command & CMD_LRESET) ? " LReset" : "",
  213. (command & CMD_IAAD) ? " IAAD" : "",
  214. (command & CMD_ASE) ? " Async" : "",
  215. (command & CMD_PSE) ? " Periodic" : "",
  216. fls_strings [(command >> 2) & 0x3],
  217. (command & CMD_RESET) ? " Reset" : "",
  218. (command & CMD_RUN) ? "RUN" : "HALT"
  219. );
  220. }
  221. static int
  222. dbg_port_buf (char *buf, unsigned len, const char *label, int port, u32 status)
  223. {
  224. char *sig;
  225. /* signaling state */
  226. switch (status & (3 << 10)) {
  227. case 0 << 10: sig = "se0"; break;
  228. case 1 << 10: sig = "k"; break; /* low speed */
  229. case 2 << 10: sig = "j"; break;
  230. default: sig = "?"; break;
  231. }
  232. return scnprintf (buf, len,
  233. "%s%sport %d status %06x%s%s sig=%s%s%s%s%s%s%s%s%s%s",
  234. label, label [0] ? " " : "", port, status,
  235. (status & PORT_POWER) ? " POWER" : "",
  236. (status & PORT_OWNER) ? " OWNER" : "",
  237. sig,
  238. (status & PORT_RESET) ? " RESET" : "",
  239. (status & PORT_SUSPEND) ? " SUSPEND" : "",
  240. (status & PORT_RESUME) ? " RESUME" : "",
  241. (status & PORT_OCC) ? " OCC" : "",
  242. (status & PORT_OC) ? " OC" : "",
  243. (status & PORT_PEC) ? " PEC" : "",
  244. (status & PORT_PE) ? " PE" : "",
  245. (status & PORT_CSC) ? " CSC" : "",
  246. (status & PORT_CONNECT) ? " CONNECT" : "");
  247. }
  248. #else
  249. static inline void __maybe_unused
  250. dbg_qh (char *label, struct ehci_hcd *ehci, struct ehci_qh *qh)
  251. {}
  252. static inline int __maybe_unused
  253. dbg_status_buf (char *buf, unsigned len, const char *label, u32 status)
  254. { return 0; }
  255. static inline int __maybe_unused
  256. dbg_command_buf (char *buf, unsigned len, const char *label, u32 command)
  257. { return 0; }
  258. static inline int __maybe_unused
  259. dbg_intr_buf (char *buf, unsigned len, const char *label, u32 enable)
  260. { return 0; }
  261. static inline int __maybe_unused
  262. dbg_port_buf (char *buf, unsigned len, const char *label, int port, u32 status)
  263. { return 0; }
  264. #endif /* DEBUG */
  265. /* functions have the "wrong" filename when they're output... */
  266. #define dbg_status(ehci, label, status) { \
  267. char _buf [80]; \
  268. dbg_status_buf (_buf, sizeof _buf, label, status); \
  269. ehci_dbg (ehci, "%s\n", _buf); \
  270. }
  271. #define dbg_cmd(ehci, label, command) { \
  272. char _buf [80]; \
  273. dbg_command_buf (_buf, sizeof _buf, label, command); \
  274. ehci_dbg (ehci, "%s\n", _buf); \
  275. }
  276. #define dbg_port(ehci, label, port, status) { \
  277. char _buf [80]; \
  278. dbg_port_buf (_buf, sizeof _buf, label, port, status); \
  279. ehci_dbg (ehci, "%s\n", _buf); \
  280. }
  281. /*-------------------------------------------------------------------------*/
  282. #ifdef STUB_DEBUG_FILES
  283. static inline void create_debug_files (struct ehci_hcd *bus) { }
  284. static inline void remove_debug_files (struct ehci_hcd *bus) { }
  285. #else
  286. /* troubleshooting help: expose state in sysfs */
  287. #define speed_char(info1) ({ char tmp; \
  288. switch (info1 & (3 << 12)) { \
  289. case 0 << 12: tmp = 'f'; break; \
  290. case 1 << 12: tmp = 'l'; break; \
  291. case 2 << 12: tmp = 'h'; break; \
  292. default: tmp = '?'; break; \
  293. }; tmp; })
  294. static inline char token_mark(struct ehci_hcd *ehci, __hc32 token)
  295. {
  296. __u32 v = hc32_to_cpu(ehci, token);
  297. if (v & QTD_STS_ACTIVE)
  298. return '*';
  299. if (v & QTD_STS_HALT)
  300. return '-';
  301. if (!IS_SHORT_READ (v))
  302. return ' ';
  303. /* tries to advance through hw_alt_next */
  304. return '/';
  305. }
  306. static void qh_lines (
  307. struct ehci_hcd *ehci,
  308. struct ehci_qh *qh,
  309. char **nextp,
  310. unsigned *sizep
  311. )
  312. {
  313. u32 scratch;
  314. u32 hw_curr;
  315. struct list_head *entry;
  316. struct ehci_qtd *td;
  317. unsigned temp;
  318. unsigned size = *sizep;
  319. char *next = *nextp;
  320. char mark;
  321. u32 list_end = EHCI_LIST_END(ehci);
  322. if (qh->hw_qtd_next == list_end) /* NEC does this */
  323. mark = '@';
  324. else
  325. mark = token_mark(ehci, qh->hw_token);
  326. if (mark == '/') { /* qh_alt_next controls qh advance? */
  327. if ((qh->hw_alt_next & QTD_MASK(ehci))
  328. == ehci->async->hw_alt_next)
  329. mark = '#'; /* blocked */
  330. else if (qh->hw_alt_next == list_end)
  331. mark = '.'; /* use hw_qtd_next */
  332. /* else alt_next points to some other qtd */
  333. }
  334. scratch = hc32_to_cpup(ehci, &qh->hw_info1);
  335. hw_curr = (mark == '*') ? hc32_to_cpup(ehci, &qh->hw_current) : 0;
  336. temp = scnprintf (next, size,
  337. "qh/%p dev%d %cs ep%d %08x %08x (%08x%c %s nak%d)",
  338. qh, scratch & 0x007f,
  339. speed_char (scratch),
  340. (scratch >> 8) & 0x000f,
  341. scratch, hc32_to_cpup(ehci, &qh->hw_info2),
  342. hc32_to_cpup(ehci, &qh->hw_token), mark,
  343. (cpu_to_hc32(ehci, QTD_TOGGLE) & qh->hw_token)
  344. ? "data1" : "data0",
  345. (hc32_to_cpup(ehci, &qh->hw_alt_next) >> 1) & 0x0f);
  346. size -= temp;
  347. next += temp;
  348. /* hc may be modifying the list as we read it ... */
  349. list_for_each (entry, &qh->qtd_list) {
  350. td = list_entry (entry, struct ehci_qtd, qtd_list);
  351. scratch = hc32_to_cpup(ehci, &td->hw_token);
  352. mark = ' ';
  353. if (hw_curr == td->qtd_dma)
  354. mark = '*';
  355. else if (qh->hw_qtd_next == cpu_to_hc32(ehci, td->qtd_dma))
  356. mark = '+';
  357. else if (QTD_LENGTH (scratch)) {
  358. if (td->hw_alt_next == ehci->async->hw_alt_next)
  359. mark = '#';
  360. else if (td->hw_alt_next != list_end)
  361. mark = '/';
  362. }
  363. temp = snprintf (next, size,
  364. "\n\t%p%c%s len=%d %08x urb %p",
  365. td, mark, ({ char *tmp;
  366. switch ((scratch>>8)&0x03) {
  367. case 0: tmp = "out"; break;
  368. case 1: tmp = "in"; break;
  369. case 2: tmp = "setup"; break;
  370. default: tmp = "?"; break;
  371. } tmp;}),
  372. (scratch >> 16) & 0x7fff,
  373. scratch,
  374. td->urb);
  375. if (temp < 0)
  376. temp = 0;
  377. else if (size < temp)
  378. temp = size;
  379. size -= temp;
  380. next += temp;
  381. if (temp == size)
  382. goto done;
  383. }
  384. temp = snprintf (next, size, "\n");
  385. if (temp < 0)
  386. temp = 0;
  387. else if (size < temp)
  388. temp = size;
  389. size -= temp;
  390. next += temp;
  391. done:
  392. *sizep = size;
  393. *nextp = next;
  394. }
  395. static ssize_t
  396. show_async (struct class_device *class_dev, char *buf)
  397. {
  398. struct usb_bus *bus;
  399. struct usb_hcd *hcd;
  400. struct ehci_hcd *ehci;
  401. unsigned long flags;
  402. unsigned temp, size;
  403. char *next;
  404. struct ehci_qh *qh;
  405. *buf = 0;
  406. bus = class_get_devdata(class_dev);
  407. hcd = bus_to_hcd(bus);
  408. ehci = hcd_to_ehci (hcd);
  409. next = buf;
  410. size = PAGE_SIZE;
  411. /* dumps a snapshot of the async schedule.
  412. * usually empty except for long-term bulk reads, or head.
  413. * one QH per line, and TDs we know about
  414. */
  415. spin_lock_irqsave (&ehci->lock, flags);
  416. for (qh = ehci->async->qh_next.qh; size > 0 && qh; qh = qh->qh_next.qh)
  417. qh_lines (ehci, qh, &next, &size);
  418. if (ehci->reclaim && size > 0) {
  419. temp = scnprintf (next, size, "\nreclaim =\n");
  420. size -= temp;
  421. next += temp;
  422. for (qh = ehci->reclaim; size > 0 && qh; qh = qh->reclaim)
  423. qh_lines (ehci, qh, &next, &size);
  424. }
  425. spin_unlock_irqrestore (&ehci->lock, flags);
  426. return strlen (buf);
  427. }
  428. static CLASS_DEVICE_ATTR (async, S_IRUGO, show_async, NULL);
  429. #define DBG_SCHED_LIMIT 64
  430. static ssize_t
  431. show_periodic (struct class_device *class_dev, char *buf)
  432. {
  433. struct usb_bus *bus;
  434. struct usb_hcd *hcd;
  435. struct ehci_hcd *ehci;
  436. unsigned long flags;
  437. union ehci_shadow p, *seen;
  438. unsigned temp, size, seen_count;
  439. char *next;
  440. unsigned i;
  441. __hc32 tag;
  442. if (!(seen = kmalloc (DBG_SCHED_LIMIT * sizeof *seen, GFP_ATOMIC)))
  443. return 0;
  444. seen_count = 0;
  445. bus = class_get_devdata(class_dev);
  446. hcd = bus_to_hcd(bus);
  447. ehci = hcd_to_ehci (hcd);
  448. next = buf;
  449. size = PAGE_SIZE;
  450. temp = scnprintf (next, size, "size = %d\n", ehci->periodic_size);
  451. size -= temp;
  452. next += temp;
  453. /* dump a snapshot of the periodic schedule.
  454. * iso changes, interrupt usually doesn't.
  455. */
  456. spin_lock_irqsave (&ehci->lock, flags);
  457. for (i = 0; i < ehci->periodic_size; i++) {
  458. p = ehci->pshadow [i];
  459. if (likely (!p.ptr))
  460. continue;
  461. tag = Q_NEXT_TYPE(ehci, ehci->periodic [i]);
  462. temp = scnprintf (next, size, "%4d: ", i);
  463. size -= temp;
  464. next += temp;
  465. do {
  466. switch (hc32_to_cpu(ehci, tag)) {
  467. case Q_TYPE_QH:
  468. temp = scnprintf (next, size, " qh%d-%04x/%p",
  469. p.qh->period,
  470. hc32_to_cpup(ehci,
  471. &p.qh->hw_info2)
  472. /* uframe masks */
  473. & (QH_CMASK | QH_SMASK),
  474. p.qh);
  475. size -= temp;
  476. next += temp;
  477. /* don't repeat what follows this qh */
  478. for (temp = 0; temp < seen_count; temp++) {
  479. if (seen [temp].ptr != p.ptr)
  480. continue;
  481. if (p.qh->qh_next.ptr)
  482. temp = scnprintf (next, size,
  483. " ...");
  484. p.ptr = NULL;
  485. break;
  486. }
  487. /* show more info the first time around */
  488. if (temp == seen_count && p.ptr) {
  489. u32 scratch = hc32_to_cpup(ehci,
  490. &p.qh->hw_info1);
  491. struct ehci_qtd *qtd;
  492. char *type = "";
  493. /* count tds, get ep direction */
  494. temp = 0;
  495. list_for_each_entry (qtd,
  496. &p.qh->qtd_list,
  497. qtd_list) {
  498. temp++;
  499. switch (0x03 & (hc32_to_cpu(
  500. ehci,
  501. qtd->hw_token) >> 8)) {
  502. case 0: type = "out"; continue;
  503. case 1: type = "in"; continue;
  504. }
  505. }
  506. temp = scnprintf (next, size,
  507. " (%c%d ep%d%s "
  508. "[%d/%d] q%d p%d)",
  509. speed_char (scratch),
  510. scratch & 0x007f,
  511. (scratch >> 8) & 0x000f, type,
  512. p.qh->usecs, p.qh->c_usecs,
  513. temp,
  514. 0x7ff & (scratch >> 16));
  515. if (seen_count < DBG_SCHED_LIMIT)
  516. seen [seen_count++].qh = p.qh;
  517. } else
  518. temp = 0;
  519. if (p.qh) {
  520. tag = Q_NEXT_TYPE(ehci, p.qh->hw_next);
  521. p = p.qh->qh_next;
  522. }
  523. break;
  524. case Q_TYPE_FSTN:
  525. temp = scnprintf (next, size,
  526. " fstn-%8x/%p", p.fstn->hw_prev,
  527. p.fstn);
  528. tag = Q_NEXT_TYPE(ehci, p.fstn->hw_next);
  529. p = p.fstn->fstn_next;
  530. break;
  531. case Q_TYPE_ITD:
  532. temp = scnprintf (next, size,
  533. " itd/%p", p.itd);
  534. tag = Q_NEXT_TYPE(ehci, p.itd->hw_next);
  535. p = p.itd->itd_next;
  536. break;
  537. case Q_TYPE_SITD:
  538. temp = scnprintf (next, size,
  539. " sitd%d-%04x/%p",
  540. p.sitd->stream->interval,
  541. hc32_to_cpup(ehci, &p.sitd->hw_uframe)
  542. & 0x0000ffff,
  543. p.sitd);
  544. tag = Q_NEXT_TYPE(ehci, p.sitd->hw_next);
  545. p = p.sitd->sitd_next;
  546. break;
  547. }
  548. size -= temp;
  549. next += temp;
  550. } while (p.ptr);
  551. temp = scnprintf (next, size, "\n");
  552. size -= temp;
  553. next += temp;
  554. }
  555. spin_unlock_irqrestore (&ehci->lock, flags);
  556. kfree (seen);
  557. return PAGE_SIZE - size;
  558. }
  559. static CLASS_DEVICE_ATTR (periodic, S_IRUGO, show_periodic, NULL);
  560. #undef DBG_SCHED_LIMIT
  561. static ssize_t
  562. show_registers (struct class_device *class_dev, char *buf)
  563. {
  564. struct usb_bus *bus;
  565. struct usb_hcd *hcd;
  566. struct ehci_hcd *ehci;
  567. unsigned long flags;
  568. unsigned temp, size, i;
  569. char *next, scratch [80];
  570. static char fmt [] = "%*s\n";
  571. static char label [] = "";
  572. bus = class_get_devdata(class_dev);
  573. hcd = bus_to_hcd(bus);
  574. ehci = hcd_to_ehci (hcd);
  575. next = buf;
  576. size = PAGE_SIZE;
  577. spin_lock_irqsave (&ehci->lock, flags);
  578. if (bus->controller->power.power_state.event) {
  579. size = scnprintf (next, size,
  580. "bus %s, device %s (driver " DRIVER_VERSION ")\n"
  581. "%s\n"
  582. "SUSPENDED (no register access)\n",
  583. hcd->self.controller->bus->name,
  584. hcd->self.controller->bus_id,
  585. hcd->product_desc);
  586. goto done;
  587. }
  588. /* Capability Registers */
  589. i = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
  590. temp = scnprintf (next, size,
  591. "bus %s, device %s (driver " DRIVER_VERSION ")\n"
  592. "%s\n"
  593. "EHCI %x.%02x, hcd state %d\n",
  594. hcd->self.controller->bus->name,
  595. hcd->self.controller->bus_id,
  596. hcd->product_desc,
  597. i >> 8, i & 0x0ff, hcd->state);
  598. size -= temp;
  599. next += temp;
  600. #ifdef CONFIG_PCI
  601. /* EHCI 0.96 and later may have "extended capabilities" */
  602. if (hcd->self.controller->bus == &pci_bus_type) {
  603. struct pci_dev *pdev;
  604. u32 offset, cap, cap2;
  605. unsigned count = 256/4;
  606. pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
  607. offset = HCC_EXT_CAPS(ehci_readl(ehci,
  608. &ehci->caps->hcc_params));
  609. while (offset && count--) {
  610. pci_read_config_dword (pdev, offset, &cap);
  611. switch (cap & 0xff) {
  612. case 1:
  613. temp = scnprintf (next, size,
  614. "ownership %08x%s%s\n", cap,
  615. (cap & (1 << 24)) ? " linux" : "",
  616. (cap & (1 << 16)) ? " firmware" : "");
  617. size -= temp;
  618. next += temp;
  619. offset += 4;
  620. pci_read_config_dword (pdev, offset, &cap2);
  621. temp = scnprintf (next, size,
  622. "SMI sts/enable 0x%08x\n", cap2);
  623. size -= temp;
  624. next += temp;
  625. break;
  626. case 0: /* illegal reserved capability */
  627. cap = 0;
  628. /* FALLTHROUGH */
  629. default: /* unknown */
  630. break;
  631. }
  632. temp = (cap >> 8) & 0xff;
  633. }
  634. }
  635. #endif
  636. // FIXME interpret both types of params
  637. i = ehci_readl(ehci, &ehci->caps->hcs_params);
  638. temp = scnprintf (next, size, "structural params 0x%08x\n", i);
  639. size -= temp;
  640. next += temp;
  641. i = ehci_readl(ehci, &ehci->caps->hcc_params);
  642. temp = scnprintf (next, size, "capability params 0x%08x\n", i);
  643. size -= temp;
  644. next += temp;
  645. /* Operational Registers */
  646. temp = dbg_status_buf (scratch, sizeof scratch, label,
  647. ehci_readl(ehci, &ehci->regs->status));
  648. temp = scnprintf (next, size, fmt, temp, scratch);
  649. size -= temp;
  650. next += temp;
  651. temp = dbg_command_buf (scratch, sizeof scratch, label,
  652. ehci_readl(ehci, &ehci->regs->command));
  653. temp = scnprintf (next, size, fmt, temp, scratch);
  654. size -= temp;
  655. next += temp;
  656. temp = dbg_intr_buf (scratch, sizeof scratch, label,
  657. ehci_readl(ehci, &ehci->regs->intr_enable));
  658. temp = scnprintf (next, size, fmt, temp, scratch);
  659. size -= temp;
  660. next += temp;
  661. temp = scnprintf (next, size, "uframe %04x\n",
  662. ehci_readl(ehci, &ehci->regs->frame_index));
  663. size -= temp;
  664. next += temp;
  665. for (i = 1; i <= HCS_N_PORTS (ehci->hcs_params); i++) {
  666. temp = dbg_port_buf (scratch, sizeof scratch, label, i,
  667. ehci_readl(ehci,
  668. &ehci->regs->port_status[i - 1]));
  669. temp = scnprintf (next, size, fmt, temp, scratch);
  670. size -= temp;
  671. next += temp;
  672. if (i == HCS_DEBUG_PORT(ehci->hcs_params) && ehci->debug) {
  673. temp = scnprintf (next, size,
  674. " debug control %08x\n",
  675. ehci_readl(ehci,
  676. &ehci->debug->control));
  677. size -= temp;
  678. next += temp;
  679. }
  680. }
  681. if (ehci->reclaim) {
  682. temp = scnprintf (next, size, "reclaim qh %p%s\n",
  683. ehci->reclaim,
  684. ehci->reclaim_ready ? " ready" : "");
  685. size -= temp;
  686. next += temp;
  687. }
  688. #ifdef EHCI_STATS
  689. temp = scnprintf (next, size,
  690. "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
  691. ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim,
  692. ehci->stats.lost_iaa);
  693. size -= temp;
  694. next += temp;
  695. temp = scnprintf (next, size, "complete %ld unlink %ld\n",
  696. ehci->stats.complete, ehci->stats.unlink);
  697. size -= temp;
  698. next += temp;
  699. #endif
  700. done:
  701. spin_unlock_irqrestore (&ehci->lock, flags);
  702. return PAGE_SIZE - size;
  703. }
  704. static CLASS_DEVICE_ATTR (registers, S_IRUGO, show_registers, NULL);
  705. static inline void create_debug_files (struct ehci_hcd *ehci)
  706. {
  707. struct class_device *cldev = ehci_to_hcd(ehci)->self.class_dev;
  708. int retval;
  709. retval = class_device_create_file(cldev, &class_device_attr_async);
  710. retval = class_device_create_file(cldev, &class_device_attr_periodic);
  711. retval = class_device_create_file(cldev, &class_device_attr_registers);
  712. }
  713. static inline void remove_debug_files (struct ehci_hcd *ehci)
  714. {
  715. struct class_device *cldev = ehci_to_hcd(ehci)->self.class_dev;
  716. class_device_remove_file(cldev, &class_device_attr_async);
  717. class_device_remove_file(cldev, &class_device_attr_periodic);
  718. class_device_remove_file(cldev, &class_device_attr_registers);
  719. }
  720. #endif /* STUB_DEBUG_FILES */