s3c2410_udc.c 48 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/smp_lock.h>
  31. #include <linux/errno.h>
  32. #include <linux/init.h>
  33. #include <linux/timer.h>
  34. #include <linux/list.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/version.h>
  38. #include <linux/clk.h>
  39. #include <linux/debugfs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/usb.h>
  42. #include <linux/usb/gadget.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/system.h>
  47. #include <asm/unaligned.h>
  48. #include <asm/arch/irqs.h>
  49. #include <asm/arch/hardware.h>
  50. #include <asm/arch/regs-clock.h>
  51. #include <asm/arch/regs-gpio.h>
  52. #include <asm/arch/regs-udc.h>
  53. #include <asm/arch/udc.h>
  54. #include <asm/mach-types.h>
  55. #include "s3c2410_udc.h"
  56. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  57. #define DRIVER_VERSION "29 Apr 2007"
  58. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  59. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  60. static const char gadget_name[] = "s3c2410_udc";
  61. static const char driver_desc[] = DRIVER_DESC;
  62. static struct s3c2410_udc *the_controller;
  63. static struct clk *udc_clock;
  64. static struct clk *usb_bus_clock;
  65. static void __iomem *base_addr;
  66. static u64 rsrc_start;
  67. static u64 rsrc_len;
  68. static struct dentry *s3c2410_udc_debugfs_root;
  69. static inline u32 udc_read(u32 reg)
  70. {
  71. return readb(base_addr + reg);
  72. }
  73. static inline void udc_write(u32 value, u32 reg)
  74. {
  75. writeb(value, base_addr + reg);
  76. }
  77. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  78. {
  79. writeb(value, base + reg);
  80. }
  81. static struct s3c2410_udc_mach_info *udc_info;
  82. /*************************** DEBUG FUNCTION ***************************/
  83. #define DEBUG_NORMAL 1
  84. #define DEBUG_VERBOSE 2
  85. #ifdef CONFIG_USB_S3C2410_DEBUG
  86. #define USB_S3C2410_DEBUG_LEVEL 0
  87. static uint32_t s3c2410_ticks = 0;
  88. static int dprintk(int level, const char *fmt, ...)
  89. {
  90. static char printk_buf[1024];
  91. static long prevticks;
  92. static int invocation;
  93. va_list args;
  94. int len;
  95. if (level > USB_S3C2410_DEBUG_LEVEL)
  96. return 0;
  97. if (s3c2410_ticks != prevticks) {
  98. prevticks = s3c2410_ticks;
  99. invocation = 0;
  100. }
  101. len = scnprintf(printk_buf,
  102. sizeof(printk_buf), "%1lu.%02d USB: ",
  103. prevticks, invocation++);
  104. va_start(args, fmt);
  105. len = vscnprintf(printk_buf+len,
  106. sizeof(printk_buf)-len, fmt, args);
  107. va_end(args);
  108. return printk(KERN_DEBUG "%s", printk_buf);
  109. }
  110. #else
  111. static int dprintk(int level, const char *fmt, ...)
  112. {
  113. return 0;
  114. }
  115. #endif
  116. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  117. {
  118. u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
  119. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  120. u32 ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2;
  121. u32 ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2;
  122. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  123. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  124. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  125. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  126. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  127. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  128. udc_write(0, S3C2410_UDC_INDEX_REG);
  129. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  130. udc_write(1, S3C2410_UDC_INDEX_REG);
  131. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  132. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  133. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  134. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  135. udc_write(2, S3C2410_UDC_INDEX_REG);
  136. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  137. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  138. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  139. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  140. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  141. "PWR_REG : 0x%04X\n"
  142. "EP_INT_REG : 0x%04X\n"
  143. "USB_INT_REG : 0x%04X\n"
  144. "EP_INT_EN_REG : 0x%04X\n"
  145. "USB_INT_EN_REG : 0x%04X\n"
  146. "EP0_CSR : 0x%04X\n"
  147. "EP1_I_CSR1 : 0x%04X\n"
  148. "EP1_I_CSR2 : 0x%04X\n"
  149. "EP1_O_CSR1 : 0x%04X\n"
  150. "EP1_O_CSR2 : 0x%04X\n"
  151. "EP2_I_CSR1 : 0x%04X\n"
  152. "EP2_I_CSR2 : 0x%04X\n"
  153. "EP2_O_CSR1 : 0x%04X\n"
  154. "EP2_O_CSR2 : 0x%04X\n",
  155. addr_reg,pwr_reg,ep_int_reg,usb_int_reg,
  156. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  157. ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2,
  158. ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2
  159. );
  160. return 0;
  161. }
  162. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  163. struct file *file)
  164. {
  165. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  166. }
  167. static const struct file_operations s3c2410_udc_debugfs_fops = {
  168. .open = s3c2410_udc_debugfs_fops_open,
  169. .read = seq_read,
  170. .llseek = seq_lseek,
  171. .release = single_release,
  172. .owner = THIS_MODULE,
  173. };
  174. /* io macros */
  175. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  176. {
  177. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  178. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  179. S3C2410_UDC_EP0_CSR_REG);
  180. }
  181. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  182. {
  183. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  184. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  185. }
  186. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  187. {
  188. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  189. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  190. }
  191. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  192. {
  193. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  194. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  195. }
  196. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  197. {
  198. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  199. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  200. }
  201. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  202. {
  203. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  204. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  205. }
  206. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  207. {
  208. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  209. udc_writeb(base,(S3C2410_UDC_EP0_CSR_SOPKTRDY
  210. | S3C2410_UDC_EP0_CSR_DE),
  211. S3C2410_UDC_EP0_CSR_REG);
  212. }
  213. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  214. {
  215. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  216. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  217. | S3C2410_UDC_EP0_CSR_SSE),
  218. S3C2410_UDC_EP0_CSR_REG);
  219. }
  220. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  221. {
  222. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  223. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  224. | S3C2410_UDC_EP0_CSR_DE),
  225. S3C2410_UDC_EP0_CSR_REG);
  226. }
  227. /*------------------------- I/O ----------------------------------*/
  228. /*
  229. * s3c2410_udc_done
  230. */
  231. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  232. struct s3c2410_request *req, int status)
  233. {
  234. unsigned halted = ep->halted;
  235. list_del_init(&req->queue);
  236. if (likely (req->req.status == -EINPROGRESS))
  237. req->req.status = status;
  238. else
  239. status = req->req.status;
  240. ep->halted = 1;
  241. req->req.complete(&ep->ep, &req->req);
  242. ep->halted = halted;
  243. }
  244. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  245. struct s3c2410_ep *ep, int status)
  246. {
  247. /* Sanity check */
  248. if (&ep->queue == NULL)
  249. return;
  250. while (!list_empty (&ep->queue)) {
  251. struct s3c2410_request *req;
  252. req = list_entry (ep->queue.next, struct s3c2410_request,
  253. queue);
  254. s3c2410_udc_done(ep, req, status);
  255. }
  256. }
  257. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  258. {
  259. unsigned i;
  260. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  261. * fifos, and pending transactions mustn't be continued in any case.
  262. */
  263. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  264. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  265. }
  266. static inline int s3c2410_udc_fifo_count_out(void)
  267. {
  268. int tmp;
  269. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  270. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  271. return tmp;
  272. }
  273. /*
  274. * s3c2410_udc_write_packet
  275. */
  276. static inline int s3c2410_udc_write_packet(int fifo,
  277. struct s3c2410_request *req,
  278. unsigned max)
  279. {
  280. unsigned len = min(req->req.length - req->req.actual, max);
  281. u8 *buf = req->req.buf + req->req.actual;
  282. prefetch(buf);
  283. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  284. req->req.actual, req->req.length, len, req->req.actual + len);
  285. req->req.actual += len;
  286. udelay(5);
  287. writesb(base_addr + fifo, buf, len);
  288. return len;
  289. }
  290. /*
  291. * s3c2410_udc_write_fifo
  292. *
  293. * return: 0 = still running, 1 = completed, negative = errno
  294. */
  295. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  296. struct s3c2410_request *req)
  297. {
  298. unsigned count;
  299. int is_last;
  300. u32 idx;
  301. int fifo_reg;
  302. u32 ep_csr;
  303. idx = ep->bEndpointAddress & 0x7F;
  304. switch (idx) {
  305. default:
  306. idx = 0;
  307. case 0:
  308. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  309. break;
  310. case 1:
  311. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  312. break;
  313. case 2:
  314. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  315. break;
  316. case 3:
  317. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  318. break;
  319. case 4:
  320. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  321. break;
  322. }
  323. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  324. /* last packet is often short (sometimes a zlp) */
  325. if (count != ep->ep.maxpacket)
  326. is_last = 1;
  327. else if (req->req.length != req->req.actual || req->req.zero)
  328. is_last = 0;
  329. else
  330. is_last = 2;
  331. /* Only ep0 debug messages are interesting */
  332. if (idx == 0)
  333. dprintk(DEBUG_NORMAL,
  334. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  335. idx, count, req->req.actual, req->req.length,
  336. is_last, req->req.zero);
  337. if (is_last) {
  338. /* The order is important. It prevents sending 2 packets
  339. * at the same time */
  340. if (idx == 0) {
  341. /* Reset signal => no need to say 'data sent' */
  342. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  343. & S3C2410_UDC_USBINT_RESET))
  344. s3c2410_udc_set_ep0_de_in(base_addr);
  345. ep->dev->ep0state=EP0_IDLE;
  346. } else {
  347. udc_write(idx, S3C2410_UDC_INDEX_REG);
  348. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  349. udc_write(idx, S3C2410_UDC_INDEX_REG);
  350. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  351. S3C2410_UDC_IN_CSR1_REG);
  352. }
  353. s3c2410_udc_done(ep, req, 0);
  354. is_last = 1;
  355. } else {
  356. if (idx == 0) {
  357. /* Reset signal => no need to say 'data sent' */
  358. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  359. & S3C2410_UDC_USBINT_RESET))
  360. s3c2410_udc_set_ep0_ipr(base_addr);
  361. } else {
  362. udc_write(idx, S3C2410_UDC_INDEX_REG);
  363. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  364. udc_write(idx, S3C2410_UDC_INDEX_REG);
  365. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  366. S3C2410_UDC_IN_CSR1_REG);
  367. }
  368. }
  369. return is_last;
  370. }
  371. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  372. struct s3c2410_request *req, unsigned avail)
  373. {
  374. unsigned len;
  375. len = min(req->req.length - req->req.actual, avail);
  376. req->req.actual += len;
  377. readsb(fifo + base_addr, buf, len);
  378. return len;
  379. }
  380. /*
  381. * return: 0 = still running, 1 = queue empty, negative = errno
  382. */
  383. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  384. struct s3c2410_request *req)
  385. {
  386. u8 *buf;
  387. u32 ep_csr;
  388. unsigned bufferspace;
  389. int is_last=1;
  390. unsigned avail;
  391. int fifo_count = 0;
  392. u32 idx;
  393. int fifo_reg;
  394. idx = ep->bEndpointAddress & 0x7F;
  395. switch (idx) {
  396. default:
  397. idx = 0;
  398. case 0:
  399. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  400. break;
  401. case 1:
  402. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  403. break;
  404. case 2:
  405. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  406. break;
  407. case 3:
  408. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  409. break;
  410. case 4:
  411. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  412. break;
  413. }
  414. if (!req->req.length)
  415. return 1;
  416. buf = req->req.buf + req->req.actual;
  417. bufferspace = req->req.length - req->req.actual;
  418. if (!bufferspace) {
  419. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  420. return -1;
  421. }
  422. udc_write(idx, S3C2410_UDC_INDEX_REG);
  423. fifo_count = s3c2410_udc_fifo_count_out();
  424. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  425. if (fifo_count > ep->ep.maxpacket)
  426. avail = ep->ep.maxpacket;
  427. else
  428. avail = fifo_count;
  429. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  430. /* checking this with ep0 is not accurate as we already
  431. * read a control request
  432. **/
  433. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  434. is_last = 1;
  435. /* overflowed this request? flush extra data */
  436. if (fifo_count != avail)
  437. req->req.status = -EOVERFLOW;
  438. } else {
  439. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  440. }
  441. udc_write(idx, S3C2410_UDC_INDEX_REG);
  442. fifo_count = s3c2410_udc_fifo_count_out();
  443. /* Only ep0 debug messages are interesting */
  444. if (idx == 0)
  445. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  446. __func__, fifo_count,is_last);
  447. if (is_last) {
  448. if (idx == 0) {
  449. s3c2410_udc_set_ep0_de_out(base_addr);
  450. ep->dev->ep0state = EP0_IDLE;
  451. } else {
  452. udc_write(idx, S3C2410_UDC_INDEX_REG);
  453. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  454. udc_write(idx, S3C2410_UDC_INDEX_REG);
  455. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  456. S3C2410_UDC_OUT_CSR1_REG);
  457. }
  458. s3c2410_udc_done(ep, req, 0);
  459. } else {
  460. if (idx == 0) {
  461. s3c2410_udc_clear_ep0_opr(base_addr);
  462. } else {
  463. udc_write(idx, S3C2410_UDC_INDEX_REG);
  464. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  465. udc_write(idx, S3C2410_UDC_INDEX_REG);
  466. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  467. S3C2410_UDC_OUT_CSR1_REG);
  468. }
  469. }
  470. return is_last;
  471. }
  472. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  473. {
  474. unsigned char *outbuf = (unsigned char*)crq;
  475. int bytes_read = 0;
  476. udc_write(0, S3C2410_UDC_INDEX_REG);
  477. bytes_read = s3c2410_udc_fifo_count_out();
  478. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  479. if (bytes_read > sizeof(struct usb_ctrlrequest))
  480. bytes_read = sizeof(struct usb_ctrlrequest);
  481. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  482. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  483. bytes_read, crq->bRequest, crq->bRequestType,
  484. crq->wValue, crq->wIndex, crq->wLength);
  485. return bytes_read;
  486. }
  487. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  488. struct usb_ctrlrequest *crq)
  489. {
  490. u16 status = 0;
  491. u8 ep_num = crq->wIndex & 0x7F;
  492. u8 is_in = crq->wIndex & USB_DIR_IN;
  493. switch (crq->bRequestType & USB_RECIP_MASK) {
  494. case USB_RECIP_INTERFACE:
  495. break;
  496. case USB_RECIP_DEVICE:
  497. status = dev->devstatus;
  498. break;
  499. case USB_RECIP_ENDPOINT:
  500. if (ep_num > 4 || crq->wLength > 2)
  501. return 1;
  502. if (ep_num == 0) {
  503. udc_write(0, S3C2410_UDC_INDEX_REG);
  504. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  505. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  506. } else {
  507. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  508. if (is_in) {
  509. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  510. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  511. } else {
  512. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  513. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  514. }
  515. }
  516. status = status ? 1 : 0;
  517. break;
  518. default:
  519. return 1;
  520. }
  521. /* Seems to be needed to get it working. ouch :( */
  522. udelay(5);
  523. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  524. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  525. s3c2410_udc_set_ep0_de_in(base_addr);
  526. return 0;
  527. }
  528. /*------------------------- usb state machine -------------------------------*/
  529. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  530. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  531. struct s3c2410_ep *ep,
  532. struct usb_ctrlrequest *crq,
  533. u32 ep0csr)
  534. {
  535. int len, ret, tmp;
  536. /* start control request? */
  537. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  538. return;
  539. s3c2410_udc_nuke(dev, ep, -EPROTO);
  540. len = s3c2410_udc_read_fifo_crq(crq);
  541. if (len != sizeof(*crq)) {
  542. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  543. " wanted %d bytes got %d. Stalling out...\n",
  544. sizeof(*crq), len);
  545. s3c2410_udc_set_ep0_ss(base_addr);
  546. return;
  547. }
  548. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  549. crq->bRequest, crq->bRequestType, crq->wLength);
  550. /* cope with automagic for some standard requests. */
  551. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  552. == USB_TYPE_STANDARD;
  553. dev->req_config = 0;
  554. dev->req_pending = 1;
  555. switch (crq->bRequest) {
  556. case USB_REQ_SET_CONFIGURATION:
  557. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ... \n");
  558. if (crq->bRequestType == USB_RECIP_DEVICE) {
  559. dev->req_config = 1;
  560. s3c2410_udc_set_ep0_de_out(base_addr);
  561. }
  562. break;
  563. case USB_REQ_SET_INTERFACE:
  564. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ... \n");
  565. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  566. dev->req_config = 1;
  567. s3c2410_udc_set_ep0_de_out(base_addr);
  568. }
  569. break;
  570. case USB_REQ_SET_ADDRESS:
  571. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ... \n");
  572. if (crq->bRequestType == USB_RECIP_DEVICE) {
  573. tmp = crq->wValue & 0x7F;
  574. dev->address = tmp;
  575. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  576. S3C2410_UDC_FUNC_ADDR_REG);
  577. s3c2410_udc_set_ep0_de_out(base_addr);
  578. return;
  579. }
  580. break;
  581. case USB_REQ_GET_STATUS:
  582. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ... \n");
  583. s3c2410_udc_clear_ep0_opr(base_addr);
  584. if (dev->req_std) {
  585. if (!s3c2410_udc_get_status(dev, crq)) {
  586. return;
  587. }
  588. }
  589. break;
  590. case USB_REQ_CLEAR_FEATURE:
  591. s3c2410_udc_clear_ep0_opr(base_addr);
  592. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  593. break;
  594. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  595. break;
  596. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  597. s3c2410_udc_set_ep0_de_out(base_addr);
  598. return;
  599. case USB_REQ_SET_FEATURE:
  600. s3c2410_udc_clear_ep0_opr(base_addr);
  601. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  602. break;
  603. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  604. break;
  605. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  606. s3c2410_udc_set_ep0_de_out(base_addr);
  607. return;
  608. default:
  609. s3c2410_udc_clear_ep0_opr(base_addr);
  610. break;
  611. }
  612. if (crq->bRequestType & USB_DIR_IN)
  613. dev->ep0state = EP0_IN_DATA_PHASE;
  614. else
  615. dev->ep0state = EP0_OUT_DATA_PHASE;
  616. ret = dev->driver->setup(&dev->gadget, crq);
  617. if (ret < 0) {
  618. if (dev->req_config) {
  619. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  620. crq->bRequest, ret);
  621. return;
  622. }
  623. if (ret == -EOPNOTSUPP)
  624. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  625. else
  626. dprintk(DEBUG_NORMAL,
  627. "dev->driver->setup failed. (%d)\n", ret);
  628. udelay(5);
  629. s3c2410_udc_set_ep0_ss(base_addr);
  630. s3c2410_udc_set_ep0_de_out(base_addr);
  631. dev->ep0state = EP0_IDLE;
  632. /* deferred i/o == no response yet */
  633. } else if (dev->req_pending) {
  634. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  635. dev->req_pending=0;
  636. }
  637. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  638. }
  639. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  640. {
  641. u32 ep0csr;
  642. struct s3c2410_ep *ep = &dev->ep[0];
  643. struct s3c2410_request *req;
  644. struct usb_ctrlrequest crq;
  645. if (list_empty(&ep->queue))
  646. req = NULL;
  647. else
  648. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  649. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  650. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  651. udc_write(0, S3C2410_UDC_INDEX_REG);
  652. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  653. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  654. ep0csr, ep0states[dev->ep0state]);
  655. /* clear stall status */
  656. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  657. s3c2410_udc_nuke(dev, ep, -EPIPE);
  658. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  659. s3c2410_udc_clear_ep0_sst(base_addr);
  660. dev->ep0state = EP0_IDLE;
  661. return;
  662. }
  663. /* clear setup end */
  664. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  665. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  666. s3c2410_udc_nuke(dev, ep, 0);
  667. s3c2410_udc_clear_ep0_se(base_addr);
  668. dev->ep0state = EP0_IDLE;
  669. }
  670. switch (dev->ep0state) {
  671. case EP0_IDLE:
  672. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  673. break;
  674. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  675. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  676. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req) {
  677. s3c2410_udc_write_fifo(ep, req);
  678. }
  679. break;
  680. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  681. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  682. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req ) {
  683. s3c2410_udc_read_fifo(ep,req);
  684. }
  685. break;
  686. case EP0_END_XFER:
  687. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  688. dev->ep0state = EP0_IDLE;
  689. break;
  690. case EP0_STALL:
  691. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  692. dev->ep0state = EP0_IDLE;
  693. break;
  694. }
  695. }
  696. /*
  697. * handle_ep - Manage I/O endpoints
  698. */
  699. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  700. {
  701. struct s3c2410_request *req;
  702. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  703. u32 ep_csr1;
  704. u32 idx;
  705. if (likely (!list_empty(&ep->queue)))
  706. req = list_entry(ep->queue.next,
  707. struct s3c2410_request, queue);
  708. else
  709. req = NULL;
  710. idx = ep->bEndpointAddress & 0x7F;
  711. if (is_in) {
  712. udc_write(idx, S3C2410_UDC_INDEX_REG);
  713. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  714. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  715. idx, ep_csr1, req ? 1 : 0);
  716. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  717. dprintk(DEBUG_VERBOSE, "st\n");
  718. udc_write(idx, S3C2410_UDC_INDEX_REG);
  719. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  720. S3C2410_UDC_IN_CSR1_REG);
  721. return;
  722. }
  723. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req) {
  724. s3c2410_udc_write_fifo(ep,req);
  725. }
  726. } else {
  727. udc_write(idx, S3C2410_UDC_INDEX_REG);
  728. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  729. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  730. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  731. udc_write(idx, S3C2410_UDC_INDEX_REG);
  732. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  733. S3C2410_UDC_OUT_CSR1_REG);
  734. return;
  735. }
  736. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
  737. s3c2410_udc_read_fifo(ep,req);
  738. }
  739. }
  740. }
  741. #include <asm/arch/regs-irq.h>
  742. /*
  743. * s3c2410_udc_irq - interrupt handler
  744. */
  745. static irqreturn_t s3c2410_udc_irq(int irq, void *_dev)
  746. {
  747. struct s3c2410_udc *dev = _dev;
  748. int usb_status;
  749. int usbd_status;
  750. int pwr_reg;
  751. int ep0csr;
  752. int i;
  753. u32 idx;
  754. unsigned long flags;
  755. spin_lock_irqsave(&dev->lock, flags);
  756. /* Driver connected ? */
  757. if (!dev->driver) {
  758. /* Clear interrupts */
  759. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  760. S3C2410_UDC_USB_INT_REG);
  761. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  762. S3C2410_UDC_EP_INT_REG);
  763. }
  764. /* Save index */
  765. idx = udc_read(S3C2410_UDC_INDEX_REG);
  766. /* Read status registers */
  767. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  768. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  769. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  770. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  771. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  772. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  773. usb_status, usbd_status, pwr_reg, ep0csr);
  774. /*
  775. * Now, handle interrupts. There's two types :
  776. * - Reset, Resume, Suspend coming -> usb_int_reg
  777. * - EP -> ep_int_reg
  778. */
  779. /* RESET */
  780. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  781. /* two kind of reset :
  782. * - reset start -> pwr reg = 8
  783. * - reset end -> pwr reg = 0
  784. **/
  785. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  786. ep0csr, pwr_reg);
  787. dev->gadget.speed = USB_SPEED_UNKNOWN;
  788. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  789. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  790. S3C2410_UDC_MAXP_REG);
  791. dev->address = 0;
  792. dev->ep0state = EP0_IDLE;
  793. dev->gadget.speed = USB_SPEED_FULL;
  794. /* clear interrupt */
  795. udc_write(S3C2410_UDC_USBINT_RESET,
  796. S3C2410_UDC_USB_INT_REG);
  797. udc_write(idx, S3C2410_UDC_INDEX_REG);
  798. spin_unlock_irqrestore(&dev->lock, flags);
  799. return IRQ_HANDLED;
  800. }
  801. /* RESUME */
  802. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  803. dprintk(DEBUG_NORMAL, "USB resume\n");
  804. /* clear interrupt */
  805. udc_write(S3C2410_UDC_USBINT_RESUME,
  806. S3C2410_UDC_USB_INT_REG);
  807. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  808. && dev->driver
  809. && dev->driver->resume)
  810. dev->driver->resume(&dev->gadget);
  811. }
  812. /* SUSPEND */
  813. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  814. dprintk(DEBUG_NORMAL, "USB suspend\n");
  815. /* clear interrupt */
  816. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  817. S3C2410_UDC_USB_INT_REG);
  818. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  819. && dev->driver
  820. && dev->driver->suspend)
  821. dev->driver->suspend(&dev->gadget);
  822. dev->ep0state = EP0_IDLE;
  823. }
  824. /* EP */
  825. /* control traffic */
  826. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  827. * generate an interrupt
  828. */
  829. if (usbd_status & S3C2410_UDC_INT_EP0) {
  830. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  831. /* Clear the interrupt bit by setting it to 1 */
  832. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  833. s3c2410_udc_handle_ep0(dev);
  834. }
  835. /* endpoint data transfers */
  836. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  837. u32 tmp = 1 << i;
  838. if (usbd_status & tmp) {
  839. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  840. /* Clear the interrupt bit by setting it to 1 */
  841. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  842. s3c2410_udc_handle_ep(&dev->ep[i]);
  843. }
  844. }
  845. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", irq);
  846. /* Restore old index */
  847. udc_write(idx, S3C2410_UDC_INDEX_REG);
  848. spin_unlock_irqrestore(&dev->lock, flags);
  849. return IRQ_HANDLED;
  850. }
  851. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  852. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  853. {
  854. return container_of(ep, struct s3c2410_ep, ep);
  855. }
  856. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  857. {
  858. return container_of(gadget, struct s3c2410_udc, gadget);
  859. }
  860. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  861. {
  862. return container_of(req, struct s3c2410_request, req);
  863. }
  864. /*
  865. * s3c2410_udc_ep_enable
  866. */
  867. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  868. const struct usb_endpoint_descriptor *desc)
  869. {
  870. struct s3c2410_udc *dev;
  871. struct s3c2410_ep *ep;
  872. u32 max, tmp;
  873. unsigned long flags;
  874. u32 csr1,csr2;
  875. u32 int_en_reg;
  876. ep = to_s3c2410_ep(_ep);
  877. if (!_ep || !desc || ep->desc
  878. || _ep->name == ep0name
  879. || desc->bDescriptorType != USB_DT_ENDPOINT)
  880. return -EINVAL;
  881. dev = ep->dev;
  882. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  883. return -ESHUTDOWN;
  884. max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff;
  885. local_irq_save (flags);
  886. _ep->maxpacket = max & 0x7ff;
  887. ep->desc = desc;
  888. ep->halted = 0;
  889. ep->bEndpointAddress = desc->bEndpointAddress;
  890. /* set max packet */
  891. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  892. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  893. /* set type, direction, address; reset fifo counters */
  894. if (desc->bEndpointAddress & USB_DIR_IN) {
  895. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  896. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  897. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  898. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  899. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  900. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  901. } else {
  902. /* don't flush in fifo or it will cause endpoint interrupt */
  903. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  904. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  905. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  906. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  907. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  908. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  909. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  910. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  911. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  912. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  913. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  914. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  915. }
  916. /* enable irqs */
  917. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  918. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  919. /* print some debug message */
  920. tmp = desc->bEndpointAddress;
  921. dprintk (DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  922. _ep->name,ep->num, tmp,
  923. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  924. local_irq_restore (flags);
  925. s3c2410_udc_set_halt(_ep, 0);
  926. return 0;
  927. }
  928. /*
  929. * s3c2410_udc_ep_disable
  930. */
  931. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  932. {
  933. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  934. unsigned long flags;
  935. u32 int_en_reg;
  936. if (!_ep || !ep->desc) {
  937. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  938. _ep ? ep->ep.name : NULL);
  939. return -EINVAL;
  940. }
  941. local_irq_save(flags);
  942. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  943. ep->desc = NULL;
  944. ep->halted = 1;
  945. s3c2410_udc_nuke (ep->dev, ep, -ESHUTDOWN);
  946. /* disable irqs */
  947. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  948. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  949. local_irq_restore(flags);
  950. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  951. return 0;
  952. }
  953. /*
  954. * s3c2410_udc_alloc_request
  955. */
  956. static struct usb_request *
  957. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  958. {
  959. struct s3c2410_request *req;
  960. dprintk(DEBUG_VERBOSE,"%s(%p,%d)\n", __func__, _ep, mem_flags);
  961. if (!_ep)
  962. return NULL;
  963. req = kzalloc (sizeof(struct s3c2410_request), mem_flags);
  964. if (!req)
  965. return NULL;
  966. INIT_LIST_HEAD (&req->queue);
  967. return &req->req;
  968. }
  969. /*
  970. * s3c2410_udc_free_request
  971. */
  972. static void
  973. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  974. {
  975. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  976. struct s3c2410_request *req = to_s3c2410_req(_req);
  977. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  978. if (!ep || !_req || (!ep->desc && _ep->name != ep0name))
  979. return;
  980. WARN_ON (!list_empty (&req->queue));
  981. kfree(req);
  982. }
  983. /*
  984. * s3c2410_udc_queue
  985. */
  986. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  987. gfp_t gfp_flags)
  988. {
  989. struct s3c2410_request *req = to_s3c2410_req(_req);
  990. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  991. struct s3c2410_udc *dev;
  992. u32 ep_csr = 0;
  993. int fifo_count = 0;
  994. unsigned long flags;
  995. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  996. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  997. return -EINVAL;
  998. }
  999. dev = ep->dev;
  1000. if (unlikely (!dev->driver
  1001. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  1002. return -ESHUTDOWN;
  1003. }
  1004. local_irq_save (flags);
  1005. if (unlikely(!_req || !_req->complete
  1006. || !_req->buf || !list_empty(&req->queue))) {
  1007. if (!_req)
  1008. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1009. else {
  1010. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1011. __func__, !_req->complete,!_req->buf,
  1012. !list_empty(&req->queue));
  1013. }
  1014. local_irq_restore(flags);
  1015. return -EINVAL;
  1016. }
  1017. _req->status = -EINPROGRESS;
  1018. _req->actual = 0;
  1019. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1020. __func__, ep->bEndpointAddress, _req->length);
  1021. if (ep->bEndpointAddress) {
  1022. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1023. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1024. ? S3C2410_UDC_IN_CSR1_REG
  1025. : S3C2410_UDC_OUT_CSR1_REG);
  1026. fifo_count = s3c2410_udc_fifo_count_out();
  1027. } else {
  1028. udc_write(0, S3C2410_UDC_INDEX_REG);
  1029. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1030. fifo_count = s3c2410_udc_fifo_count_out();
  1031. }
  1032. /* kickstart this i/o queue? */
  1033. if (list_empty(&ep->queue) && !ep->halted) {
  1034. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1035. switch (dev->ep0state) {
  1036. case EP0_IN_DATA_PHASE:
  1037. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1038. && s3c2410_udc_write_fifo(ep,
  1039. req)) {
  1040. dev->ep0state = EP0_IDLE;
  1041. req = NULL;
  1042. }
  1043. break;
  1044. case EP0_OUT_DATA_PHASE:
  1045. if ((!_req->length)
  1046. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1047. && s3c2410_udc_read_fifo(ep,
  1048. req))) {
  1049. dev->ep0state = EP0_IDLE;
  1050. req = NULL;
  1051. }
  1052. break;
  1053. default:
  1054. local_irq_restore(flags);
  1055. return -EL2HLT;
  1056. }
  1057. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1058. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1059. && s3c2410_udc_write_fifo(ep, req)) {
  1060. req = NULL;
  1061. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1062. && fifo_count
  1063. && s3c2410_udc_read_fifo(ep, req)) {
  1064. req = NULL;
  1065. }
  1066. }
  1067. /* pio or dma irq handler advances the queue. */
  1068. if (likely (req != 0))
  1069. list_add_tail(&req->queue, &ep->queue);
  1070. local_irq_restore(flags);
  1071. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1072. return 0;
  1073. }
  1074. /*
  1075. * s3c2410_udc_dequeue
  1076. */
  1077. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1078. {
  1079. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1080. struct s3c2410_udc *udc;
  1081. int retval = -EINVAL;
  1082. unsigned long flags;
  1083. struct s3c2410_request *req = NULL;
  1084. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1085. if (!the_controller->driver)
  1086. return -ESHUTDOWN;
  1087. if (!_ep || !_req)
  1088. return retval;
  1089. udc = to_s3c2410_udc(ep->gadget);
  1090. local_irq_save (flags);
  1091. list_for_each_entry (req, &ep->queue, queue) {
  1092. if (&req->req == _req) {
  1093. list_del_init (&req->queue);
  1094. _req->status = -ECONNRESET;
  1095. retval = 0;
  1096. break;
  1097. }
  1098. }
  1099. if (retval == 0) {
  1100. dprintk(DEBUG_VERBOSE,
  1101. "dequeued req %p from %s, len %d buf %p\n",
  1102. req, _ep->name, _req->length, _req->buf);
  1103. s3c2410_udc_done(ep, req, -ECONNRESET);
  1104. }
  1105. local_irq_restore (flags);
  1106. return retval;
  1107. }
  1108. /*
  1109. * s3c2410_udc_set_halt
  1110. */
  1111. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1112. {
  1113. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1114. u32 ep_csr = 0;
  1115. unsigned long flags;
  1116. u32 idx;
  1117. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1118. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1119. return -EINVAL;
  1120. }
  1121. local_irq_save (flags);
  1122. idx = ep->bEndpointAddress & 0x7F;
  1123. if (idx == 0) {
  1124. s3c2410_udc_set_ep0_ss(base_addr);
  1125. s3c2410_udc_set_ep0_de_out(base_addr);
  1126. } else {
  1127. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1128. ep_csr = udc_read((ep->bEndpointAddress &USB_DIR_IN)
  1129. ? S3C2410_UDC_IN_CSR1_REG
  1130. : S3C2410_UDC_OUT_CSR1_REG);
  1131. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1132. if (value)
  1133. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1134. S3C2410_UDC_IN_CSR1_REG);
  1135. else {
  1136. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1137. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1138. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1139. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1140. }
  1141. } else {
  1142. if (value)
  1143. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1144. S3C2410_UDC_OUT_CSR1_REG);
  1145. else {
  1146. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1147. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1148. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1149. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1150. }
  1151. }
  1152. }
  1153. ep->halted = value ? 1 : 0;
  1154. local_irq_restore (flags);
  1155. return 0;
  1156. }
  1157. static const struct usb_ep_ops s3c2410_ep_ops = {
  1158. .enable = s3c2410_udc_ep_enable,
  1159. .disable = s3c2410_udc_ep_disable,
  1160. .alloc_request = s3c2410_udc_alloc_request,
  1161. .free_request = s3c2410_udc_free_request,
  1162. .queue = s3c2410_udc_queue,
  1163. .dequeue = s3c2410_udc_dequeue,
  1164. .set_halt = s3c2410_udc_set_halt,
  1165. };
  1166. /*------------------------- usb_gadget_ops ----------------------------------*/
  1167. /*
  1168. * s3c2410_udc_get_frame
  1169. */
  1170. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1171. {
  1172. int tmp;
  1173. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1174. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1175. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1176. return tmp;
  1177. }
  1178. /*
  1179. * s3c2410_udc_wakeup
  1180. */
  1181. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1182. {
  1183. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1184. return 0;
  1185. }
  1186. /*
  1187. * s3c2410_udc_set_selfpowered
  1188. */
  1189. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1190. {
  1191. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1192. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1193. if (value)
  1194. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1195. else
  1196. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1197. return 0;
  1198. }
  1199. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1200. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1201. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1202. {
  1203. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1204. if (udc_info && udc_info->udc_command) {
  1205. if (is_on)
  1206. s3c2410_udc_enable(udc);
  1207. else {
  1208. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1209. if (udc->driver && udc->driver->disconnect)
  1210. udc->driver->disconnect(&udc->gadget);
  1211. }
  1212. s3c2410_udc_disable(udc);
  1213. }
  1214. }
  1215. else
  1216. return -EOPNOTSUPP;
  1217. return 0;
  1218. }
  1219. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1220. {
  1221. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1222. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1223. udc->vbus = (is_active != 0);
  1224. s3c2410_udc_set_pullup(udc, is_active);
  1225. return 0;
  1226. }
  1227. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1228. {
  1229. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1230. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1231. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1232. return 0;
  1233. }
  1234. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1235. {
  1236. struct s3c2410_udc *dev = _dev;
  1237. unsigned int value;
  1238. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1239. value = s3c2410_gpio_getpin(udc_info->vbus_pin);
  1240. if (udc_info->vbus_pin_inverted)
  1241. value = !value;
  1242. if (value != dev->vbus)
  1243. s3c2410_udc_vbus_session(&dev->gadget, value);
  1244. return IRQ_HANDLED;
  1245. }
  1246. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1247. {
  1248. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1249. if (udc_info && udc_info->vbus_draw) {
  1250. udc_info->vbus_draw(ma);
  1251. return 0;
  1252. }
  1253. return -ENOTSUPP;
  1254. }
  1255. static const struct usb_gadget_ops s3c2410_ops = {
  1256. .get_frame = s3c2410_udc_get_frame,
  1257. .wakeup = s3c2410_udc_wakeup,
  1258. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1259. .pullup = s3c2410_udc_pullup,
  1260. .vbus_session = s3c2410_udc_vbus_session,
  1261. .vbus_draw = s3c2410_vbus_draw,
  1262. };
  1263. /*------------------------- gadget driver handling---------------------------*/
  1264. /*
  1265. * s3c2410_udc_disable
  1266. */
  1267. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1268. {
  1269. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1270. /* Disable all interrupts */
  1271. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1272. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1273. /* Clear the interrupt registers */
  1274. udc_write(S3C2410_UDC_USBINT_RESET
  1275. | S3C2410_UDC_USBINT_RESUME
  1276. | S3C2410_UDC_USBINT_SUSPEND,
  1277. S3C2410_UDC_USB_INT_REG);
  1278. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1279. /* Good bye, cruel world */
  1280. if (udc_info && udc_info->udc_command)
  1281. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1282. /* Set speed to unknown */
  1283. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1284. }
  1285. /*
  1286. * s3c2410_udc_reinit
  1287. */
  1288. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1289. {
  1290. u32 i;
  1291. /* device/ep0 records init */
  1292. INIT_LIST_HEAD (&dev->gadget.ep_list);
  1293. INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
  1294. dev->ep0state = EP0_IDLE;
  1295. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1296. struct s3c2410_ep *ep = &dev->ep[i];
  1297. if (i != 0)
  1298. list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
  1299. ep->dev = dev;
  1300. ep->desc = NULL;
  1301. ep->halted = 0;
  1302. INIT_LIST_HEAD (&ep->queue);
  1303. }
  1304. }
  1305. /*
  1306. * s3c2410_udc_enable
  1307. */
  1308. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1309. {
  1310. int i;
  1311. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1312. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1313. dev->gadget.speed = USB_SPEED_FULL;
  1314. /* Set MAXP for all endpoints */
  1315. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1316. udc_write(i, S3C2410_UDC_INDEX_REG);
  1317. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1318. S3C2410_UDC_MAXP_REG);
  1319. }
  1320. /* Set default power state */
  1321. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1322. /* Enable reset and suspend interrupt interrupts */
  1323. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1324. S3C2410_UDC_USB_INT_EN_REG);
  1325. /* Enable ep0 interrupt */
  1326. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1327. /* time to say "hello, world" */
  1328. if (udc_info && udc_info->udc_command)
  1329. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1330. }
  1331. /*
  1332. * usb_gadget_register_driver
  1333. */
  1334. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1335. {
  1336. struct s3c2410_udc *udc = the_controller;
  1337. int retval;
  1338. dprintk(DEBUG_NORMAL, "usb_gadget_register_driver() '%s'\n",
  1339. driver->driver.name);
  1340. /* Sanity checks */
  1341. if (!udc)
  1342. return -ENODEV;
  1343. if (udc->driver)
  1344. return -EBUSY;
  1345. if (!driver->bind || !driver->setup
  1346. || driver->speed != USB_SPEED_FULL) {
  1347. printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
  1348. driver->bind, driver->setup, driver->speed);
  1349. return -EINVAL;
  1350. }
  1351. #if defined(MODULE)
  1352. if (!driver->unbind) {
  1353. printk(KERN_ERR "Invalid driver: no unbind method\n");
  1354. return -EINVAL;
  1355. }
  1356. #endif
  1357. /* Hook the driver */
  1358. udc->driver = driver;
  1359. udc->gadget.dev.driver = &driver->driver;
  1360. /* Bind the driver */
  1361. if ((retval = device_add(&udc->gadget.dev)) != 0) {
  1362. printk(KERN_ERR "Error in device_add() : %d\n",retval);
  1363. goto register_error;
  1364. }
  1365. dprintk(DEBUG_NORMAL, "binding gadget driver '%s'\n",
  1366. driver->driver.name);
  1367. if ((retval = driver->bind (&udc->gadget)) != 0) {
  1368. device_del(&udc->gadget.dev);
  1369. goto register_error;
  1370. }
  1371. /* Enable udc */
  1372. s3c2410_udc_enable(udc);
  1373. return 0;
  1374. register_error:
  1375. udc->driver = NULL;
  1376. udc->gadget.dev.driver = NULL;
  1377. return retval;
  1378. }
  1379. /*
  1380. * usb_gadget_unregister_driver
  1381. */
  1382. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1383. {
  1384. struct s3c2410_udc *udc = the_controller;
  1385. if (!udc)
  1386. return -ENODEV;
  1387. if (!driver || driver != udc->driver || !driver->unbind)
  1388. return -EINVAL;
  1389. dprintk(DEBUG_NORMAL,"usb_gadget_register_driver() '%s'\n",
  1390. driver->driver.name);
  1391. if (driver->disconnect)
  1392. driver->disconnect(&udc->gadget);
  1393. device_del(&udc->gadget.dev);
  1394. udc->driver = NULL;
  1395. /* Disable udc */
  1396. s3c2410_udc_disable(udc);
  1397. return 0;
  1398. }
  1399. /*---------------------------------------------------------------------------*/
  1400. static struct s3c2410_udc memory = {
  1401. .gadget = {
  1402. .ops = &s3c2410_ops,
  1403. .ep0 = &memory.ep[0].ep,
  1404. .name = gadget_name,
  1405. .dev = {
  1406. .bus_id = "gadget",
  1407. },
  1408. },
  1409. /* control endpoint */
  1410. .ep[0] = {
  1411. .num = 0,
  1412. .ep = {
  1413. .name = ep0name,
  1414. .ops = &s3c2410_ep_ops,
  1415. .maxpacket = EP0_FIFO_SIZE,
  1416. },
  1417. .dev = &memory,
  1418. },
  1419. /* first group of endpoints */
  1420. .ep[1] = {
  1421. .num = 1,
  1422. .ep = {
  1423. .name = "ep1-bulk",
  1424. .ops = &s3c2410_ep_ops,
  1425. .maxpacket = EP_FIFO_SIZE,
  1426. },
  1427. .dev = &memory,
  1428. .fifo_size = EP_FIFO_SIZE,
  1429. .bEndpointAddress = 1,
  1430. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1431. },
  1432. .ep[2] = {
  1433. .num = 2,
  1434. .ep = {
  1435. .name = "ep2-bulk",
  1436. .ops = &s3c2410_ep_ops,
  1437. .maxpacket = EP_FIFO_SIZE,
  1438. },
  1439. .dev = &memory,
  1440. .fifo_size = EP_FIFO_SIZE,
  1441. .bEndpointAddress = 2,
  1442. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1443. },
  1444. .ep[3] = {
  1445. .num = 3,
  1446. .ep = {
  1447. .name = "ep3-bulk",
  1448. .ops = &s3c2410_ep_ops,
  1449. .maxpacket = EP_FIFO_SIZE,
  1450. },
  1451. .dev = &memory,
  1452. .fifo_size = EP_FIFO_SIZE,
  1453. .bEndpointAddress = 3,
  1454. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1455. },
  1456. .ep[4] = {
  1457. .num = 4,
  1458. .ep = {
  1459. .name = "ep4-bulk",
  1460. .ops = &s3c2410_ep_ops,
  1461. .maxpacket = EP_FIFO_SIZE,
  1462. },
  1463. .dev = &memory,
  1464. .fifo_size = EP_FIFO_SIZE,
  1465. .bEndpointAddress = 4,
  1466. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1467. }
  1468. };
  1469. /*
  1470. * probe - binds to the platform device
  1471. */
  1472. static int s3c2410_udc_probe(struct platform_device *pdev)
  1473. {
  1474. struct s3c2410_udc *udc = &memory;
  1475. struct device *dev = &pdev->dev;
  1476. int retval;
  1477. unsigned int irq;
  1478. dev_dbg(dev, "%s()\n", __func__);
  1479. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1480. if (IS_ERR(usb_bus_clock)) {
  1481. dev_err(dev, "failed to get usb bus clock source\n");
  1482. return PTR_ERR(usb_bus_clock);
  1483. }
  1484. clk_enable(usb_bus_clock);
  1485. udc_clock = clk_get(NULL, "usb-device");
  1486. if (IS_ERR(udc_clock)) {
  1487. dev_err(dev, "failed to get udc clock source\n");
  1488. return PTR_ERR(udc_clock);
  1489. }
  1490. clk_enable(udc_clock);
  1491. mdelay(10);
  1492. dev_dbg(dev, "got and enabled clocks\n");
  1493. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1494. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1495. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1496. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1497. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1498. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1499. }
  1500. spin_lock_init (&udc->lock);
  1501. udc_info = pdev->dev.platform_data;
  1502. rsrc_start = S3C2410_PA_USBDEV;
  1503. rsrc_len = S3C24XX_SZ_USBDEV;
  1504. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1505. return -EBUSY;
  1506. base_addr = ioremap(rsrc_start, rsrc_len);
  1507. if (!base_addr) {
  1508. retval = -ENOMEM;
  1509. goto err_mem;
  1510. }
  1511. device_initialize(&udc->gadget.dev);
  1512. udc->gadget.dev.parent = &pdev->dev;
  1513. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1514. the_controller = udc;
  1515. platform_set_drvdata(pdev, udc);
  1516. s3c2410_udc_disable(udc);
  1517. s3c2410_udc_reinit(udc);
  1518. /* irq setup after old hardware state is cleaned up */
  1519. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1520. IRQF_DISABLED, gadget_name, udc);
  1521. if (retval != 0) {
  1522. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1523. retval = -EBUSY;
  1524. goto err_map;
  1525. }
  1526. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1527. if (udc_info && udc_info->vbus_pin > 0) {
  1528. irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
  1529. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1530. IRQF_DISABLED | IRQF_TRIGGER_RISING
  1531. | IRQF_TRIGGER_FALLING,
  1532. gadget_name, udc);
  1533. if (retval != 0) {
  1534. dev_err(dev, "can't get vbus irq %i, err %d\n",
  1535. irq, retval);
  1536. retval = -EBUSY;
  1537. goto err_int;
  1538. }
  1539. dev_dbg(dev, "got irq %i\n", irq);
  1540. } else {
  1541. udc->vbus = 1;
  1542. }
  1543. if (s3c2410_udc_debugfs_root) {
  1544. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1545. s3c2410_udc_debugfs_root,
  1546. udc, &s3c2410_udc_debugfs_fops);
  1547. if (IS_ERR(udc->regs_info)) {
  1548. dev_warn(dev, "debugfs file creation failed %ld\n",
  1549. PTR_ERR(udc->regs_info));
  1550. udc->regs_info = NULL;
  1551. }
  1552. }
  1553. dev_dbg(dev, "probe ok\n");
  1554. return 0;
  1555. err_int:
  1556. free_irq(IRQ_USBD, udc);
  1557. err_map:
  1558. iounmap(base_addr);
  1559. err_mem:
  1560. release_mem_region(rsrc_start, rsrc_len);
  1561. return retval;
  1562. }
  1563. /*
  1564. * s3c2410_udc_remove
  1565. */
  1566. static int s3c2410_udc_remove(struct platform_device *pdev)
  1567. {
  1568. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1569. unsigned int irq;
  1570. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1571. if (udc->driver)
  1572. return -EBUSY;
  1573. debugfs_remove(udc->regs_info);
  1574. if (udc_info && udc_info->vbus_pin > 0) {
  1575. irq = s3c2410_gpio_getirq(udc_info->vbus_pin);
  1576. free_irq(irq, udc);
  1577. }
  1578. free_irq(IRQ_USBD, udc);
  1579. iounmap(base_addr);
  1580. release_mem_region(rsrc_start, rsrc_len);
  1581. platform_set_drvdata(pdev, NULL);
  1582. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1583. clk_disable(udc_clock);
  1584. clk_put(udc_clock);
  1585. udc_clock = NULL;
  1586. }
  1587. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1588. clk_disable(usb_bus_clock);
  1589. clk_put(usb_bus_clock);
  1590. usb_bus_clock = NULL;
  1591. }
  1592. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1593. return 0;
  1594. }
  1595. #ifdef CONFIG_PM
  1596. static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1597. {
  1598. if (udc_info && udc_info->udc_command)
  1599. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1600. return 0;
  1601. }
  1602. static int s3c2410_udc_resume(struct platform_device *pdev)
  1603. {
  1604. if (udc_info && udc_info->udc_command)
  1605. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1606. return 0;
  1607. }
  1608. #else
  1609. #define s3c2410_udc_suspend NULL
  1610. #define s3c2410_udc_resume NULL
  1611. #endif
  1612. static struct platform_driver udc_driver_2410 = {
  1613. .driver = {
  1614. .name = "s3c2410-usbgadget",
  1615. .owner = THIS_MODULE,
  1616. },
  1617. .probe = s3c2410_udc_probe,
  1618. .remove = s3c2410_udc_remove,
  1619. .suspend = s3c2410_udc_suspend,
  1620. .resume = s3c2410_udc_resume,
  1621. };
  1622. static struct platform_driver udc_driver_2440 = {
  1623. .driver = {
  1624. .name = "s3c2440-usbgadget",
  1625. .owner = THIS_MODULE,
  1626. },
  1627. .probe = s3c2410_udc_probe,
  1628. .remove = s3c2410_udc_remove,
  1629. .suspend = s3c2410_udc_suspend,
  1630. .resume = s3c2410_udc_resume,
  1631. };
  1632. static int __init udc_init(void)
  1633. {
  1634. int retval;
  1635. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1636. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1637. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1638. printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
  1639. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1640. s3c2410_udc_debugfs_root = NULL;
  1641. }
  1642. retval = platform_driver_register(&udc_driver_2410);
  1643. if (retval)
  1644. goto err;
  1645. retval = platform_driver_register(&udc_driver_2440);
  1646. if (retval)
  1647. goto err;
  1648. return 0;
  1649. err:
  1650. debugfs_remove(s3c2410_udc_debugfs_root);
  1651. return retval;
  1652. }
  1653. static void __exit udc_exit(void)
  1654. {
  1655. platform_driver_unregister(&udc_driver_2410);
  1656. platform_driver_unregister(&udc_driver_2440);
  1657. debugfs_remove(s3c2410_udc_debugfs_root);
  1658. }
  1659. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1660. EXPORT_SYMBOL(usb_gadget_register_driver);
  1661. module_init(udc_init);
  1662. module_exit(udc_exit);
  1663. MODULE_AUTHOR(DRIVER_AUTHOR);
  1664. MODULE_DESCRIPTION(DRIVER_DESC);
  1665. MODULE_VERSION(DRIVER_VERSION);
  1666. MODULE_LICENSE("GPL");