m66592-udc.c 40 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/usb/ch9.h>
  28. #include <linux/usb/gadget.h>
  29. #include "m66592-udc.h"
  30. MODULE_DESCRIPTION("M66592 USB gadget driver");
  31. MODULE_LICENSE("GPL");
  32. MODULE_AUTHOR("Yoshihiro Shimoda");
  33. #define DRIVER_VERSION "29 May 2007"
  34. /* module parameters */
  35. static unsigned short clock = M66592_XTAL24;
  36. module_param(clock, ushort, 0644);
  37. MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
  38. "(default=16384)");
  39. static unsigned short vif = M66592_LDRV;
  40. module_param(vif, ushort, 0644);
  41. MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
  42. static unsigned short endian;
  43. module_param(endian, ushort, 0644);
  44. MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
  45. static unsigned short irq_sense = M66592_INTL;
  46. module_param(irq_sense, ushort, 0644);
  47. MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
  48. "(default=2)");
  49. static const char udc_name[] = "m66592_udc";
  50. static const char *m66592_ep_name[] = {
  51. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  52. };
  53. static void disable_controller(struct m66592 *m66592);
  54. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  55. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  56. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  57. gfp_t gfp_flags);
  58. static void transfer_complete(struct m66592_ep *ep,
  59. struct m66592_request *req, int status);
  60. /*-------------------------------------------------------------------------*/
  61. static inline u16 get_usb_speed(struct m66592 *m66592)
  62. {
  63. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  64. }
  65. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  66. unsigned long reg)
  67. {
  68. u16 tmp;
  69. tmp = m66592_read(m66592, M66592_INTENB0);
  70. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  71. M66592_INTENB0);
  72. m66592_bset(m66592, (1 << pipenum), reg);
  73. m66592_write(m66592, tmp, M66592_INTENB0);
  74. }
  75. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  76. unsigned long reg)
  77. {
  78. u16 tmp;
  79. tmp = m66592_read(m66592, M66592_INTENB0);
  80. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  81. M66592_INTENB0);
  82. m66592_bclr(m66592, (1 << pipenum), reg);
  83. m66592_write(m66592, tmp, M66592_INTENB0);
  84. }
  85. static void m66592_usb_connect(struct m66592 *m66592)
  86. {
  87. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  88. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  89. M66592_INTENB0);
  90. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  91. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  92. }
  93. static void m66592_usb_disconnect(struct m66592 *m66592)
  94. __releases(m66592->lock)
  95. __acquires(m66592->lock)
  96. {
  97. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  98. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  99. M66592_INTENB0);
  100. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  101. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  102. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  103. spin_unlock(&m66592->lock);
  104. m66592->driver->disconnect(&m66592->gadget);
  105. spin_lock(&m66592->lock);
  106. disable_controller(m66592);
  107. INIT_LIST_HEAD(&m66592->ep[0].queue);
  108. }
  109. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  110. {
  111. u16 pid = 0;
  112. unsigned long offset;
  113. if (pipenum == 0)
  114. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  115. else if (pipenum < M66592_MAX_NUM_PIPE) {
  116. offset = get_pipectr_addr(pipenum);
  117. pid = m66592_read(m66592, offset) & M66592_PID;
  118. } else
  119. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  120. return pid;
  121. }
  122. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  123. u16 pid)
  124. {
  125. unsigned long offset;
  126. if (pipenum == 0)
  127. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  128. else if (pipenum < M66592_MAX_NUM_PIPE) {
  129. offset = get_pipectr_addr(pipenum);
  130. m66592_mdfy(m66592, pid, M66592_PID, offset);
  131. } else
  132. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  133. }
  134. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  135. {
  136. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  137. }
  138. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  139. {
  140. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  141. }
  142. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  143. {
  144. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  145. }
  146. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  147. {
  148. u16 ret = 0;
  149. unsigned long offset;
  150. if (pipenum == 0)
  151. ret = m66592_read(m66592, M66592_DCPCTR);
  152. else if (pipenum < M66592_MAX_NUM_PIPE) {
  153. offset = get_pipectr_addr(pipenum);
  154. ret = m66592_read(m66592, offset);
  155. } else
  156. printk(KERN_ERR "unexpect pipe num (%d)\n", pipenum);
  157. return ret;
  158. }
  159. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  160. {
  161. unsigned long offset;
  162. pipe_stop(m66592, pipenum);
  163. if (pipenum == 0)
  164. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  165. else if (pipenum < M66592_MAX_NUM_PIPE) {
  166. offset = get_pipectr_addr(pipenum);
  167. m66592_bset(m66592, M66592_SQCLR, offset);
  168. } else
  169. printk(KERN_ERR "unexpect pipe num(%d)\n", pipenum);
  170. }
  171. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  172. {
  173. u16 tmp;
  174. int size;
  175. if (pipenum == 0) {
  176. tmp = m66592_read(m66592, M66592_DCPCFG);
  177. if ((tmp & M66592_CNTMD) != 0)
  178. size = 256;
  179. else {
  180. tmp = m66592_read(m66592, M66592_DCPMAXP);
  181. size = tmp & M66592_MAXP;
  182. }
  183. } else {
  184. m66592_write(m66592, pipenum, M66592_PIPESEL);
  185. tmp = m66592_read(m66592, M66592_PIPECFG);
  186. if ((tmp & M66592_CNTMD) != 0) {
  187. tmp = m66592_read(m66592, M66592_PIPEBUF);
  188. size = ((tmp >> 10) + 1) * 64;
  189. } else {
  190. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  191. size = tmp & M66592_MXPS;
  192. }
  193. }
  194. return size;
  195. }
  196. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  197. {
  198. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  199. if (ep->use_dma)
  200. return;
  201. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  202. ndelay(450);
  203. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  204. }
  205. static int pipe_buffer_setting(struct m66592 *m66592,
  206. struct m66592_pipe_info *info)
  207. {
  208. u16 bufnum = 0, buf_bsize = 0;
  209. u16 pipecfg = 0;
  210. if (info->pipe == 0)
  211. return -EINVAL;
  212. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  213. if (info->dir_in)
  214. pipecfg |= M66592_DIR;
  215. pipecfg |= info->type;
  216. pipecfg |= info->epnum;
  217. switch (info->type) {
  218. case M66592_INT:
  219. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  220. buf_bsize = 0;
  221. break;
  222. case M66592_BULK:
  223. bufnum = m66592->bi_bufnum +
  224. (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
  225. m66592->bi_bufnum += 16;
  226. buf_bsize = 7;
  227. pipecfg |= M66592_DBLB;
  228. if (!info->dir_in)
  229. pipecfg |= M66592_SHTNAK;
  230. break;
  231. case M66592_ISO:
  232. bufnum = m66592->bi_bufnum +
  233. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  234. m66592->bi_bufnum += 16;
  235. buf_bsize = 7;
  236. break;
  237. }
  238. if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
  239. printk(KERN_ERR "m66592 pipe memory is insufficient(%d)\n",
  240. m66592->bi_bufnum);
  241. return -ENOMEM;
  242. }
  243. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  244. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  245. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  246. if (info->interval)
  247. info->interval--;
  248. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  249. return 0;
  250. }
  251. static void pipe_buffer_release(struct m66592 *m66592,
  252. struct m66592_pipe_info *info)
  253. {
  254. if (info->pipe == 0)
  255. return;
  256. switch (info->type) {
  257. case M66592_BULK:
  258. if (is_bulk_pipe(info->pipe))
  259. m66592->bi_bufnum -= 16;
  260. break;
  261. case M66592_ISO:
  262. if (is_isoc_pipe(info->pipe))
  263. m66592->bi_bufnum -= 16;
  264. break;
  265. }
  266. if (is_bulk_pipe(info->pipe)) {
  267. m66592->bulk--;
  268. } else if (is_interrupt_pipe(info->pipe))
  269. m66592->interrupt--;
  270. else if (is_isoc_pipe(info->pipe)) {
  271. m66592->isochronous--;
  272. if (info->type == M66592_BULK)
  273. m66592->bulk--;
  274. } else
  275. printk(KERN_ERR "ep_release: unexpect pipenum (%d)\n",
  276. info->pipe);
  277. }
  278. static void pipe_initialize(struct m66592_ep *ep)
  279. {
  280. struct m66592 *m66592 = ep->m66592;
  281. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  282. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  283. m66592_write(m66592, 0, ep->pipectr);
  284. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  285. if (ep->use_dma) {
  286. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  287. ndelay(450);
  288. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  289. }
  290. }
  291. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  292. const struct usb_endpoint_descriptor *desc,
  293. u16 pipenum, int dma)
  294. {
  295. if ((pipenum != 0) && dma) {
  296. if (m66592->num_dma == 0) {
  297. m66592->num_dma++;
  298. ep->use_dma = 1;
  299. ep->fifoaddr = M66592_D0FIFO;
  300. ep->fifosel = M66592_D0FIFOSEL;
  301. ep->fifoctr = M66592_D0FIFOCTR;
  302. ep->fifotrn = M66592_D0FIFOTRN;
  303. } else if (m66592->num_dma == 1) {
  304. m66592->num_dma++;
  305. ep->use_dma = 1;
  306. ep->fifoaddr = M66592_D1FIFO;
  307. ep->fifosel = M66592_D1FIFOSEL;
  308. ep->fifoctr = M66592_D1FIFOCTR;
  309. ep->fifotrn = M66592_D1FIFOTRN;
  310. } else {
  311. ep->use_dma = 0;
  312. ep->fifoaddr = M66592_CFIFO;
  313. ep->fifosel = M66592_CFIFOSEL;
  314. ep->fifoctr = M66592_CFIFOCTR;
  315. ep->fifotrn = 0;
  316. }
  317. } else {
  318. ep->use_dma = 0;
  319. ep->fifoaddr = M66592_CFIFO;
  320. ep->fifosel = M66592_CFIFOSEL;
  321. ep->fifoctr = M66592_CFIFOCTR;
  322. ep->fifotrn = 0;
  323. }
  324. ep->pipectr = get_pipectr_addr(pipenum);
  325. ep->pipenum = pipenum;
  326. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  327. m66592->pipenum2ep[pipenum] = ep;
  328. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  329. INIT_LIST_HEAD(&ep->queue);
  330. }
  331. static void m66592_ep_release(struct m66592_ep *ep)
  332. {
  333. struct m66592 *m66592 = ep->m66592;
  334. u16 pipenum = ep->pipenum;
  335. if (pipenum == 0)
  336. return;
  337. if (ep->use_dma)
  338. m66592->num_dma--;
  339. ep->pipenum = 0;
  340. ep->busy = 0;
  341. ep->use_dma = 0;
  342. }
  343. static int alloc_pipe_config(struct m66592_ep *ep,
  344. const struct usb_endpoint_descriptor *desc)
  345. {
  346. struct m66592 *m66592 = ep->m66592;
  347. struct m66592_pipe_info info;
  348. int dma = 0;
  349. int *counter;
  350. int ret;
  351. ep->desc = desc;
  352. BUG_ON(ep->pipenum);
  353. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  354. case USB_ENDPOINT_XFER_BULK:
  355. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  356. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  357. printk(KERN_ERR "bulk pipe is insufficient\n");
  358. return -ENODEV;
  359. } else {
  360. info.pipe = M66592_BASE_PIPENUM_ISOC
  361. + m66592->isochronous;
  362. counter = &m66592->isochronous;
  363. }
  364. } else {
  365. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  366. counter = &m66592->bulk;
  367. }
  368. info.type = M66592_BULK;
  369. dma = 1;
  370. break;
  371. case USB_ENDPOINT_XFER_INT:
  372. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  373. printk(KERN_ERR "interrupt pipe is insufficient\n");
  374. return -ENODEV;
  375. }
  376. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  377. info.type = M66592_INT;
  378. counter = &m66592->interrupt;
  379. break;
  380. case USB_ENDPOINT_XFER_ISOC:
  381. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  382. printk(KERN_ERR "isochronous pipe is insufficient\n");
  383. return -ENODEV;
  384. }
  385. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  386. info.type = M66592_ISO;
  387. counter = &m66592->isochronous;
  388. break;
  389. default:
  390. printk(KERN_ERR "unexpect xfer type\n");
  391. return -EINVAL;
  392. }
  393. ep->type = info.type;
  394. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  395. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  396. info.interval = desc->bInterval;
  397. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  398. info.dir_in = 1;
  399. else
  400. info.dir_in = 0;
  401. ret = pipe_buffer_setting(m66592, &info);
  402. if (ret < 0) {
  403. printk(KERN_ERR "pipe_buffer_setting fail\n");
  404. return ret;
  405. }
  406. (*counter)++;
  407. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  408. m66592->bulk++;
  409. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  410. pipe_initialize(ep);
  411. return 0;
  412. }
  413. static int free_pipe_config(struct m66592_ep *ep)
  414. {
  415. struct m66592 *m66592 = ep->m66592;
  416. struct m66592_pipe_info info;
  417. info.pipe = ep->pipenum;
  418. info.type = ep->type;
  419. pipe_buffer_release(m66592, &info);
  420. m66592_ep_release(ep);
  421. return 0;
  422. }
  423. /*-------------------------------------------------------------------------*/
  424. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  425. {
  426. enable_irq_ready(m66592, pipenum);
  427. enable_irq_nrdy(m66592, pipenum);
  428. }
  429. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  430. {
  431. disable_irq_ready(m66592, pipenum);
  432. disable_irq_nrdy(m66592, pipenum);
  433. }
  434. /* if complete is true, gadget driver complete function is not call */
  435. static void control_end(struct m66592 *m66592, unsigned ccpl)
  436. {
  437. m66592->ep[0].internal_ccpl = ccpl;
  438. pipe_start(m66592, 0);
  439. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  440. }
  441. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  442. {
  443. struct m66592 *m66592 = ep->m66592;
  444. pipe_change(m66592, ep->pipenum);
  445. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  446. (M66592_ISEL | M66592_CURPIPE),
  447. M66592_CFIFOSEL);
  448. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  449. if (req->req.length == 0) {
  450. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  451. pipe_start(m66592, 0);
  452. transfer_complete(ep, req, 0);
  453. } else {
  454. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  455. irq_ep0_write(ep, req);
  456. }
  457. }
  458. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  459. {
  460. struct m66592 *m66592 = ep->m66592;
  461. u16 tmp;
  462. pipe_change(m66592, ep->pipenum);
  463. disable_irq_empty(m66592, ep->pipenum);
  464. pipe_start(m66592, ep->pipenum);
  465. tmp = m66592_read(m66592, ep->fifoctr);
  466. if (unlikely((tmp & M66592_FRDY) == 0))
  467. pipe_irq_enable(m66592, ep->pipenum);
  468. else
  469. irq_packet_write(ep, req);
  470. }
  471. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  472. {
  473. struct m66592 *m66592 = ep->m66592;
  474. u16 pipenum = ep->pipenum;
  475. if (ep->pipenum == 0) {
  476. m66592_mdfy(m66592, M66592_PIPE0,
  477. (M66592_ISEL | M66592_CURPIPE),
  478. M66592_CFIFOSEL);
  479. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  480. pipe_start(m66592, pipenum);
  481. pipe_irq_enable(m66592, pipenum);
  482. } else {
  483. if (ep->use_dma) {
  484. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  485. pipe_change(m66592, pipenum);
  486. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  487. m66592_write(m66592,
  488. (req->req.length + ep->ep.maxpacket - 1)
  489. / ep->ep.maxpacket,
  490. ep->fifotrn);
  491. }
  492. pipe_start(m66592, pipenum); /* trigger once */
  493. pipe_irq_enable(m66592, pipenum);
  494. }
  495. }
  496. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  497. {
  498. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  499. start_packet_write(ep, req);
  500. else
  501. start_packet_read(ep, req);
  502. }
  503. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  504. {
  505. u16 ctsq;
  506. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  507. switch (ctsq) {
  508. case M66592_CS_RDDS:
  509. start_ep0_write(ep, req);
  510. break;
  511. case M66592_CS_WRDS:
  512. start_packet_read(ep, req);
  513. break;
  514. case M66592_CS_WRND:
  515. control_end(ep->m66592, 0);
  516. break;
  517. default:
  518. printk(KERN_ERR "start_ep0: unexpect ctsq(%x)\n", ctsq);
  519. break;
  520. }
  521. }
  522. static void init_controller(struct m66592 *m66592)
  523. {
  524. m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  525. M66592_PINCFG);
  526. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  527. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
  528. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  529. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  530. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  531. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  532. msleep(3);
  533. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  534. msleep(1);
  535. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  536. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  537. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  538. M66592_DMA0CFG);
  539. }
  540. static void disable_controller(struct m66592 *m66592)
  541. {
  542. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  543. udelay(1);
  544. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  545. udelay(1);
  546. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  547. udelay(1);
  548. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  549. }
  550. static void m66592_start_xclock(struct m66592 *m66592)
  551. {
  552. u16 tmp;
  553. tmp = m66592_read(m66592, M66592_SYSCFG);
  554. if (!(tmp & M66592_XCKE))
  555. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  556. }
  557. /*-------------------------------------------------------------------------*/
  558. static void transfer_complete(struct m66592_ep *ep,
  559. struct m66592_request *req, int status)
  560. __releases(m66592->lock)
  561. __acquires(m66592->lock)
  562. {
  563. int restart = 0;
  564. if (unlikely(ep->pipenum == 0)) {
  565. if (ep->internal_ccpl) {
  566. ep->internal_ccpl = 0;
  567. return;
  568. }
  569. }
  570. list_del_init(&req->queue);
  571. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  572. req->req.status = -ESHUTDOWN;
  573. else
  574. req->req.status = status;
  575. if (!list_empty(&ep->queue))
  576. restart = 1;
  577. spin_unlock(&ep->m66592->lock);
  578. req->req.complete(&ep->ep, &req->req);
  579. spin_lock(&ep->m66592->lock);
  580. if (restart) {
  581. req = list_entry(ep->queue.next, struct m66592_request, queue);
  582. if (ep->desc)
  583. start_packet(ep, req);
  584. }
  585. }
  586. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  587. {
  588. int i;
  589. u16 tmp;
  590. unsigned bufsize;
  591. size_t size;
  592. void *buf;
  593. u16 pipenum = ep->pipenum;
  594. struct m66592 *m66592 = ep->m66592;
  595. pipe_change(m66592, pipenum);
  596. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  597. i = 0;
  598. do {
  599. tmp = m66592_read(m66592, ep->fifoctr);
  600. if (i++ > 100000) {
  601. printk(KERN_ERR "pipe0 is busy. maybe cpu i/o bus"
  602. "conflict. please power off this controller.");
  603. return;
  604. }
  605. ndelay(1);
  606. } while ((tmp & M66592_FRDY) == 0);
  607. /* prepare parameters */
  608. bufsize = get_buffer_size(m66592, pipenum);
  609. buf = req->req.buf + req->req.actual;
  610. size = min(bufsize, req->req.length - req->req.actual);
  611. /* write fifo */
  612. if (req->req.buf) {
  613. if (size > 0)
  614. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  615. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  616. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  617. }
  618. /* update parameters */
  619. req->req.actual += size;
  620. /* check transfer finish */
  621. if ((!req->req.zero && (req->req.actual == req->req.length))
  622. || (size % ep->ep.maxpacket)
  623. || (size == 0)) {
  624. disable_irq_ready(m66592, pipenum);
  625. disable_irq_empty(m66592, pipenum);
  626. } else {
  627. disable_irq_ready(m66592, pipenum);
  628. enable_irq_empty(m66592, pipenum);
  629. }
  630. pipe_start(m66592, pipenum);
  631. }
  632. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  633. {
  634. u16 tmp;
  635. unsigned bufsize;
  636. size_t size;
  637. void *buf;
  638. u16 pipenum = ep->pipenum;
  639. struct m66592 *m66592 = ep->m66592;
  640. pipe_change(m66592, pipenum);
  641. tmp = m66592_read(m66592, ep->fifoctr);
  642. if (unlikely((tmp & M66592_FRDY) == 0)) {
  643. pipe_stop(m66592, pipenum);
  644. pipe_irq_disable(m66592, pipenum);
  645. printk(KERN_ERR "write fifo not ready. pipnum=%d\n", pipenum);
  646. return;
  647. }
  648. /* prepare parameters */
  649. bufsize = get_buffer_size(m66592, pipenum);
  650. buf = req->req.buf + req->req.actual;
  651. size = min(bufsize, req->req.length - req->req.actual);
  652. /* write fifo */
  653. if (req->req.buf) {
  654. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  655. if ((size == 0)
  656. || ((size % ep->ep.maxpacket) != 0)
  657. || ((bufsize != ep->ep.maxpacket)
  658. && (bufsize > size)))
  659. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  660. }
  661. /* update parameters */
  662. req->req.actual += size;
  663. /* check transfer finish */
  664. if ((!req->req.zero && (req->req.actual == req->req.length))
  665. || (size % ep->ep.maxpacket)
  666. || (size == 0)) {
  667. disable_irq_ready(m66592, pipenum);
  668. enable_irq_empty(m66592, pipenum);
  669. } else {
  670. disable_irq_empty(m66592, pipenum);
  671. pipe_irq_enable(m66592, pipenum);
  672. }
  673. }
  674. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  675. {
  676. u16 tmp;
  677. int rcv_len, bufsize, req_len;
  678. int size;
  679. void *buf;
  680. u16 pipenum = ep->pipenum;
  681. struct m66592 *m66592 = ep->m66592;
  682. int finish = 0;
  683. pipe_change(m66592, pipenum);
  684. tmp = m66592_read(m66592, ep->fifoctr);
  685. if (unlikely((tmp & M66592_FRDY) == 0)) {
  686. req->req.status = -EPIPE;
  687. pipe_stop(m66592, pipenum);
  688. pipe_irq_disable(m66592, pipenum);
  689. printk(KERN_ERR "read fifo not ready");
  690. return;
  691. }
  692. /* prepare parameters */
  693. rcv_len = tmp & M66592_DTLN;
  694. bufsize = get_buffer_size(m66592, pipenum);
  695. buf = req->req.buf + req->req.actual;
  696. req_len = req->req.length - req->req.actual;
  697. if (rcv_len < bufsize)
  698. size = min(rcv_len, req_len);
  699. else
  700. size = min(bufsize, req_len);
  701. /* update parameters */
  702. req->req.actual += size;
  703. /* check transfer finish */
  704. if ((!req->req.zero && (req->req.actual == req->req.length))
  705. || (size % ep->ep.maxpacket)
  706. || (size == 0)) {
  707. pipe_stop(m66592, pipenum);
  708. pipe_irq_disable(m66592, pipenum);
  709. finish = 1;
  710. }
  711. /* read fifo */
  712. if (req->req.buf) {
  713. if (size == 0)
  714. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  715. else
  716. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  717. }
  718. if ((ep->pipenum != 0) && finish)
  719. transfer_complete(ep, req, 0);
  720. }
  721. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  722. {
  723. u16 check;
  724. u16 pipenum;
  725. struct m66592_ep *ep;
  726. struct m66592_request *req;
  727. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  728. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  729. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  730. M66592_CFIFOSEL);
  731. ep = &m66592->ep[0];
  732. req = list_entry(ep->queue.next, struct m66592_request, queue);
  733. irq_packet_read(ep, req);
  734. } else {
  735. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  736. check = 1 << pipenum;
  737. if ((status & check) && (enb & check)) {
  738. m66592_write(m66592, ~check, M66592_BRDYSTS);
  739. ep = m66592->pipenum2ep[pipenum];
  740. req = list_entry(ep->queue.next,
  741. struct m66592_request, queue);
  742. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  743. irq_packet_write(ep, req);
  744. else
  745. irq_packet_read(ep, req);
  746. }
  747. }
  748. }
  749. }
  750. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  751. {
  752. u16 tmp;
  753. u16 check;
  754. u16 pipenum;
  755. struct m66592_ep *ep;
  756. struct m66592_request *req;
  757. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  758. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  759. ep = &m66592->ep[0];
  760. req = list_entry(ep->queue.next, struct m66592_request, queue);
  761. irq_ep0_write(ep, req);
  762. } else {
  763. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  764. check = 1 << pipenum;
  765. if ((status & check) && (enb & check)) {
  766. m66592_write(m66592, ~check, M66592_BEMPSTS);
  767. tmp = control_reg_get(m66592, pipenum);
  768. if ((tmp & M66592_INBUFM) == 0) {
  769. disable_irq_empty(m66592, pipenum);
  770. pipe_irq_disable(m66592, pipenum);
  771. pipe_stop(m66592, pipenum);
  772. ep = m66592->pipenum2ep[pipenum];
  773. req = list_entry(ep->queue.next,
  774. struct m66592_request,
  775. queue);
  776. if (!list_empty(&ep->queue))
  777. transfer_complete(ep, req, 0);
  778. }
  779. }
  780. }
  781. }
  782. }
  783. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  784. __releases(m66592->lock)
  785. __acquires(m66592->lock)
  786. {
  787. struct m66592_ep *ep;
  788. u16 pid;
  789. u16 status = 0;
  790. u16 w_index = le16_to_cpu(ctrl->wIndex);
  791. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  792. case USB_RECIP_DEVICE:
  793. status = 1 << USB_DEVICE_SELF_POWERED;
  794. break;
  795. case USB_RECIP_INTERFACE:
  796. status = 0;
  797. break;
  798. case USB_RECIP_ENDPOINT:
  799. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  800. pid = control_reg_get_pid(m66592, ep->pipenum);
  801. if (pid == M66592_PID_STALL)
  802. status = 1 << USB_ENDPOINT_HALT;
  803. else
  804. status = 0;
  805. break;
  806. default:
  807. pipe_stall(m66592, 0);
  808. return; /* exit */
  809. }
  810. m66592->ep0_data = cpu_to_le16(status);
  811. m66592->ep0_req->buf = &m66592->ep0_data;
  812. m66592->ep0_req->length = 2;
  813. /* AV: what happens if we get called again before that gets through? */
  814. spin_unlock(&m66592->lock);
  815. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  816. spin_lock(&m66592->lock);
  817. }
  818. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  819. {
  820. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  821. case USB_RECIP_DEVICE:
  822. control_end(m66592, 1);
  823. break;
  824. case USB_RECIP_INTERFACE:
  825. control_end(m66592, 1);
  826. break;
  827. case USB_RECIP_ENDPOINT: {
  828. struct m66592_ep *ep;
  829. struct m66592_request *req;
  830. u16 w_index = le16_to_cpu(ctrl->wIndex);
  831. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  832. pipe_stop(m66592, ep->pipenum);
  833. control_reg_sqclr(m66592, ep->pipenum);
  834. control_end(m66592, 1);
  835. req = list_entry(ep->queue.next,
  836. struct m66592_request, queue);
  837. if (ep->busy) {
  838. ep->busy = 0;
  839. if (list_empty(&ep->queue))
  840. break;
  841. start_packet(ep, req);
  842. } else if (!list_empty(&ep->queue))
  843. pipe_start(m66592, ep->pipenum);
  844. }
  845. break;
  846. default:
  847. pipe_stall(m66592, 0);
  848. break;
  849. }
  850. }
  851. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  852. {
  853. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  854. case USB_RECIP_DEVICE:
  855. control_end(m66592, 1);
  856. break;
  857. case USB_RECIP_INTERFACE:
  858. control_end(m66592, 1);
  859. break;
  860. case USB_RECIP_ENDPOINT: {
  861. struct m66592_ep *ep;
  862. u16 w_index = le16_to_cpu(ctrl->wIndex);
  863. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  864. pipe_stall(m66592, ep->pipenum);
  865. control_end(m66592, 1);
  866. }
  867. break;
  868. default:
  869. pipe_stall(m66592, 0);
  870. break;
  871. }
  872. }
  873. /* if return value is true, call class driver's setup() */
  874. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  875. {
  876. u16 *p = (u16 *)ctrl;
  877. unsigned long offset = M66592_USBREQ;
  878. int i, ret = 0;
  879. /* read fifo */
  880. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  881. for (i = 0; i < 4; i++)
  882. p[i] = m66592_read(m66592, offset + i*2);
  883. /* check request */
  884. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  885. switch (ctrl->bRequest) {
  886. case USB_REQ_GET_STATUS:
  887. get_status(m66592, ctrl);
  888. break;
  889. case USB_REQ_CLEAR_FEATURE:
  890. clear_feature(m66592, ctrl);
  891. break;
  892. case USB_REQ_SET_FEATURE:
  893. set_feature(m66592, ctrl);
  894. break;
  895. default:
  896. ret = 1;
  897. break;
  898. }
  899. } else
  900. ret = 1;
  901. return ret;
  902. }
  903. static void m66592_update_usb_speed(struct m66592 *m66592)
  904. {
  905. u16 speed = get_usb_speed(m66592);
  906. switch (speed) {
  907. case M66592_HSMODE:
  908. m66592->gadget.speed = USB_SPEED_HIGH;
  909. break;
  910. case M66592_FSMODE:
  911. m66592->gadget.speed = USB_SPEED_FULL;
  912. break;
  913. default:
  914. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  915. printk(KERN_ERR "USB speed unknown\n");
  916. }
  917. }
  918. static void irq_device_state(struct m66592 *m66592)
  919. {
  920. u16 dvsq;
  921. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  922. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  923. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  924. m66592->driver->disconnect(&m66592->gadget);
  925. m66592_update_usb_speed(m66592);
  926. }
  927. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  928. m66592_update_usb_speed(m66592);
  929. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  930. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  931. m66592_update_usb_speed(m66592);
  932. m66592->old_dvsq = dvsq;
  933. }
  934. static void irq_control_stage(struct m66592 *m66592)
  935. __releases(m66592->lock)
  936. __acquires(m66592->lock)
  937. {
  938. struct usb_ctrlrequest ctrl;
  939. u16 ctsq;
  940. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  941. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  942. switch (ctsq) {
  943. case M66592_CS_IDST: {
  944. struct m66592_ep *ep;
  945. struct m66592_request *req;
  946. ep = &m66592->ep[0];
  947. req = list_entry(ep->queue.next, struct m66592_request, queue);
  948. transfer_complete(ep, req, 0);
  949. }
  950. break;
  951. case M66592_CS_RDDS:
  952. case M66592_CS_WRDS:
  953. case M66592_CS_WRND:
  954. if (setup_packet(m66592, &ctrl)) {
  955. spin_unlock(&m66592->lock);
  956. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  957. pipe_stall(m66592, 0);
  958. spin_lock(&m66592->lock);
  959. }
  960. break;
  961. case M66592_CS_RDSS:
  962. case M66592_CS_WRSS:
  963. control_end(m66592, 0);
  964. break;
  965. default:
  966. printk(KERN_ERR "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  967. break;
  968. }
  969. }
  970. static irqreturn_t m66592_irq(int irq, void *_m66592)
  971. {
  972. struct m66592 *m66592 = _m66592;
  973. u16 intsts0;
  974. u16 intenb0;
  975. u16 brdysts, nrdysts, bempsts;
  976. u16 brdyenb, nrdyenb, bempenb;
  977. u16 savepipe;
  978. u16 mask0;
  979. spin_lock(&m66592->lock);
  980. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  981. intenb0 = m66592_read(m66592, M66592_INTENB0);
  982. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  983. mask0 = intsts0 & intenb0;
  984. if (mask0) {
  985. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  986. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  987. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  988. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  989. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  990. bempenb = m66592_read(m66592, M66592_BEMPENB);
  991. if (mask0 & M66592_VBINT) {
  992. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  993. M66592_INTSTS0);
  994. m66592_start_xclock(m66592);
  995. /* start vbus sampling */
  996. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  997. & M66592_VBSTS;
  998. m66592->scount = M66592_MAX_SAMPLING;
  999. mod_timer(&m66592->timer,
  1000. jiffies + msecs_to_jiffies(50));
  1001. }
  1002. if (intsts0 & M66592_DVSQ)
  1003. irq_device_state(m66592);
  1004. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1005. && (brdysts & brdyenb)) {
  1006. irq_pipe_ready(m66592, brdysts, brdyenb);
  1007. }
  1008. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1009. && (bempsts & bempenb)) {
  1010. irq_pipe_empty(m66592, bempsts, bempenb);
  1011. }
  1012. if (intsts0 & M66592_CTRT)
  1013. irq_control_stage(m66592);
  1014. }
  1015. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1016. spin_unlock(&m66592->lock);
  1017. return IRQ_HANDLED;
  1018. }
  1019. static void m66592_timer(unsigned long _m66592)
  1020. {
  1021. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1022. unsigned long flags;
  1023. u16 tmp;
  1024. spin_lock_irqsave(&m66592->lock, flags);
  1025. tmp = m66592_read(m66592, M66592_SYSCFG);
  1026. if (!(tmp & M66592_RCKE)) {
  1027. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1028. udelay(10);
  1029. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1030. }
  1031. if (m66592->scount > 0) {
  1032. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1033. if (tmp == m66592->old_vbus) {
  1034. m66592->scount--;
  1035. if (m66592->scount == 0) {
  1036. if (tmp == M66592_VBSTS)
  1037. m66592_usb_connect(m66592);
  1038. else
  1039. m66592_usb_disconnect(m66592);
  1040. } else {
  1041. mod_timer(&m66592->timer,
  1042. jiffies + msecs_to_jiffies(50));
  1043. }
  1044. } else {
  1045. m66592->scount = M66592_MAX_SAMPLING;
  1046. m66592->old_vbus = tmp;
  1047. mod_timer(&m66592->timer,
  1048. jiffies + msecs_to_jiffies(50));
  1049. }
  1050. }
  1051. spin_unlock_irqrestore(&m66592->lock, flags);
  1052. }
  1053. /*-------------------------------------------------------------------------*/
  1054. static int m66592_enable(struct usb_ep *_ep,
  1055. const struct usb_endpoint_descriptor *desc)
  1056. {
  1057. struct m66592_ep *ep;
  1058. ep = container_of(_ep, struct m66592_ep, ep);
  1059. return alloc_pipe_config(ep, desc);
  1060. }
  1061. static int m66592_disable(struct usb_ep *_ep)
  1062. {
  1063. struct m66592_ep *ep;
  1064. struct m66592_request *req;
  1065. unsigned long flags;
  1066. ep = container_of(_ep, struct m66592_ep, ep);
  1067. BUG_ON(!ep);
  1068. while (!list_empty(&ep->queue)) {
  1069. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1070. spin_lock_irqsave(&ep->m66592->lock, flags);
  1071. transfer_complete(ep, req, -ECONNRESET);
  1072. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1073. }
  1074. pipe_irq_disable(ep->m66592, ep->pipenum);
  1075. return free_pipe_config(ep);
  1076. }
  1077. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1078. gfp_t gfp_flags)
  1079. {
  1080. struct m66592_request *req;
  1081. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1082. if (!req)
  1083. return NULL;
  1084. INIT_LIST_HEAD(&req->queue);
  1085. return &req->req;
  1086. }
  1087. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1088. {
  1089. struct m66592_request *req;
  1090. req = container_of(_req, struct m66592_request, req);
  1091. kfree(req);
  1092. }
  1093. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1094. gfp_t gfp_flags)
  1095. {
  1096. struct m66592_ep *ep;
  1097. struct m66592_request *req;
  1098. unsigned long flags;
  1099. int request = 0;
  1100. ep = container_of(_ep, struct m66592_ep, ep);
  1101. req = container_of(_req, struct m66592_request, req);
  1102. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1103. return -ESHUTDOWN;
  1104. spin_lock_irqsave(&ep->m66592->lock, flags);
  1105. if (list_empty(&ep->queue))
  1106. request = 1;
  1107. list_add_tail(&req->queue, &ep->queue);
  1108. req->req.actual = 0;
  1109. req->req.status = -EINPROGRESS;
  1110. if (ep->desc == NULL) /* control */
  1111. start_ep0(ep, req);
  1112. else {
  1113. if (request && !ep->busy)
  1114. start_packet(ep, req);
  1115. }
  1116. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1117. return 0;
  1118. }
  1119. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1120. {
  1121. struct m66592_ep *ep;
  1122. struct m66592_request *req;
  1123. unsigned long flags;
  1124. ep = container_of(_ep, struct m66592_ep, ep);
  1125. req = container_of(_req, struct m66592_request, req);
  1126. spin_lock_irqsave(&ep->m66592->lock, flags);
  1127. if (!list_empty(&ep->queue))
  1128. transfer_complete(ep, req, -ECONNRESET);
  1129. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1130. return 0;
  1131. }
  1132. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1133. {
  1134. struct m66592_ep *ep;
  1135. struct m66592_request *req;
  1136. unsigned long flags;
  1137. int ret = 0;
  1138. ep = container_of(_ep, struct m66592_ep, ep);
  1139. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1140. spin_lock_irqsave(&ep->m66592->lock, flags);
  1141. if (!list_empty(&ep->queue)) {
  1142. ret = -EAGAIN;
  1143. goto out;
  1144. }
  1145. if (value) {
  1146. ep->busy = 1;
  1147. pipe_stall(ep->m66592, ep->pipenum);
  1148. } else {
  1149. ep->busy = 0;
  1150. pipe_stop(ep->m66592, ep->pipenum);
  1151. }
  1152. out:
  1153. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1154. return ret;
  1155. }
  1156. static void m66592_fifo_flush(struct usb_ep *_ep)
  1157. {
  1158. struct m66592_ep *ep;
  1159. unsigned long flags;
  1160. ep = container_of(_ep, struct m66592_ep, ep);
  1161. spin_lock_irqsave(&ep->m66592->lock, flags);
  1162. if (list_empty(&ep->queue) && !ep->busy) {
  1163. pipe_stop(ep->m66592, ep->pipenum);
  1164. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1165. }
  1166. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1167. }
  1168. static struct usb_ep_ops m66592_ep_ops = {
  1169. .enable = m66592_enable,
  1170. .disable = m66592_disable,
  1171. .alloc_request = m66592_alloc_request,
  1172. .free_request = m66592_free_request,
  1173. .queue = m66592_queue,
  1174. .dequeue = m66592_dequeue,
  1175. .set_halt = m66592_set_halt,
  1176. .fifo_flush = m66592_fifo_flush,
  1177. };
  1178. /*-------------------------------------------------------------------------*/
  1179. static struct m66592 *the_controller;
  1180. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1181. {
  1182. struct m66592 *m66592 = the_controller;
  1183. int retval;
  1184. if (!driver
  1185. || driver->speed != USB_SPEED_HIGH
  1186. || !driver->bind
  1187. || !driver->setup)
  1188. return -EINVAL;
  1189. if (!m66592)
  1190. return -ENODEV;
  1191. if (m66592->driver)
  1192. return -EBUSY;
  1193. /* hook up the driver */
  1194. driver->driver.bus = NULL;
  1195. m66592->driver = driver;
  1196. m66592->gadget.dev.driver = &driver->driver;
  1197. retval = device_add(&m66592->gadget.dev);
  1198. if (retval) {
  1199. printk(KERN_ERR "device_add error (%d)\n", retval);
  1200. goto error;
  1201. }
  1202. retval = driver->bind (&m66592->gadget);
  1203. if (retval) {
  1204. printk(KERN_ERR "bind to driver error (%d)\n", retval);
  1205. device_del(&m66592->gadget.dev);
  1206. goto error;
  1207. }
  1208. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1209. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1210. m66592_start_xclock(m66592);
  1211. /* start vbus sampling */
  1212. m66592->old_vbus = m66592_read(m66592,
  1213. M66592_INTSTS0) & M66592_VBSTS;
  1214. m66592->scount = M66592_MAX_SAMPLING;
  1215. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1216. }
  1217. return 0;
  1218. error:
  1219. m66592->driver = NULL;
  1220. m66592->gadget.dev.driver = NULL;
  1221. return retval;
  1222. }
  1223. EXPORT_SYMBOL(usb_gadget_register_driver);
  1224. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1225. {
  1226. struct m66592 *m66592 = the_controller;
  1227. unsigned long flags;
  1228. if (driver != m66592->driver || !driver->unbind)
  1229. return -EINVAL;
  1230. spin_lock_irqsave(&m66592->lock, flags);
  1231. if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
  1232. m66592_usb_disconnect(m66592);
  1233. spin_unlock_irqrestore(&m66592->lock, flags);
  1234. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1235. driver->unbind(&m66592->gadget);
  1236. init_controller(m66592);
  1237. disable_controller(m66592);
  1238. device_del(&m66592->gadget.dev);
  1239. m66592->driver = NULL;
  1240. return 0;
  1241. }
  1242. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1243. /*-------------------------------------------------------------------------*/
  1244. static int m66592_get_frame(struct usb_gadget *_gadget)
  1245. {
  1246. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1247. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1248. }
  1249. static struct usb_gadget_ops m66592_gadget_ops = {
  1250. .get_frame = m66592_get_frame,
  1251. };
  1252. static int __exit m66592_remove(struct platform_device *pdev)
  1253. {
  1254. struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
  1255. del_timer_sync(&m66592->timer);
  1256. iounmap(m66592->reg);
  1257. free_irq(platform_get_irq(pdev, 0), m66592);
  1258. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1259. kfree(m66592);
  1260. return 0;
  1261. }
  1262. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1263. {
  1264. }
  1265. #define resource_len(r) (((r)->end - (r)->start) + 1)
  1266. static int __init m66592_probe(struct platform_device *pdev)
  1267. {
  1268. struct resource *res;
  1269. int irq;
  1270. void __iomem *reg = NULL;
  1271. struct m66592 *m66592 = NULL;
  1272. int ret = 0;
  1273. int i;
  1274. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1275. (char *)udc_name);
  1276. if (!res) {
  1277. ret = -ENODEV;
  1278. printk(KERN_ERR "platform_get_resource_byname error.\n");
  1279. goto clean_up;
  1280. }
  1281. irq = platform_get_irq(pdev, 0);
  1282. if (irq < 0) {
  1283. ret = -ENODEV;
  1284. printk(KERN_ERR "platform_get_irq error.\n");
  1285. goto clean_up;
  1286. }
  1287. reg = ioremap(res->start, resource_len(res));
  1288. if (reg == NULL) {
  1289. ret = -ENOMEM;
  1290. printk(KERN_ERR "ioremap error.\n");
  1291. goto clean_up;
  1292. }
  1293. /* initialize ucd */
  1294. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1295. if (m66592 == NULL) {
  1296. printk(KERN_ERR "kzalloc error\n");
  1297. goto clean_up;
  1298. }
  1299. spin_lock_init(&m66592->lock);
  1300. dev_set_drvdata(&pdev->dev, m66592);
  1301. m66592->gadget.ops = &m66592_gadget_ops;
  1302. device_initialize(&m66592->gadget.dev);
  1303. strcpy(m66592->gadget.dev.bus_id, "gadget");
  1304. m66592->gadget.is_dualspeed = 1;
  1305. m66592->gadget.dev.parent = &pdev->dev;
  1306. m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1307. m66592->gadget.dev.release = pdev->dev.release;
  1308. m66592->gadget.name = udc_name;
  1309. init_timer(&m66592->timer);
  1310. m66592->timer.function = m66592_timer;
  1311. m66592->timer.data = (unsigned long)m66592;
  1312. m66592->reg = reg;
  1313. m66592->bi_bufnum = M66592_BASE_BUFNUM;
  1314. ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
  1315. udc_name, m66592);
  1316. if (ret < 0) {
  1317. printk(KERN_ERR "request_irq error (%d)\n", ret);
  1318. goto clean_up;
  1319. }
  1320. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1321. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1322. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1323. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1324. struct m66592_ep *ep = &m66592->ep[i];
  1325. if (i != 0) {
  1326. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1327. list_add_tail(&m66592->ep[i].ep.ep_list,
  1328. &m66592->gadget.ep_list);
  1329. }
  1330. ep->m66592 = m66592;
  1331. INIT_LIST_HEAD(&ep->queue);
  1332. ep->ep.name = m66592_ep_name[i];
  1333. ep->ep.ops = &m66592_ep_ops;
  1334. ep->ep.maxpacket = 512;
  1335. }
  1336. m66592->ep[0].ep.maxpacket = 64;
  1337. m66592->ep[0].pipenum = 0;
  1338. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1339. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1340. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1341. m66592->ep[0].fifotrn = 0;
  1342. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1343. m66592->pipenum2ep[0] = &m66592->ep[0];
  1344. m66592->epaddr2ep[0] = &m66592->ep[0];
  1345. the_controller = m66592;
  1346. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1347. if (m66592->ep0_req == NULL)
  1348. goto clean_up2;
  1349. m66592->ep0_req->complete = nop_completion;
  1350. init_controller(m66592);
  1351. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1352. return 0;
  1353. clean_up2:
  1354. free_irq(irq, m66592);
  1355. clean_up:
  1356. if (m66592) {
  1357. if (m66592->ep0_req)
  1358. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1359. kfree(m66592);
  1360. }
  1361. if (reg)
  1362. iounmap(reg);
  1363. return ret;
  1364. }
  1365. /*-------------------------------------------------------------------------*/
  1366. static struct platform_driver m66592_driver = {
  1367. .remove = __exit_p(m66592_remove),
  1368. .driver = {
  1369. .name = (char *) udc_name,
  1370. },
  1371. };
  1372. static int __init m66592_udc_init(void)
  1373. {
  1374. return platform_driver_probe(&m66592_driver, m66592_probe);
  1375. }
  1376. module_init(m66592_udc_init);
  1377. static void __exit m66592_udc_cleanup(void)
  1378. {
  1379. platform_driver_unregister(&m66592_driver);
  1380. }
  1381. module_exit(m66592_udc_cleanup);