atmel_usba_udc.c 49 KB

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  1. /*
  2. * Driver for the Atmel USBA high speed USB device controller
  3. *
  4. * Copyright (C) 2005-2007 Atmel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/device.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/list.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/usb/ch9.h>
  20. #include <linux/usb/gadget.h>
  21. #include <linux/delay.h>
  22. #include <asm/gpio.h>
  23. #include <asm/arch/board.h>
  24. #include "atmel_usba_udc.h"
  25. static struct usba_udc the_udc;
  26. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  27. #include <linux/debugfs.h>
  28. #include <linux/uaccess.h>
  29. static int queue_dbg_open(struct inode *inode, struct file *file)
  30. {
  31. struct usba_ep *ep = inode->i_private;
  32. struct usba_request *req, *req_copy;
  33. struct list_head *queue_data;
  34. queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
  35. if (!queue_data)
  36. return -ENOMEM;
  37. INIT_LIST_HEAD(queue_data);
  38. spin_lock_irq(&ep->udc->lock);
  39. list_for_each_entry(req, &ep->queue, queue) {
  40. req_copy = kmalloc(sizeof(*req_copy), GFP_ATOMIC);
  41. if (!req_copy)
  42. goto fail;
  43. memcpy(req_copy, req, sizeof(*req_copy));
  44. list_add_tail(&req_copy->queue, queue_data);
  45. }
  46. spin_unlock_irq(&ep->udc->lock);
  47. file->private_data = queue_data;
  48. return 0;
  49. fail:
  50. spin_unlock_irq(&ep->udc->lock);
  51. list_for_each_entry_safe(req, req_copy, queue_data, queue) {
  52. list_del(&req->queue);
  53. kfree(req);
  54. }
  55. kfree(queue_data);
  56. return -ENOMEM;
  57. }
  58. /*
  59. * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
  60. *
  61. * b: buffer address
  62. * l: buffer length
  63. * I/i: interrupt/no interrupt
  64. * Z/z: zero/no zero
  65. * S/s: short ok/short not ok
  66. * s: status
  67. * n: nr_packets
  68. * F/f: submitted/not submitted to FIFO
  69. * D/d: using/not using DMA
  70. * L/l: last transaction/not last transaction
  71. */
  72. static ssize_t queue_dbg_read(struct file *file, char __user *buf,
  73. size_t nbytes, loff_t *ppos)
  74. {
  75. struct list_head *queue = file->private_data;
  76. struct usba_request *req, *tmp_req;
  77. size_t len, remaining, actual = 0;
  78. char tmpbuf[38];
  79. if (!access_ok(VERIFY_WRITE, buf, nbytes))
  80. return -EFAULT;
  81. mutex_lock(&file->f_dentry->d_inode->i_mutex);
  82. list_for_each_entry_safe(req, tmp_req, queue, queue) {
  83. len = snprintf(tmpbuf, sizeof(tmpbuf),
  84. "%8p %08x %c%c%c %5d %c%c%c\n",
  85. req->req.buf, req->req.length,
  86. req->req.no_interrupt ? 'i' : 'I',
  87. req->req.zero ? 'Z' : 'z',
  88. req->req.short_not_ok ? 's' : 'S',
  89. req->req.status,
  90. req->submitted ? 'F' : 'f',
  91. req->using_dma ? 'D' : 'd',
  92. req->last_transaction ? 'L' : 'l');
  93. len = min(len, sizeof(tmpbuf));
  94. if (len > nbytes)
  95. break;
  96. list_del(&req->queue);
  97. kfree(req);
  98. remaining = __copy_to_user(buf, tmpbuf, len);
  99. actual += len - remaining;
  100. if (remaining)
  101. break;
  102. nbytes -= len;
  103. buf += len;
  104. }
  105. mutex_unlock(&file->f_dentry->d_inode->i_mutex);
  106. return actual;
  107. }
  108. static int queue_dbg_release(struct inode *inode, struct file *file)
  109. {
  110. struct list_head *queue_data = file->private_data;
  111. struct usba_request *req, *tmp_req;
  112. list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
  113. list_del(&req->queue);
  114. kfree(req);
  115. }
  116. kfree(queue_data);
  117. return 0;
  118. }
  119. static int regs_dbg_open(struct inode *inode, struct file *file)
  120. {
  121. struct usba_udc *udc;
  122. unsigned int i;
  123. u32 *data;
  124. int ret = -ENOMEM;
  125. mutex_lock(&inode->i_mutex);
  126. udc = inode->i_private;
  127. data = kmalloc(inode->i_size, GFP_KERNEL);
  128. if (!data)
  129. goto out;
  130. spin_lock_irq(&udc->lock);
  131. for (i = 0; i < inode->i_size / 4; i++)
  132. data[i] = __raw_readl(udc->regs + i * 4);
  133. spin_unlock_irq(&udc->lock);
  134. file->private_data = data;
  135. ret = 0;
  136. out:
  137. mutex_unlock(&inode->i_mutex);
  138. return ret;
  139. }
  140. static ssize_t regs_dbg_read(struct file *file, char __user *buf,
  141. size_t nbytes, loff_t *ppos)
  142. {
  143. struct inode *inode = file->f_dentry->d_inode;
  144. int ret;
  145. mutex_lock(&inode->i_mutex);
  146. ret = simple_read_from_buffer(buf, nbytes, ppos,
  147. file->private_data,
  148. file->f_dentry->d_inode->i_size);
  149. mutex_unlock(&inode->i_mutex);
  150. return ret;
  151. }
  152. static int regs_dbg_release(struct inode *inode, struct file *file)
  153. {
  154. kfree(file->private_data);
  155. return 0;
  156. }
  157. const struct file_operations queue_dbg_fops = {
  158. .owner = THIS_MODULE,
  159. .open = queue_dbg_open,
  160. .llseek = no_llseek,
  161. .read = queue_dbg_read,
  162. .release = queue_dbg_release,
  163. };
  164. const struct file_operations regs_dbg_fops = {
  165. .owner = THIS_MODULE,
  166. .open = regs_dbg_open,
  167. .llseek = generic_file_llseek,
  168. .read = regs_dbg_read,
  169. .release = regs_dbg_release,
  170. };
  171. static void usba_ep_init_debugfs(struct usba_udc *udc,
  172. struct usba_ep *ep)
  173. {
  174. struct dentry *ep_root;
  175. ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
  176. if (!ep_root)
  177. goto err_root;
  178. ep->debugfs_dir = ep_root;
  179. ep->debugfs_queue = debugfs_create_file("queue", 0400, ep_root,
  180. ep, &queue_dbg_fops);
  181. if (!ep->debugfs_queue)
  182. goto err_queue;
  183. if (ep->can_dma) {
  184. ep->debugfs_dma_status
  185. = debugfs_create_u32("dma_status", 0400, ep_root,
  186. &ep->last_dma_status);
  187. if (!ep->debugfs_dma_status)
  188. goto err_dma_status;
  189. }
  190. if (ep_is_control(ep)) {
  191. ep->debugfs_state
  192. = debugfs_create_u32("state", 0400, ep_root,
  193. &ep->state);
  194. if (!ep->debugfs_state)
  195. goto err_state;
  196. }
  197. return;
  198. err_state:
  199. if (ep->can_dma)
  200. debugfs_remove(ep->debugfs_dma_status);
  201. err_dma_status:
  202. debugfs_remove(ep->debugfs_queue);
  203. err_queue:
  204. debugfs_remove(ep_root);
  205. err_root:
  206. dev_err(&ep->udc->pdev->dev,
  207. "failed to create debugfs directory for %s\n", ep->ep.name);
  208. }
  209. static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  210. {
  211. debugfs_remove(ep->debugfs_queue);
  212. debugfs_remove(ep->debugfs_dma_status);
  213. debugfs_remove(ep->debugfs_state);
  214. debugfs_remove(ep->debugfs_dir);
  215. ep->debugfs_dma_status = NULL;
  216. ep->debugfs_dir = NULL;
  217. }
  218. static void usba_init_debugfs(struct usba_udc *udc)
  219. {
  220. struct dentry *root, *regs;
  221. struct resource *regs_resource;
  222. root = debugfs_create_dir(udc->gadget.name, NULL);
  223. if (IS_ERR(root) || !root)
  224. goto err_root;
  225. udc->debugfs_root = root;
  226. regs = debugfs_create_file("regs", 0400, root, udc, &regs_dbg_fops);
  227. if (!regs)
  228. goto err_regs;
  229. regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
  230. CTRL_IOMEM_ID);
  231. regs->d_inode->i_size = regs_resource->end - regs_resource->start + 1;
  232. udc->debugfs_regs = regs;
  233. usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
  234. return;
  235. err_regs:
  236. debugfs_remove(root);
  237. err_root:
  238. udc->debugfs_root = NULL;
  239. dev_err(&udc->pdev->dev, "debugfs is not available\n");
  240. }
  241. static void usba_cleanup_debugfs(struct usba_udc *udc)
  242. {
  243. usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
  244. debugfs_remove(udc->debugfs_regs);
  245. debugfs_remove(udc->debugfs_root);
  246. udc->debugfs_regs = NULL;
  247. udc->debugfs_root = NULL;
  248. }
  249. #else
  250. static inline void usba_ep_init_debugfs(struct usba_udc *udc,
  251. struct usba_ep *ep)
  252. {
  253. }
  254. static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
  255. {
  256. }
  257. static inline void usba_init_debugfs(struct usba_udc *udc)
  258. {
  259. }
  260. static inline void usba_cleanup_debugfs(struct usba_udc *udc)
  261. {
  262. }
  263. #endif
  264. static int vbus_is_present(struct usba_udc *udc)
  265. {
  266. if (udc->vbus_pin != -1)
  267. return gpio_get_value(udc->vbus_pin);
  268. /* No Vbus detection: Assume always present */
  269. return 1;
  270. }
  271. static void copy_to_fifo(void __iomem *fifo, const void *buf, int len)
  272. {
  273. unsigned long tmp;
  274. DBG(DBG_FIFO, "copy to FIFO (len %d):\n", len);
  275. for (; len > 0; len -= 4, buf += 4, fifo += 4) {
  276. tmp = *(unsigned long *)buf;
  277. if (len >= 4) {
  278. DBG(DBG_FIFO, " -> %08lx\n", tmp);
  279. __raw_writel(tmp, fifo);
  280. } else {
  281. do {
  282. DBG(DBG_FIFO, " -> %02lx\n", tmp >> 24);
  283. __raw_writeb(tmp >> 24, fifo);
  284. fifo++;
  285. tmp <<= 8;
  286. } while (--len);
  287. break;
  288. }
  289. }
  290. }
  291. static void copy_from_fifo(void *buf, void __iomem *fifo, int len)
  292. {
  293. union {
  294. unsigned long *w;
  295. unsigned char *b;
  296. } p;
  297. unsigned long tmp;
  298. DBG(DBG_FIFO, "copy from FIFO (len %d):\n", len);
  299. for (p.w = buf; len > 0; len -= 4, p.w++, fifo += 4) {
  300. if (len >= 4) {
  301. tmp = __raw_readl(fifo);
  302. *p.w = tmp;
  303. DBG(DBG_FIFO, " -> %08lx\n", tmp);
  304. } else {
  305. do {
  306. tmp = __raw_readb(fifo);
  307. *p.b = tmp;
  308. DBG(DBG_FIFO, " -> %02lx\n", tmp);
  309. fifo++, p.b++;
  310. } while (--len);
  311. }
  312. }
  313. }
  314. static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
  315. {
  316. unsigned int transaction_len;
  317. transaction_len = req->req.length - req->req.actual;
  318. req->last_transaction = 1;
  319. if (transaction_len > ep->ep.maxpacket) {
  320. transaction_len = ep->ep.maxpacket;
  321. req->last_transaction = 0;
  322. } else if (transaction_len == ep->ep.maxpacket && req->req.zero)
  323. req->last_transaction = 0;
  324. DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
  325. ep->ep.name, req, transaction_len,
  326. req->last_transaction ? ", done" : "");
  327. copy_to_fifo(ep->fifo, req->req.buf + req->req.actual, transaction_len);
  328. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  329. req->req.actual += transaction_len;
  330. }
  331. static void submit_request(struct usba_ep *ep, struct usba_request *req)
  332. {
  333. DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
  334. ep->ep.name, req, req->req.length);
  335. req->req.actual = 0;
  336. req->submitted = 1;
  337. if (req->using_dma) {
  338. if (req->req.length == 0) {
  339. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  340. return;
  341. }
  342. if (req->req.zero)
  343. usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
  344. else
  345. usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
  346. usba_dma_writel(ep, ADDRESS, req->req.dma);
  347. usba_dma_writel(ep, CONTROL, req->ctrl);
  348. } else {
  349. next_fifo_transaction(ep, req);
  350. if (req->last_transaction) {
  351. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  352. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  353. } else {
  354. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  355. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  356. }
  357. }
  358. }
  359. static void submit_next_request(struct usba_ep *ep)
  360. {
  361. struct usba_request *req;
  362. if (list_empty(&ep->queue)) {
  363. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
  364. return;
  365. }
  366. req = list_entry(ep->queue.next, struct usba_request, queue);
  367. if (!req->submitted)
  368. submit_request(ep, req);
  369. }
  370. static void send_status(struct usba_udc *udc, struct usba_ep *ep)
  371. {
  372. ep->state = STATUS_STAGE_IN;
  373. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  374. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  375. }
  376. static void receive_data(struct usba_ep *ep)
  377. {
  378. struct usba_udc *udc = ep->udc;
  379. struct usba_request *req;
  380. unsigned long status;
  381. unsigned int bytecount, nr_busy;
  382. int is_complete = 0;
  383. status = usba_ep_readl(ep, STA);
  384. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  385. DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
  386. while (nr_busy > 0) {
  387. if (list_empty(&ep->queue)) {
  388. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  389. break;
  390. }
  391. req = list_entry(ep->queue.next,
  392. struct usba_request, queue);
  393. bytecount = USBA_BFEXT(BYTE_COUNT, status);
  394. if (status & (1 << 31))
  395. is_complete = 1;
  396. if (req->req.actual + bytecount >= req->req.length) {
  397. is_complete = 1;
  398. bytecount = req->req.length - req->req.actual;
  399. }
  400. copy_from_fifo(req->req.buf + req->req.actual,
  401. ep->fifo, bytecount);
  402. req->req.actual += bytecount;
  403. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  404. if (is_complete) {
  405. DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
  406. req->req.status = 0;
  407. list_del_init(&req->queue);
  408. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  409. spin_unlock(&udc->lock);
  410. req->req.complete(&ep->ep, &req->req);
  411. spin_lock(&udc->lock);
  412. }
  413. status = usba_ep_readl(ep, STA);
  414. nr_busy = USBA_BFEXT(BUSY_BANKS, status);
  415. if (is_complete && ep_is_control(ep)) {
  416. send_status(udc, ep);
  417. break;
  418. }
  419. }
  420. }
  421. static void
  422. request_complete(struct usba_ep *ep, struct usba_request *req, int status)
  423. {
  424. struct usba_udc *udc = ep->udc;
  425. WARN_ON(!list_empty(&req->queue));
  426. if (req->req.status == -EINPROGRESS)
  427. req->req.status = status;
  428. if (req->mapped) {
  429. dma_unmap_single(
  430. &udc->pdev->dev, req->req.dma, req->req.length,
  431. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  432. req->req.dma = DMA_ADDR_INVALID;
  433. req->mapped = 0;
  434. }
  435. DBG(DBG_GADGET | DBG_REQ,
  436. "%s: req %p complete: status %d, actual %u\n",
  437. ep->ep.name, req, req->req.status, req->req.actual);
  438. spin_unlock(&udc->lock);
  439. req->req.complete(&ep->ep, &req->req);
  440. spin_lock(&udc->lock);
  441. }
  442. static void
  443. request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
  444. {
  445. struct usba_request *req, *tmp_req;
  446. list_for_each_entry_safe(req, tmp_req, list, queue) {
  447. list_del_init(&req->queue);
  448. request_complete(ep, req, status);
  449. }
  450. }
  451. static int
  452. usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
  453. {
  454. struct usba_ep *ep = to_usba_ep(_ep);
  455. struct usba_udc *udc = ep->udc;
  456. unsigned long flags, ept_cfg, maxpacket;
  457. unsigned int nr_trans;
  458. DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
  459. maxpacket = le16_to_cpu(desc->wMaxPacketSize) & 0x7ff;
  460. if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
  461. || ep->index == 0
  462. || desc->bDescriptorType != USB_DT_ENDPOINT
  463. || maxpacket == 0
  464. || maxpacket > ep->fifo_size) {
  465. DBG(DBG_ERR, "ep_enable: Invalid argument");
  466. return -EINVAL;
  467. }
  468. ep->is_isoc = 0;
  469. ep->is_in = 0;
  470. if (maxpacket <= 8)
  471. ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
  472. else
  473. /* LSB is bit 1, not 0 */
  474. ept_cfg = USBA_BF(EPT_SIZE, fls(maxpacket - 1) - 3);
  475. DBG(DBG_HW, "%s: EPT_SIZE = %lu (maxpacket = %lu)\n",
  476. ep->ep.name, ept_cfg, maxpacket);
  477. if ((desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) {
  478. ep->is_in = 1;
  479. ept_cfg |= USBA_EPT_DIR_IN;
  480. }
  481. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  482. case USB_ENDPOINT_XFER_CONTROL:
  483. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
  484. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE);
  485. break;
  486. case USB_ENDPOINT_XFER_ISOC:
  487. if (!ep->can_isoc) {
  488. DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
  489. ep->ep.name);
  490. return -EINVAL;
  491. }
  492. /*
  493. * Bits 11:12 specify number of _additional_
  494. * transactions per microframe.
  495. */
  496. nr_trans = ((le16_to_cpu(desc->wMaxPacketSize) >> 11) & 3) + 1;
  497. if (nr_trans > 3)
  498. return -EINVAL;
  499. ep->is_isoc = 1;
  500. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
  501. /*
  502. * Do triple-buffering on high-bandwidth iso endpoints.
  503. */
  504. if (nr_trans > 1 && ep->nr_banks == 3)
  505. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_TRIPLE);
  506. else
  507. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  508. ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
  509. break;
  510. case USB_ENDPOINT_XFER_BULK:
  511. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
  512. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  513. break;
  514. case USB_ENDPOINT_XFER_INT:
  515. ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
  516. ept_cfg |= USBA_BF(BK_NUMBER, USBA_BK_NUMBER_DOUBLE);
  517. break;
  518. }
  519. spin_lock_irqsave(&ep->udc->lock, flags);
  520. if (ep->desc) {
  521. spin_unlock_irqrestore(&ep->udc->lock, flags);
  522. DBG(DBG_ERR, "ep%d already enabled\n", ep->index);
  523. return -EBUSY;
  524. }
  525. ep->desc = desc;
  526. ep->ep.maxpacket = maxpacket;
  527. usba_ep_writel(ep, CFG, ept_cfg);
  528. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  529. if (ep->can_dma) {
  530. u32 ctrl;
  531. usba_writel(udc, INT_ENB,
  532. (usba_readl(udc, INT_ENB)
  533. | USBA_BF(EPT_INT, 1 << ep->index)
  534. | USBA_BF(DMA_INT, 1 << ep->index)));
  535. ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
  536. usba_ep_writel(ep, CTL_ENB, ctrl);
  537. } else {
  538. usba_writel(udc, INT_ENB,
  539. (usba_readl(udc, INT_ENB)
  540. | USBA_BF(EPT_INT, 1 << ep->index)));
  541. }
  542. spin_unlock_irqrestore(&udc->lock, flags);
  543. DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
  544. (unsigned long)usba_ep_readl(ep, CFG));
  545. DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
  546. (unsigned long)usba_readl(udc, INT_ENB));
  547. return 0;
  548. }
  549. static int usba_ep_disable(struct usb_ep *_ep)
  550. {
  551. struct usba_ep *ep = to_usba_ep(_ep);
  552. struct usba_udc *udc = ep->udc;
  553. LIST_HEAD(req_list);
  554. unsigned long flags;
  555. DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
  556. spin_lock_irqsave(&udc->lock, flags);
  557. if (!ep->desc) {
  558. spin_unlock_irqrestore(&udc->lock, flags);
  559. DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
  560. return -EINVAL;
  561. }
  562. ep->desc = NULL;
  563. list_splice_init(&ep->queue, &req_list);
  564. if (ep->can_dma) {
  565. usba_dma_writel(ep, CONTROL, 0);
  566. usba_dma_writel(ep, ADDRESS, 0);
  567. usba_dma_readl(ep, STATUS);
  568. }
  569. usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
  570. usba_writel(udc, INT_ENB,
  571. usba_readl(udc, INT_ENB)
  572. & ~USBA_BF(EPT_INT, 1 << ep->index));
  573. request_complete_list(ep, &req_list, -ESHUTDOWN);
  574. spin_unlock_irqrestore(&udc->lock, flags);
  575. return 0;
  576. }
  577. static struct usb_request *
  578. usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
  579. {
  580. struct usba_request *req;
  581. DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
  582. req = kzalloc(sizeof(*req), gfp_flags);
  583. if (!req)
  584. return NULL;
  585. INIT_LIST_HEAD(&req->queue);
  586. req->req.dma = DMA_ADDR_INVALID;
  587. return &req->req;
  588. }
  589. static void
  590. usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
  591. {
  592. struct usba_request *req = to_usba_req(_req);
  593. DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
  594. kfree(req);
  595. }
  596. static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
  597. struct usba_request *req, gfp_t gfp_flags)
  598. {
  599. unsigned long flags;
  600. int ret;
  601. DBG(DBG_DMA, "%s: req l/%u d/%08x %c%c%c\n",
  602. ep->ep.name, req->req.length, req->req.dma,
  603. req->req.zero ? 'Z' : 'z',
  604. req->req.short_not_ok ? 'S' : 's',
  605. req->req.no_interrupt ? 'I' : 'i');
  606. if (req->req.length > 0x10000) {
  607. /* Lengths from 0 to 65536 (inclusive) are supported */
  608. DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
  609. return -EINVAL;
  610. }
  611. req->using_dma = 1;
  612. if (req->req.dma == DMA_ADDR_INVALID) {
  613. req->req.dma = dma_map_single(
  614. &udc->pdev->dev, req->req.buf, req->req.length,
  615. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  616. req->mapped = 1;
  617. } else {
  618. dma_sync_single_for_device(
  619. &udc->pdev->dev, req->req.dma, req->req.length,
  620. ep->is_in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  621. req->mapped = 0;
  622. }
  623. req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
  624. | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
  625. | USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
  626. if (ep->is_in)
  627. req->ctrl |= USBA_DMA_END_BUF_EN;
  628. /*
  629. * Add this request to the queue and submit for DMA if
  630. * possible. Check if we're still alive first -- we may have
  631. * received a reset since last time we checked.
  632. */
  633. ret = -ESHUTDOWN;
  634. spin_lock_irqsave(&udc->lock, flags);
  635. if (ep->desc) {
  636. if (list_empty(&ep->queue))
  637. submit_request(ep, req);
  638. list_add_tail(&req->queue, &ep->queue);
  639. ret = 0;
  640. }
  641. spin_unlock_irqrestore(&udc->lock, flags);
  642. return ret;
  643. }
  644. static int
  645. usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
  646. {
  647. struct usba_request *req = to_usba_req(_req);
  648. struct usba_ep *ep = to_usba_ep(_ep);
  649. struct usba_udc *udc = ep->udc;
  650. unsigned long flags;
  651. int ret;
  652. DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
  653. ep->ep.name, req, _req->length);
  654. if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || !ep->desc)
  655. return -ESHUTDOWN;
  656. req->submitted = 0;
  657. req->using_dma = 0;
  658. req->last_transaction = 0;
  659. _req->status = -EINPROGRESS;
  660. _req->actual = 0;
  661. if (ep->can_dma)
  662. return queue_dma(udc, ep, req, gfp_flags);
  663. /* May have received a reset since last time we checked */
  664. ret = -ESHUTDOWN;
  665. spin_lock_irqsave(&udc->lock, flags);
  666. if (ep->desc) {
  667. list_add_tail(&req->queue, &ep->queue);
  668. if (ep->is_in || (ep_is_control(ep)
  669. && (ep->state == DATA_STAGE_IN
  670. || ep->state == STATUS_STAGE_IN)))
  671. usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
  672. else
  673. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  674. ret = 0;
  675. }
  676. spin_unlock_irqrestore(&udc->lock, flags);
  677. return ret;
  678. }
  679. static void
  680. usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
  681. {
  682. req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
  683. }
  684. static int stop_dma(struct usba_ep *ep, u32 *pstatus)
  685. {
  686. unsigned int timeout;
  687. u32 status;
  688. /*
  689. * Stop the DMA controller. When writing both CH_EN
  690. * and LINK to 0, the other bits are not affected.
  691. */
  692. usba_dma_writel(ep, CONTROL, 0);
  693. /* Wait for the FIFO to empty */
  694. for (timeout = 40; timeout; --timeout) {
  695. status = usba_dma_readl(ep, STATUS);
  696. if (!(status & USBA_DMA_CH_EN))
  697. break;
  698. udelay(1);
  699. }
  700. if (pstatus)
  701. *pstatus = status;
  702. if (timeout == 0) {
  703. dev_err(&ep->udc->pdev->dev,
  704. "%s: timed out waiting for DMA FIFO to empty\n",
  705. ep->ep.name);
  706. return -ETIMEDOUT;
  707. }
  708. return 0;
  709. }
  710. static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  711. {
  712. struct usba_ep *ep = to_usba_ep(_ep);
  713. struct usba_udc *udc = ep->udc;
  714. struct usba_request *req = to_usba_req(_req);
  715. unsigned long flags;
  716. u32 status;
  717. DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
  718. ep->ep.name, req);
  719. spin_lock_irqsave(&udc->lock, flags);
  720. if (req->using_dma) {
  721. /*
  722. * If this request is currently being transferred,
  723. * stop the DMA controller and reset the FIFO.
  724. */
  725. if (ep->queue.next == &req->queue) {
  726. status = usba_dma_readl(ep, STATUS);
  727. if (status & USBA_DMA_CH_EN)
  728. stop_dma(ep, &status);
  729. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  730. ep->last_dma_status = status;
  731. #endif
  732. usba_writel(udc, EPT_RST, 1 << ep->index);
  733. usba_update_req(ep, req, status);
  734. }
  735. }
  736. /*
  737. * Errors should stop the queue from advancing until the
  738. * completion function returns.
  739. */
  740. list_del_init(&req->queue);
  741. request_complete(ep, req, -ECONNRESET);
  742. /* Process the next request if any */
  743. submit_next_request(ep);
  744. spin_unlock_irqrestore(&udc->lock, flags);
  745. return 0;
  746. }
  747. static int usba_ep_set_halt(struct usb_ep *_ep, int value)
  748. {
  749. struct usba_ep *ep = to_usba_ep(_ep);
  750. struct usba_udc *udc = ep->udc;
  751. unsigned long flags;
  752. int ret = 0;
  753. DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
  754. value ? "set" : "clear");
  755. if (!ep->desc) {
  756. DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
  757. ep->ep.name);
  758. return -ENODEV;
  759. }
  760. if (ep->is_isoc) {
  761. DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
  762. ep->ep.name);
  763. return -ENOTTY;
  764. }
  765. spin_lock_irqsave(&udc->lock, flags);
  766. /*
  767. * We can't halt IN endpoints while there are still data to be
  768. * transferred
  769. */
  770. if (!list_empty(&ep->queue)
  771. || ((value && ep->is_in && (usba_ep_readl(ep, STA)
  772. & USBA_BF(BUSY_BANKS, -1L))))) {
  773. ret = -EAGAIN;
  774. } else {
  775. if (value)
  776. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  777. else
  778. usba_ep_writel(ep, CLR_STA,
  779. USBA_FORCE_STALL | USBA_TOGGLE_CLR);
  780. usba_ep_readl(ep, STA);
  781. }
  782. spin_unlock_irqrestore(&udc->lock, flags);
  783. return ret;
  784. }
  785. static int usba_ep_fifo_status(struct usb_ep *_ep)
  786. {
  787. struct usba_ep *ep = to_usba_ep(_ep);
  788. return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  789. }
  790. static void usba_ep_fifo_flush(struct usb_ep *_ep)
  791. {
  792. struct usba_ep *ep = to_usba_ep(_ep);
  793. struct usba_udc *udc = ep->udc;
  794. usba_writel(udc, EPT_RST, 1 << ep->index);
  795. }
  796. static const struct usb_ep_ops usba_ep_ops = {
  797. .enable = usba_ep_enable,
  798. .disable = usba_ep_disable,
  799. .alloc_request = usba_ep_alloc_request,
  800. .free_request = usba_ep_free_request,
  801. .queue = usba_ep_queue,
  802. .dequeue = usba_ep_dequeue,
  803. .set_halt = usba_ep_set_halt,
  804. .fifo_status = usba_ep_fifo_status,
  805. .fifo_flush = usba_ep_fifo_flush,
  806. };
  807. static int usba_udc_get_frame(struct usb_gadget *gadget)
  808. {
  809. struct usba_udc *udc = to_usba_udc(gadget);
  810. return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
  811. }
  812. static int usba_udc_wakeup(struct usb_gadget *gadget)
  813. {
  814. struct usba_udc *udc = to_usba_udc(gadget);
  815. unsigned long flags;
  816. u32 ctrl;
  817. int ret = -EINVAL;
  818. spin_lock_irqsave(&udc->lock, flags);
  819. if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
  820. ctrl = usba_readl(udc, CTRL);
  821. usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
  822. ret = 0;
  823. }
  824. spin_unlock_irqrestore(&udc->lock, flags);
  825. return ret;
  826. }
  827. static int
  828. usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
  829. {
  830. struct usba_udc *udc = to_usba_udc(gadget);
  831. unsigned long flags;
  832. spin_lock_irqsave(&udc->lock, flags);
  833. if (is_selfpowered)
  834. udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
  835. else
  836. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  837. spin_unlock_irqrestore(&udc->lock, flags);
  838. return 0;
  839. }
  840. static const struct usb_gadget_ops usba_udc_ops = {
  841. .get_frame = usba_udc_get_frame,
  842. .wakeup = usba_udc_wakeup,
  843. .set_selfpowered = usba_udc_set_selfpowered,
  844. };
  845. #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
  846. { \
  847. .ep = { \
  848. .ops = &usba_ep_ops, \
  849. .name = nam, \
  850. .maxpacket = maxpkt, \
  851. }, \
  852. .udc = &the_udc, \
  853. .queue = LIST_HEAD_INIT(usba_ep[idx].queue), \
  854. .fifo_size = maxpkt, \
  855. .nr_banks = maxbk, \
  856. .index = idx, \
  857. .can_dma = dma, \
  858. .can_isoc = isoc, \
  859. }
  860. static struct usba_ep usba_ep[] = {
  861. EP("ep0", 0, 64, 1, 0, 0),
  862. EP("ep1in-bulk", 1, 512, 2, 1, 1),
  863. EP("ep2out-bulk", 2, 512, 2, 1, 1),
  864. EP("ep3in-int", 3, 64, 3, 1, 0),
  865. EP("ep4out-int", 4, 64, 3, 1, 0),
  866. EP("ep5in-iso", 5, 1024, 3, 1, 1),
  867. EP("ep6out-iso", 6, 1024, 3, 1, 1),
  868. };
  869. #undef EP
  870. static struct usb_endpoint_descriptor usba_ep0_desc = {
  871. .bLength = USB_DT_ENDPOINT_SIZE,
  872. .bDescriptorType = USB_DT_ENDPOINT,
  873. .bEndpointAddress = 0,
  874. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  875. .wMaxPacketSize = __constant_cpu_to_le16(64),
  876. /* FIXME: I have no idea what to put here */
  877. .bInterval = 1,
  878. };
  879. static void nop_release(struct device *dev)
  880. {
  881. }
  882. static struct usba_udc the_udc = {
  883. .gadget = {
  884. .ops = &usba_udc_ops,
  885. .ep0 = &usba_ep[0].ep,
  886. .ep_list = LIST_HEAD_INIT(the_udc.gadget.ep_list),
  887. .is_dualspeed = 1,
  888. .name = "atmel_usba_udc",
  889. .dev = {
  890. .bus_id = "gadget",
  891. .release = nop_release,
  892. },
  893. },
  894. .lock = SPIN_LOCK_UNLOCKED,
  895. };
  896. /*
  897. * Called with interrupts disabled and udc->lock held.
  898. */
  899. static void reset_all_endpoints(struct usba_udc *udc)
  900. {
  901. struct usba_ep *ep;
  902. struct usba_request *req, *tmp_req;
  903. usba_writel(udc, EPT_RST, ~0UL);
  904. ep = to_usba_ep(udc->gadget.ep0);
  905. list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
  906. list_del_init(&req->queue);
  907. request_complete(ep, req, -ECONNRESET);
  908. }
  909. list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
  910. if (ep->desc) {
  911. spin_unlock(&udc->lock);
  912. usba_ep_disable(&ep->ep);
  913. spin_lock(&udc->lock);
  914. }
  915. }
  916. }
  917. static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
  918. {
  919. struct usba_ep *ep;
  920. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  921. return to_usba_ep(udc->gadget.ep0);
  922. list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
  923. u8 bEndpointAddress;
  924. if (!ep->desc)
  925. continue;
  926. bEndpointAddress = ep->desc->bEndpointAddress;
  927. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  928. continue;
  929. if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
  930. == (wIndex & USB_ENDPOINT_NUMBER_MASK))
  931. return ep;
  932. }
  933. return NULL;
  934. }
  935. /* Called with interrupts disabled and udc->lock held */
  936. static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
  937. {
  938. usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
  939. ep->state = WAIT_FOR_SETUP;
  940. }
  941. static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
  942. {
  943. if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
  944. return 1;
  945. return 0;
  946. }
  947. static inline void set_address(struct usba_udc *udc, unsigned int addr)
  948. {
  949. u32 regval;
  950. DBG(DBG_BUS, "setting address %u...\n", addr);
  951. regval = usba_readl(udc, CTRL);
  952. regval = USBA_BFINS(DEV_ADDR, addr, regval);
  953. usba_writel(udc, CTRL, regval);
  954. }
  955. static int do_test_mode(struct usba_udc *udc)
  956. {
  957. static const char test_packet_buffer[] = {
  958. /* JKJKJKJK * 9 */
  959. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  960. /* JJKKJJKK * 8 */
  961. 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
  962. /* JJKKJJKK * 8 */
  963. 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
  964. /* JJJJJJJKKKKKKK * 8 */
  965. 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  966. 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  967. /* JJJJJJJK * 8 */
  968. 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
  969. /* {JKKKKKKK * 10}, JK */
  970. 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
  971. };
  972. struct usba_ep *ep;
  973. struct device *dev = &udc->pdev->dev;
  974. int test_mode;
  975. test_mode = udc->test_mode;
  976. /* Start from a clean slate */
  977. reset_all_endpoints(udc);
  978. switch (test_mode) {
  979. case 0x0100:
  980. /* Test_J */
  981. usba_writel(udc, TST, USBA_TST_J_MODE);
  982. dev_info(dev, "Entering Test_J mode...\n");
  983. break;
  984. case 0x0200:
  985. /* Test_K */
  986. usba_writel(udc, TST, USBA_TST_K_MODE);
  987. dev_info(dev, "Entering Test_K mode...\n");
  988. break;
  989. case 0x0300:
  990. /*
  991. * Test_SE0_NAK: Force high-speed mode and set up ep0
  992. * for Bulk IN transfers
  993. */
  994. ep = &usba_ep[0];
  995. usba_writel(udc, TST,
  996. USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
  997. usba_ep_writel(ep, CFG,
  998. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  999. | USBA_EPT_DIR_IN
  1000. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  1001. | USBA_BF(BK_NUMBER, 1));
  1002. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  1003. set_protocol_stall(udc, ep);
  1004. dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
  1005. } else {
  1006. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  1007. dev_info(dev, "Entering Test_SE0_NAK mode...\n");
  1008. }
  1009. break;
  1010. case 0x0400:
  1011. /* Test_Packet */
  1012. ep = &usba_ep[0];
  1013. usba_ep_writel(ep, CFG,
  1014. USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
  1015. | USBA_EPT_DIR_IN
  1016. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
  1017. | USBA_BF(BK_NUMBER, 1));
  1018. if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
  1019. set_protocol_stall(udc, ep);
  1020. dev_err(dev, "Test_Packet: ep0 not mapped\n");
  1021. } else {
  1022. usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
  1023. usba_writel(udc, TST, USBA_TST_PKT_MODE);
  1024. copy_to_fifo(ep->fifo, test_packet_buffer,
  1025. sizeof(test_packet_buffer));
  1026. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1027. dev_info(dev, "Entering Test_Packet mode...\n");
  1028. }
  1029. break;
  1030. default:
  1031. dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
  1032. return -EINVAL;
  1033. }
  1034. return 0;
  1035. }
  1036. /* Avoid overly long expressions */
  1037. static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
  1038. {
  1039. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
  1040. return true;
  1041. return false;
  1042. }
  1043. static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
  1044. {
  1045. if (crq->wValue == __constant_cpu_to_le16(USB_DEVICE_TEST_MODE))
  1046. return true;
  1047. return false;
  1048. }
  1049. static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
  1050. {
  1051. if (crq->wValue == __constant_cpu_to_le16(USB_ENDPOINT_HALT))
  1052. return true;
  1053. return false;
  1054. }
  1055. static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
  1056. struct usb_ctrlrequest *crq)
  1057. {
  1058. int retval = 0;;
  1059. switch (crq->bRequest) {
  1060. case USB_REQ_GET_STATUS: {
  1061. u16 status;
  1062. if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
  1063. status = cpu_to_le16(udc->devstatus);
  1064. } else if (crq->bRequestType
  1065. == (USB_DIR_IN | USB_RECIP_INTERFACE)) {
  1066. status = __constant_cpu_to_le16(0);
  1067. } else if (crq->bRequestType
  1068. == (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
  1069. struct usba_ep *target;
  1070. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1071. if (!target)
  1072. goto stall;
  1073. status = 0;
  1074. if (is_stalled(udc, target))
  1075. status |= __constant_cpu_to_le16(1);
  1076. } else
  1077. goto delegate;
  1078. /* Write directly to the FIFO. No queueing is done. */
  1079. if (crq->wLength != __constant_cpu_to_le16(sizeof(status)))
  1080. goto stall;
  1081. ep->state = DATA_STAGE_IN;
  1082. __raw_writew(status, ep->fifo);
  1083. usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
  1084. break;
  1085. }
  1086. case USB_REQ_CLEAR_FEATURE: {
  1087. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1088. if (feature_is_dev_remote_wakeup(crq))
  1089. udc->devstatus
  1090. &= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
  1091. else
  1092. /* Can't CLEAR_FEATURE TEST_MODE */
  1093. goto stall;
  1094. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1095. struct usba_ep *target;
  1096. if (crq->wLength != __constant_cpu_to_le16(0)
  1097. || !feature_is_ep_halt(crq))
  1098. goto stall;
  1099. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1100. if (!target)
  1101. goto stall;
  1102. usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
  1103. if (target->index != 0)
  1104. usba_ep_writel(target, CLR_STA,
  1105. USBA_TOGGLE_CLR);
  1106. } else {
  1107. goto delegate;
  1108. }
  1109. send_status(udc, ep);
  1110. break;
  1111. }
  1112. case USB_REQ_SET_FEATURE: {
  1113. if (crq->bRequestType == USB_RECIP_DEVICE) {
  1114. if (feature_is_dev_test_mode(crq)) {
  1115. send_status(udc, ep);
  1116. ep->state = STATUS_STAGE_TEST;
  1117. udc->test_mode = le16_to_cpu(crq->wIndex);
  1118. return 0;
  1119. } else if (feature_is_dev_remote_wakeup(crq)) {
  1120. udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
  1121. } else {
  1122. goto stall;
  1123. }
  1124. } else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
  1125. struct usba_ep *target;
  1126. if (crq->wLength != __constant_cpu_to_le16(0)
  1127. || !feature_is_ep_halt(crq))
  1128. goto stall;
  1129. target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
  1130. if (!target)
  1131. goto stall;
  1132. usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
  1133. } else
  1134. goto delegate;
  1135. send_status(udc, ep);
  1136. break;
  1137. }
  1138. case USB_REQ_SET_ADDRESS:
  1139. if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
  1140. goto delegate;
  1141. set_address(udc, le16_to_cpu(crq->wValue));
  1142. send_status(udc, ep);
  1143. ep->state = STATUS_STAGE_ADDR;
  1144. break;
  1145. default:
  1146. delegate:
  1147. spin_unlock(&udc->lock);
  1148. retval = udc->driver->setup(&udc->gadget, crq);
  1149. spin_lock(&udc->lock);
  1150. }
  1151. return retval;
  1152. stall:
  1153. printk(KERN_ERR
  1154. "udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
  1155. "halting endpoint...\n",
  1156. ep->ep.name, crq->bRequestType, crq->bRequest,
  1157. le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
  1158. le16_to_cpu(crq->wLength));
  1159. set_protocol_stall(udc, ep);
  1160. return -1;
  1161. }
  1162. static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
  1163. {
  1164. struct usba_request *req;
  1165. u32 epstatus;
  1166. u32 epctrl;
  1167. restart:
  1168. epstatus = usba_ep_readl(ep, STA);
  1169. epctrl = usba_ep_readl(ep, CTL);
  1170. DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
  1171. ep->ep.name, ep->state, epstatus, epctrl);
  1172. req = NULL;
  1173. if (!list_empty(&ep->queue))
  1174. req = list_entry(ep->queue.next,
  1175. struct usba_request, queue);
  1176. if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1177. if (req->submitted)
  1178. next_fifo_transaction(ep, req);
  1179. else
  1180. submit_request(ep, req);
  1181. if (req->last_transaction) {
  1182. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1183. usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
  1184. }
  1185. goto restart;
  1186. }
  1187. if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
  1188. usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
  1189. switch (ep->state) {
  1190. case DATA_STAGE_IN:
  1191. usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
  1192. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1193. ep->state = STATUS_STAGE_OUT;
  1194. break;
  1195. case STATUS_STAGE_ADDR:
  1196. /* Activate our new address */
  1197. usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
  1198. | USBA_FADDR_EN));
  1199. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1200. ep->state = WAIT_FOR_SETUP;
  1201. break;
  1202. case STATUS_STAGE_IN:
  1203. if (req) {
  1204. list_del_init(&req->queue);
  1205. request_complete(ep, req, 0);
  1206. submit_next_request(ep);
  1207. }
  1208. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1209. ep->state = WAIT_FOR_SETUP;
  1210. break;
  1211. case STATUS_STAGE_TEST:
  1212. usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
  1213. ep->state = WAIT_FOR_SETUP;
  1214. if (do_test_mode(udc))
  1215. set_protocol_stall(udc, ep);
  1216. break;
  1217. default:
  1218. printk(KERN_ERR
  1219. "udc: %s: TXCOMP: Invalid endpoint state %d, "
  1220. "halting endpoint...\n",
  1221. ep->ep.name, ep->state);
  1222. set_protocol_stall(udc, ep);
  1223. break;
  1224. }
  1225. goto restart;
  1226. }
  1227. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1228. switch (ep->state) {
  1229. case STATUS_STAGE_OUT:
  1230. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1231. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1232. if (req) {
  1233. list_del_init(&req->queue);
  1234. request_complete(ep, req, 0);
  1235. }
  1236. ep->state = WAIT_FOR_SETUP;
  1237. break;
  1238. case DATA_STAGE_OUT:
  1239. receive_data(ep);
  1240. break;
  1241. default:
  1242. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1243. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1244. printk(KERN_ERR
  1245. "udc: %s: RXRDY: Invalid endpoint state %d, "
  1246. "halting endpoint...\n",
  1247. ep->ep.name, ep->state);
  1248. set_protocol_stall(udc, ep);
  1249. break;
  1250. }
  1251. goto restart;
  1252. }
  1253. if (epstatus & USBA_RX_SETUP) {
  1254. union {
  1255. struct usb_ctrlrequest crq;
  1256. unsigned long data[2];
  1257. } crq;
  1258. unsigned int pkt_len;
  1259. int ret;
  1260. if (ep->state != WAIT_FOR_SETUP) {
  1261. /*
  1262. * Didn't expect a SETUP packet at this
  1263. * point. Clean up any pending requests (which
  1264. * may be successful).
  1265. */
  1266. int status = -EPROTO;
  1267. /*
  1268. * RXRDY and TXCOMP are dropped when SETUP
  1269. * packets arrive. Just pretend we received
  1270. * the status packet.
  1271. */
  1272. if (ep->state == STATUS_STAGE_OUT
  1273. || ep->state == STATUS_STAGE_IN) {
  1274. usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
  1275. status = 0;
  1276. }
  1277. if (req) {
  1278. list_del_init(&req->queue);
  1279. request_complete(ep, req, status);
  1280. }
  1281. }
  1282. pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
  1283. DBG(DBG_HW, "Packet length: %u\n", pkt_len);
  1284. if (pkt_len != sizeof(crq)) {
  1285. printk(KERN_WARNING "udc: Invalid packet length %u "
  1286. "(expected %lu)\n", pkt_len, sizeof(crq));
  1287. set_protocol_stall(udc, ep);
  1288. return;
  1289. }
  1290. DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
  1291. copy_from_fifo(crq.data, ep->fifo, sizeof(crq));
  1292. /* Free up one bank in the FIFO so that we can
  1293. * generate or receive a reply right away. */
  1294. usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
  1295. /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
  1296. ep->state, crq.crq.bRequestType,
  1297. crq.crq.bRequest); */
  1298. if (crq.crq.bRequestType & USB_DIR_IN) {
  1299. /*
  1300. * The USB 2.0 spec states that "if wLength is
  1301. * zero, there is no data transfer phase."
  1302. * However, testusb #14 seems to actually
  1303. * expect a data phase even if wLength = 0...
  1304. */
  1305. ep->state = DATA_STAGE_IN;
  1306. } else {
  1307. if (crq.crq.wLength != __constant_cpu_to_le16(0))
  1308. ep->state = DATA_STAGE_OUT;
  1309. else
  1310. ep->state = STATUS_STAGE_IN;
  1311. }
  1312. ret = -1;
  1313. if (ep->index == 0)
  1314. ret = handle_ep0_setup(udc, ep, &crq.crq);
  1315. else {
  1316. spin_unlock(&udc->lock);
  1317. ret = udc->driver->setup(&udc->gadget, &crq.crq);
  1318. spin_lock(&udc->lock);
  1319. }
  1320. DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
  1321. crq.crq.bRequestType, crq.crq.bRequest,
  1322. le16_to_cpu(crq.crq.wLength), ep->state, ret);
  1323. if (ret < 0) {
  1324. /* Let the host know that we failed */
  1325. set_protocol_stall(udc, ep);
  1326. }
  1327. }
  1328. }
  1329. static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
  1330. {
  1331. struct usba_request *req;
  1332. u32 epstatus;
  1333. u32 epctrl;
  1334. epstatus = usba_ep_readl(ep, STA);
  1335. epctrl = usba_ep_readl(ep, CTL);
  1336. DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
  1337. while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
  1338. DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
  1339. if (list_empty(&ep->queue)) {
  1340. dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
  1341. usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
  1342. return;
  1343. }
  1344. req = list_entry(ep->queue.next, struct usba_request, queue);
  1345. if (req->using_dma) {
  1346. /* Send a zero-length packet */
  1347. usba_ep_writel(ep, SET_STA,
  1348. USBA_TX_PK_RDY);
  1349. usba_ep_writel(ep, CTL_DIS,
  1350. USBA_TX_PK_RDY);
  1351. list_del_init(&req->queue);
  1352. submit_next_request(ep);
  1353. request_complete(ep, req, 0);
  1354. } else {
  1355. if (req->submitted)
  1356. next_fifo_transaction(ep, req);
  1357. else
  1358. submit_request(ep, req);
  1359. if (req->last_transaction) {
  1360. list_del_init(&req->queue);
  1361. submit_next_request(ep);
  1362. request_complete(ep, req, 0);
  1363. }
  1364. }
  1365. epstatus = usba_ep_readl(ep, STA);
  1366. epctrl = usba_ep_readl(ep, CTL);
  1367. }
  1368. if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
  1369. DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
  1370. receive_data(ep);
  1371. usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
  1372. }
  1373. }
  1374. static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
  1375. {
  1376. struct usba_request *req;
  1377. u32 status, control, pending;
  1378. status = usba_dma_readl(ep, STATUS);
  1379. control = usba_dma_readl(ep, CONTROL);
  1380. #ifdef CONFIG_USB_GADGET_DEBUG_FS
  1381. ep->last_dma_status = status;
  1382. #endif
  1383. pending = status & control;
  1384. DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
  1385. if (status & USBA_DMA_CH_EN) {
  1386. dev_err(&udc->pdev->dev,
  1387. "DMA_CH_EN is set after transfer is finished!\n");
  1388. dev_err(&udc->pdev->dev,
  1389. "status=%#08x, pending=%#08x, control=%#08x\n",
  1390. status, pending, control);
  1391. /*
  1392. * try to pretend nothing happened. We might have to
  1393. * do something here...
  1394. */
  1395. }
  1396. if (list_empty(&ep->queue))
  1397. /* Might happen if a reset comes along at the right moment */
  1398. return;
  1399. if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
  1400. req = list_entry(ep->queue.next, struct usba_request, queue);
  1401. usba_update_req(ep, req, status);
  1402. list_del_init(&req->queue);
  1403. submit_next_request(ep);
  1404. request_complete(ep, req, 0);
  1405. }
  1406. }
  1407. static irqreturn_t usba_udc_irq(int irq, void *devid)
  1408. {
  1409. struct usba_udc *udc = devid;
  1410. u32 status;
  1411. u32 dma_status;
  1412. u32 ep_status;
  1413. spin_lock(&udc->lock);
  1414. status = usba_readl(udc, INT_STA);
  1415. DBG(DBG_INT, "irq, status=%#08x\n", status);
  1416. if (status & USBA_DET_SUSPEND) {
  1417. usba_writel(udc, INT_CLR, USBA_DET_SUSPEND);
  1418. DBG(DBG_BUS, "Suspend detected\n");
  1419. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1420. && udc->driver && udc->driver->suspend) {
  1421. spin_unlock(&udc->lock);
  1422. udc->driver->suspend(&udc->gadget);
  1423. spin_lock(&udc->lock);
  1424. }
  1425. }
  1426. if (status & USBA_WAKE_UP) {
  1427. usba_writel(udc, INT_CLR, USBA_WAKE_UP);
  1428. DBG(DBG_BUS, "Wake Up CPU detected\n");
  1429. }
  1430. if (status & USBA_END_OF_RESUME) {
  1431. usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
  1432. DBG(DBG_BUS, "Resume detected\n");
  1433. if (udc->gadget.speed != USB_SPEED_UNKNOWN
  1434. && udc->driver && udc->driver->resume) {
  1435. spin_unlock(&udc->lock);
  1436. udc->driver->resume(&udc->gadget);
  1437. spin_lock(&udc->lock);
  1438. }
  1439. }
  1440. dma_status = USBA_BFEXT(DMA_INT, status);
  1441. if (dma_status) {
  1442. int i;
  1443. for (i = 1; i < USBA_NR_ENDPOINTS; i++)
  1444. if (dma_status & (1 << i))
  1445. usba_dma_irq(udc, &usba_ep[i]);
  1446. }
  1447. ep_status = USBA_BFEXT(EPT_INT, status);
  1448. if (ep_status) {
  1449. int i;
  1450. for (i = 0; i < USBA_NR_ENDPOINTS; i++)
  1451. if (ep_status & (1 << i)) {
  1452. if (ep_is_control(&usba_ep[i]))
  1453. usba_control_irq(udc, &usba_ep[i]);
  1454. else
  1455. usba_ep_irq(udc, &usba_ep[i]);
  1456. }
  1457. }
  1458. if (status & USBA_END_OF_RESET) {
  1459. struct usba_ep *ep0;
  1460. usba_writel(udc, INT_CLR, USBA_END_OF_RESET);
  1461. reset_all_endpoints(udc);
  1462. if (status & USBA_HIGH_SPEED) {
  1463. DBG(DBG_BUS, "High-speed bus reset detected\n");
  1464. udc->gadget.speed = USB_SPEED_HIGH;
  1465. } else {
  1466. DBG(DBG_BUS, "Full-speed bus reset detected\n");
  1467. udc->gadget.speed = USB_SPEED_FULL;
  1468. }
  1469. ep0 = &usba_ep[0];
  1470. ep0->desc = &usba_ep0_desc;
  1471. ep0->state = WAIT_FOR_SETUP;
  1472. usba_ep_writel(ep0, CFG,
  1473. (USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
  1474. | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
  1475. | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
  1476. usba_ep_writel(ep0, CTL_ENB,
  1477. USBA_EPT_ENABLE | USBA_RX_SETUP);
  1478. usba_writel(udc, INT_ENB,
  1479. (usba_readl(udc, INT_ENB)
  1480. | USBA_BF(EPT_INT, 1)
  1481. | USBA_DET_SUSPEND
  1482. | USBA_END_OF_RESUME));
  1483. if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
  1484. dev_warn(&udc->pdev->dev,
  1485. "WARNING: EP0 configuration is invalid!\n");
  1486. }
  1487. spin_unlock(&udc->lock);
  1488. return IRQ_HANDLED;
  1489. }
  1490. static irqreturn_t usba_vbus_irq(int irq, void *devid)
  1491. {
  1492. struct usba_udc *udc = devid;
  1493. int vbus;
  1494. /* debounce */
  1495. udelay(10);
  1496. spin_lock(&udc->lock);
  1497. /* May happen if Vbus pin toggles during probe() */
  1498. if (!udc->driver)
  1499. goto out;
  1500. vbus = gpio_get_value(udc->vbus_pin);
  1501. if (vbus != udc->vbus_prev) {
  1502. if (vbus) {
  1503. usba_writel(udc, CTRL, USBA_EN_USBA);
  1504. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1505. } else {
  1506. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1507. reset_all_endpoints(udc);
  1508. usba_writel(udc, CTRL, 0);
  1509. spin_unlock(&udc->lock);
  1510. udc->driver->disconnect(&udc->gadget);
  1511. spin_lock(&udc->lock);
  1512. }
  1513. udc->vbus_prev = vbus;
  1514. }
  1515. out:
  1516. spin_unlock(&udc->lock);
  1517. return IRQ_HANDLED;
  1518. }
  1519. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1520. {
  1521. struct usba_udc *udc = &the_udc;
  1522. unsigned long flags;
  1523. int ret;
  1524. if (!udc->pdev)
  1525. return -ENODEV;
  1526. spin_lock_irqsave(&udc->lock, flags);
  1527. if (udc->driver) {
  1528. spin_unlock_irqrestore(&udc->lock, flags);
  1529. return -EBUSY;
  1530. }
  1531. udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
  1532. udc->driver = driver;
  1533. udc->gadget.dev.driver = &driver->driver;
  1534. spin_unlock_irqrestore(&udc->lock, flags);
  1535. clk_enable(udc->pclk);
  1536. clk_enable(udc->hclk);
  1537. ret = driver->bind(&udc->gadget);
  1538. if (ret) {
  1539. DBG(DBG_ERR, "Could not bind to driver %s: error %d\n",
  1540. driver->driver.name, ret);
  1541. goto err_driver_bind;
  1542. }
  1543. DBG(DBG_GADGET, "registered driver `%s'\n", driver->driver.name);
  1544. udc->vbus_prev = 0;
  1545. if (udc->vbus_pin != -1)
  1546. enable_irq(gpio_to_irq(udc->vbus_pin));
  1547. /* If Vbus is present, enable the controller and wait for reset */
  1548. spin_lock_irqsave(&udc->lock, flags);
  1549. if (vbus_is_present(udc) && udc->vbus_prev == 0) {
  1550. usba_writel(udc, CTRL, USBA_EN_USBA);
  1551. usba_writel(udc, INT_ENB, USBA_END_OF_RESET);
  1552. }
  1553. spin_unlock_irqrestore(&udc->lock, flags);
  1554. return 0;
  1555. err_driver_bind:
  1556. udc->driver = NULL;
  1557. udc->gadget.dev.driver = NULL;
  1558. return ret;
  1559. }
  1560. EXPORT_SYMBOL(usb_gadget_register_driver);
  1561. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1562. {
  1563. struct usba_udc *udc = &the_udc;
  1564. unsigned long flags;
  1565. if (!udc->pdev)
  1566. return -ENODEV;
  1567. if (driver != udc->driver)
  1568. return -EINVAL;
  1569. if (udc->vbus_pin != -1)
  1570. disable_irq(gpio_to_irq(udc->vbus_pin));
  1571. spin_lock_irqsave(&udc->lock, flags);
  1572. udc->gadget.speed = USB_SPEED_UNKNOWN;
  1573. reset_all_endpoints(udc);
  1574. spin_unlock_irqrestore(&udc->lock, flags);
  1575. /* This will also disable the DP pullup */
  1576. usba_writel(udc, CTRL, 0);
  1577. driver->unbind(&udc->gadget);
  1578. udc->gadget.dev.driver = NULL;
  1579. udc->driver = NULL;
  1580. clk_disable(udc->hclk);
  1581. clk_disable(udc->pclk);
  1582. DBG(DBG_GADGET, "unregistered driver `%s'\n", driver->driver.name);
  1583. return 0;
  1584. }
  1585. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1586. static int __init usba_udc_probe(struct platform_device *pdev)
  1587. {
  1588. struct usba_platform_data *pdata = pdev->dev.platform_data;
  1589. struct resource *regs, *fifo;
  1590. struct clk *pclk, *hclk;
  1591. struct usba_udc *udc = &the_udc;
  1592. int irq, ret, i;
  1593. regs = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
  1594. fifo = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
  1595. if (!regs || !fifo)
  1596. return -ENXIO;
  1597. irq = platform_get_irq(pdev, 0);
  1598. if (irq < 0)
  1599. return irq;
  1600. pclk = clk_get(&pdev->dev, "pclk");
  1601. if (IS_ERR(pclk))
  1602. return PTR_ERR(pclk);
  1603. hclk = clk_get(&pdev->dev, "hclk");
  1604. if (IS_ERR(hclk)) {
  1605. ret = PTR_ERR(hclk);
  1606. goto err_get_hclk;
  1607. }
  1608. udc->pdev = pdev;
  1609. udc->pclk = pclk;
  1610. udc->hclk = hclk;
  1611. udc->vbus_pin = -1;
  1612. ret = -ENOMEM;
  1613. udc->regs = ioremap(regs->start, regs->end - regs->start + 1);
  1614. if (!udc->regs) {
  1615. dev_err(&pdev->dev, "Unable to map I/O memory, aborting.\n");
  1616. goto err_map_regs;
  1617. }
  1618. dev_info(&pdev->dev, "MMIO registers at 0x%08lx mapped at %p\n",
  1619. (unsigned long)regs->start, udc->regs);
  1620. udc->fifo = ioremap(fifo->start, fifo->end - fifo->start + 1);
  1621. if (!udc->fifo) {
  1622. dev_err(&pdev->dev, "Unable to map FIFO, aborting.\n");
  1623. goto err_map_fifo;
  1624. }
  1625. dev_info(&pdev->dev, "FIFO at 0x%08lx mapped at %p\n",
  1626. (unsigned long)fifo->start, udc->fifo);
  1627. device_initialize(&udc->gadget.dev);
  1628. udc->gadget.dev.parent = &pdev->dev;
  1629. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1630. platform_set_drvdata(pdev, udc);
  1631. /* Make sure we start from a clean slate */
  1632. clk_enable(pclk);
  1633. usba_writel(udc, CTRL, 0);
  1634. clk_disable(pclk);
  1635. INIT_LIST_HEAD(&usba_ep[0].ep.ep_list);
  1636. usba_ep[0].ep_regs = udc->regs + USBA_EPT_BASE(0);
  1637. usba_ep[0].dma_regs = udc->regs + USBA_DMA_BASE(0);
  1638. usba_ep[0].fifo = udc->fifo + USBA_FIFO_BASE(0);
  1639. for (i = 1; i < ARRAY_SIZE(usba_ep); i++) {
  1640. struct usba_ep *ep = &usba_ep[i];
  1641. ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
  1642. ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
  1643. ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
  1644. list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
  1645. }
  1646. ret = request_irq(irq, usba_udc_irq, 0, "atmel_usba_udc", udc);
  1647. if (ret) {
  1648. dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
  1649. irq, ret);
  1650. goto err_request_irq;
  1651. }
  1652. udc->irq = irq;
  1653. ret = device_add(&udc->gadget.dev);
  1654. if (ret) {
  1655. dev_dbg(&pdev->dev, "Could not add gadget: %d\n", ret);
  1656. goto err_device_add;
  1657. }
  1658. if (pdata && pdata->vbus_pin != GPIO_PIN_NONE) {
  1659. if (!gpio_request(pdata->vbus_pin, "atmel_usba_udc")) {
  1660. udc->vbus_pin = pdata->vbus_pin;
  1661. ret = request_irq(gpio_to_irq(udc->vbus_pin),
  1662. usba_vbus_irq, 0,
  1663. "atmel_usba_udc", udc);
  1664. if (ret) {
  1665. gpio_free(udc->vbus_pin);
  1666. udc->vbus_pin = -1;
  1667. dev_warn(&udc->pdev->dev,
  1668. "failed to request vbus irq; "
  1669. "assuming always on\n");
  1670. } else {
  1671. disable_irq(gpio_to_irq(udc->vbus_pin));
  1672. }
  1673. }
  1674. }
  1675. usba_init_debugfs(udc);
  1676. for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
  1677. usba_ep_init_debugfs(udc, &usba_ep[i]);
  1678. return 0;
  1679. err_device_add:
  1680. free_irq(irq, udc);
  1681. err_request_irq:
  1682. iounmap(udc->fifo);
  1683. err_map_fifo:
  1684. iounmap(udc->regs);
  1685. err_map_regs:
  1686. clk_put(hclk);
  1687. err_get_hclk:
  1688. clk_put(pclk);
  1689. platform_set_drvdata(pdev, NULL);
  1690. return ret;
  1691. }
  1692. static int __exit usba_udc_remove(struct platform_device *pdev)
  1693. {
  1694. struct usba_udc *udc;
  1695. int i;
  1696. udc = platform_get_drvdata(pdev);
  1697. for (i = 1; i < ARRAY_SIZE(usba_ep); i++)
  1698. usba_ep_cleanup_debugfs(&usba_ep[i]);
  1699. usba_cleanup_debugfs(udc);
  1700. if (udc->vbus_pin != -1)
  1701. gpio_free(udc->vbus_pin);
  1702. free_irq(udc->irq, udc);
  1703. iounmap(udc->fifo);
  1704. iounmap(udc->regs);
  1705. clk_put(udc->hclk);
  1706. clk_put(udc->pclk);
  1707. device_unregister(&udc->gadget.dev);
  1708. return 0;
  1709. }
  1710. static struct platform_driver udc_driver = {
  1711. .remove = __exit_p(usba_udc_remove),
  1712. .driver = {
  1713. .name = "atmel_usba_udc",
  1714. },
  1715. };
  1716. static int __init udc_init(void)
  1717. {
  1718. return platform_driver_probe(&udc_driver, usba_udc_probe);
  1719. }
  1720. module_init(udc_init);
  1721. static void __exit udc_exit(void)
  1722. {
  1723. platform_driver_unregister(&udc_driver);
  1724. }
  1725. module_exit(udc_exit);
  1726. MODULE_DESCRIPTION("Atmel USBA UDC driver");
  1727. MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
  1728. MODULE_LICENSE("GPL");