pci.c 20 KB

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  1. /*
  2. * Sonics Silicon Backplane PCI-Hostbus related functions.
  3. *
  4. * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
  5. * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
  6. * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
  7. * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
  8. * Copyright (C) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  9. *
  10. * Derived from the Broadcom 4400 device driver.
  11. * Copyright (C) 2002 David S. Miller (davem@redhat.com)
  12. * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
  13. * Copyright (C) 2006 Broadcom Corporation.
  14. *
  15. * Licensed under the GNU/GPL. See COPYING for details.
  16. */
  17. #include <linux/ssb/ssb.h>
  18. #include <linux/ssb/ssb_regs.h>
  19. #include <linux/pci.h>
  20. #include <linux/delay.h>
  21. #include "ssb_private.h"
  22. /* Define the following to 1 to enable a printk on each coreswitch. */
  23. #define SSB_VERBOSE_PCICORESWITCH_DEBUG 0
  24. /* Lowlevel coreswitching */
  25. int ssb_pci_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
  26. {
  27. int err;
  28. int attempts = 0;
  29. u32 cur_core;
  30. while (1) {
  31. err = pci_write_config_dword(bus->host_pci, SSB_BAR0_WIN,
  32. (coreidx * SSB_CORE_SIZE)
  33. + SSB_ENUM_BASE);
  34. if (err)
  35. goto error;
  36. err = pci_read_config_dword(bus->host_pci, SSB_BAR0_WIN,
  37. &cur_core);
  38. if (err)
  39. goto error;
  40. cur_core = (cur_core - SSB_ENUM_BASE)
  41. / SSB_CORE_SIZE;
  42. if (cur_core == coreidx)
  43. break;
  44. if (attempts++ > SSB_BAR0_MAX_RETRIES)
  45. goto error;
  46. udelay(10);
  47. }
  48. return 0;
  49. error:
  50. ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
  51. return -ENODEV;
  52. }
  53. int ssb_pci_switch_core(struct ssb_bus *bus,
  54. struct ssb_device *dev)
  55. {
  56. int err;
  57. unsigned long flags;
  58. #if SSB_VERBOSE_PCICORESWITCH_DEBUG
  59. ssb_printk(KERN_INFO PFX
  60. "Switching to %s core, index %d\n",
  61. ssb_core_name(dev->id.coreid),
  62. dev->core_index);
  63. #endif
  64. spin_lock_irqsave(&bus->bar_lock, flags);
  65. err = ssb_pci_switch_coreidx(bus, dev->core_index);
  66. if (!err)
  67. bus->mapped_device = dev;
  68. spin_unlock_irqrestore(&bus->bar_lock, flags);
  69. return err;
  70. }
  71. /* Enable/disable the on board crystal oscillator and/or PLL. */
  72. int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
  73. {
  74. int err;
  75. u32 in, out, outenable;
  76. u16 pci_status;
  77. if (bus->bustype != SSB_BUSTYPE_PCI)
  78. return 0;
  79. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
  80. if (err)
  81. goto err_pci;
  82. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
  83. if (err)
  84. goto err_pci;
  85. err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
  86. if (err)
  87. goto err_pci;
  88. outenable |= what;
  89. if (turn_on) {
  90. /* Avoid glitching the clock if GPRS is already using it.
  91. * We can't actually read the state of the PLLPD so we infer it
  92. * by the value of XTAL_PU which *is* readable via gpioin.
  93. */
  94. if (!(in & SSB_GPIO_XTAL)) {
  95. if (what & SSB_GPIO_XTAL) {
  96. /* Turn the crystal on */
  97. out |= SSB_GPIO_XTAL;
  98. if (what & SSB_GPIO_PLL)
  99. out |= SSB_GPIO_PLL;
  100. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  101. if (err)
  102. goto err_pci;
  103. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
  104. outenable);
  105. if (err)
  106. goto err_pci;
  107. msleep(1);
  108. }
  109. if (what & SSB_GPIO_PLL) {
  110. /* Turn the PLL on */
  111. out &= ~SSB_GPIO_PLL;
  112. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  113. if (err)
  114. goto err_pci;
  115. msleep(5);
  116. }
  117. }
  118. err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
  119. if (err)
  120. goto err_pci;
  121. pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
  122. err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
  123. if (err)
  124. goto err_pci;
  125. } else {
  126. if (what & SSB_GPIO_XTAL) {
  127. /* Turn the crystal off */
  128. out &= ~SSB_GPIO_XTAL;
  129. }
  130. if (what & SSB_GPIO_PLL) {
  131. /* Turn the PLL off */
  132. out |= SSB_GPIO_PLL;
  133. }
  134. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
  135. if (err)
  136. goto err_pci;
  137. err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
  138. if (err)
  139. goto err_pci;
  140. }
  141. out:
  142. return err;
  143. err_pci:
  144. printk(KERN_ERR PFX "Error: ssb_pci_xtal() could not access PCI config space!\n");
  145. err = -EBUSY;
  146. goto out;
  147. }
  148. /* Get the word-offset for a SSB_SPROM_XXX define. */
  149. #define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
  150. /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
  151. #define SPEX(_outvar, _offset, _mask, _shift) \
  152. out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
  153. static inline u8 ssb_crc8(u8 crc, u8 data)
  154. {
  155. /* Polynomial: x^8 + x^7 + x^6 + x^4 + x^2 + 1 */
  156. static const u8 t[] = {
  157. 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
  158. 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
  159. 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
  160. 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
  161. 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
  162. 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
  163. 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
  164. 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
  165. 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
  166. 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
  167. 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
  168. 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
  169. 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
  170. 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
  171. 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
  172. 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
  173. 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
  174. 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
  175. 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
  176. 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
  177. 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
  178. 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
  179. 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
  180. 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
  181. 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
  182. 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
  183. 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
  184. 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
  185. 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
  186. 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
  187. 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
  188. 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
  189. };
  190. return t[crc ^ data];
  191. }
  192. static u8 ssb_sprom_crc(const u16 *sprom)
  193. {
  194. int word;
  195. u8 crc = 0xFF;
  196. for (word = 0; word < SSB_SPROMSIZE_WORDS - 1; word++) {
  197. crc = ssb_crc8(crc, sprom[word] & 0x00FF);
  198. crc = ssb_crc8(crc, (sprom[word] & 0xFF00) >> 8);
  199. }
  200. crc = ssb_crc8(crc, sprom[SPOFF(SSB_SPROM_REVISION)] & 0x00FF);
  201. crc ^= 0xFF;
  202. return crc;
  203. }
  204. static int sprom_check_crc(const u16 *sprom)
  205. {
  206. u8 crc;
  207. u8 expected_crc;
  208. u16 tmp;
  209. crc = ssb_sprom_crc(sprom);
  210. tmp = sprom[SPOFF(SSB_SPROM_REVISION)] & SSB_SPROM_REVISION_CRC;
  211. expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
  212. if (crc != expected_crc)
  213. return -EPROTO;
  214. return 0;
  215. }
  216. static void sprom_do_read(struct ssb_bus *bus, u16 *sprom)
  217. {
  218. int i;
  219. for (i = 0; i < SSB_SPROMSIZE_WORDS; i++)
  220. sprom[i] = readw(bus->mmio + SSB_SPROM_BASE + (i * 2));
  221. }
  222. static int sprom_do_write(struct ssb_bus *bus, const u16 *sprom)
  223. {
  224. struct pci_dev *pdev = bus->host_pci;
  225. int i, err;
  226. u32 spromctl;
  227. ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
  228. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  229. if (err)
  230. goto err_ctlreg;
  231. spromctl |= SSB_SPROMCTL_WE;
  232. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  233. if (err)
  234. goto err_ctlreg;
  235. ssb_printk(KERN_NOTICE PFX "[ 0%%");
  236. msleep(500);
  237. for (i = 0; i < SSB_SPROMSIZE_WORDS; i++) {
  238. if (i == SSB_SPROMSIZE_WORDS / 4)
  239. ssb_printk("25%%");
  240. else if (i == SSB_SPROMSIZE_WORDS / 2)
  241. ssb_printk("50%%");
  242. else if (i == (SSB_SPROMSIZE_WORDS / 4) * 3)
  243. ssb_printk("75%%");
  244. else if (i % 2)
  245. ssb_printk(".");
  246. writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
  247. mmiowb();
  248. msleep(20);
  249. }
  250. err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
  251. if (err)
  252. goto err_ctlreg;
  253. spromctl &= ~SSB_SPROMCTL_WE;
  254. err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
  255. if (err)
  256. goto err_ctlreg;
  257. msleep(500);
  258. ssb_printk("100%% ]\n");
  259. ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
  260. return 0;
  261. err_ctlreg:
  262. ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
  263. return err;
  264. }
  265. static void sprom_extract_r1(struct ssb_sprom_r1 *out, const u16 *in)
  266. {
  267. int i;
  268. u16 v;
  269. SPEX(pci_spid, SSB_SPROM1_SPID, 0xFFFF, 0);
  270. SPEX(pci_svid, SSB_SPROM1_SVID, 0xFFFF, 0);
  271. SPEX(pci_pid, SSB_SPROM1_PID, 0xFFFF, 0);
  272. for (i = 0; i < 3; i++) {
  273. v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
  274. *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
  275. }
  276. for (i = 0; i < 3; i++) {
  277. v = in[SPOFF(SSB_SPROM1_ET0MAC) + i];
  278. *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
  279. }
  280. for (i = 0; i < 3; i++) {
  281. v = in[SPOFF(SSB_SPROM1_ET1MAC) + i];
  282. *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
  283. }
  284. SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
  285. SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
  286. SSB_SPROM1_ETHPHY_ET1A_SHIFT);
  287. SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
  288. SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
  289. SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
  290. SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
  291. SSB_SPROM1_BINF_CCODE_SHIFT);
  292. SPEX(antenna_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
  293. SSB_SPROM1_BINF_ANTA_SHIFT);
  294. SPEX(antenna_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
  295. SSB_SPROM1_BINF_ANTBG_SHIFT);
  296. SPEX(pa0b0, SSB_SPROM1_PA0B0, 0xFFFF, 0);
  297. SPEX(pa0b1, SSB_SPROM1_PA0B1, 0xFFFF, 0);
  298. SPEX(pa0b2, SSB_SPROM1_PA0B2, 0xFFFF, 0);
  299. SPEX(pa1b0, SSB_SPROM1_PA1B0, 0xFFFF, 0);
  300. SPEX(pa1b1, SSB_SPROM1_PA1B1, 0xFFFF, 0);
  301. SPEX(pa1b2, SSB_SPROM1_PA1B2, 0xFFFF, 0);
  302. SPEX(gpio0, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P0, 0);
  303. SPEX(gpio1, SSB_SPROM1_GPIOA, SSB_SPROM1_GPIOA_P1,
  304. SSB_SPROM1_GPIOA_P1_SHIFT);
  305. SPEX(gpio2, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P2, 0);
  306. SPEX(gpio3, SSB_SPROM1_GPIOB, SSB_SPROM1_GPIOB_P3,
  307. SSB_SPROM1_GPIOB_P3_SHIFT);
  308. SPEX(maxpwr_a, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_A,
  309. SSB_SPROM1_MAXPWR_A_SHIFT);
  310. SPEX(maxpwr_bg, SSB_SPROM1_MAXPWR, SSB_SPROM1_MAXPWR_BG, 0);
  311. SPEX(itssi_a, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_A,
  312. SSB_SPROM1_ITSSI_A_SHIFT);
  313. SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
  314. SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
  315. SPEX(antenna_gain_a, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_A, 0);
  316. SPEX(antenna_gain_bg, SSB_SPROM1_AGAIN, SSB_SPROM1_AGAIN_BG,
  317. SSB_SPROM1_AGAIN_BG_SHIFT);
  318. for (i = 0; i < 4; i++) {
  319. v = in[SPOFF(SSB_SPROM1_OEM) + i];
  320. *(((__le16 *)out->oem) + i) = cpu_to_le16(v);
  321. }
  322. }
  323. static void sprom_extract_r2(struct ssb_sprom_r2 *out, const u16 *in)
  324. {
  325. int i;
  326. u16 v;
  327. SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
  328. SPEX(maxpwr_a_hi, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
  329. SPEX(maxpwr_a_lo, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
  330. SSB_SPROM2_MAXP_A_LO_SHIFT);
  331. SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
  332. SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
  333. SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
  334. SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
  335. SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
  336. SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
  337. SPEX(ofdm_pwr_off, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
  338. for (i = 0; i < 4; i++) {
  339. v = in[SPOFF(SSB_SPROM2_CCODE) + i];
  340. *(((__le16 *)out->country_str) + i) = cpu_to_le16(v);
  341. }
  342. }
  343. static void sprom_extract_r3(struct ssb_sprom_r3 *out, const u16 *in)
  344. {
  345. out->ofdmapo = (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0xFF00) >> 8;
  346. out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 0] & 0x00FF) << 8;
  347. out->ofdmapo <<= 16;
  348. out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0xFF00) >> 8;
  349. out->ofdmapo |= (in[SPOFF(SSB_SPROM3_OFDMAPO) + 1] & 0x00FF) << 8;
  350. out->ofdmalpo = (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0xFF00) >> 8;
  351. out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 0] & 0x00FF) << 8;
  352. out->ofdmalpo <<= 16;
  353. out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0xFF00) >> 8;
  354. out->ofdmalpo |= (in[SPOFF(SSB_SPROM3_OFDMALPO) + 1] & 0x00FF) << 8;
  355. out->ofdmahpo = (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0xFF00) >> 8;
  356. out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 0] & 0x00FF) << 8;
  357. out->ofdmahpo <<= 16;
  358. out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0xFF00) >> 8;
  359. out->ofdmahpo |= (in[SPOFF(SSB_SPROM3_OFDMAHPO) + 1] & 0x00FF) << 8;
  360. SPEX(gpioldc_on_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_ON,
  361. SSB_SPROM3_GPIOLDC_ON_SHIFT);
  362. SPEX(gpioldc_off_cnt, SSB_SPROM3_GPIOLDC, SSB_SPROM3_GPIOLDC_OFF,
  363. SSB_SPROM3_GPIOLDC_OFF_SHIFT);
  364. SPEX(cckpo_1M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_1M, 0);
  365. SPEX(cckpo_2M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_2M,
  366. SSB_SPROM3_CCKPO_2M_SHIFT);
  367. SPEX(cckpo_55M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_55M,
  368. SSB_SPROM3_CCKPO_55M_SHIFT);
  369. SPEX(cckpo_11M, SSB_SPROM3_CCKPO, SSB_SPROM3_CCKPO_11M,
  370. SSB_SPROM3_CCKPO_11M_SHIFT);
  371. out->ofdmgpo = (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0xFF00) >> 8;
  372. out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 0] & 0x00FF) << 8;
  373. out->ofdmgpo <<= 16;
  374. out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0xFF00) >> 8;
  375. out->ofdmgpo |= (in[SPOFF(SSB_SPROM3_OFDMGPO) + 1] & 0x00FF) << 8;
  376. }
  377. static int sprom_extract(struct ssb_bus *bus,
  378. struct ssb_sprom *out, const u16 *in)
  379. {
  380. memset(out, 0, sizeof(*out));
  381. SPEX(revision, SSB_SPROM_REVISION, SSB_SPROM_REVISION_REV, 0);
  382. SPEX(crc, SSB_SPROM_REVISION, SSB_SPROM_REVISION_CRC,
  383. SSB_SPROM_REVISION_CRC_SHIFT);
  384. if ((bus->chip_id & 0xFF00) == 0x4400) {
  385. /* Workaround: The BCM44XX chip has a stupid revision
  386. * number stored in the SPROM.
  387. * Always extract r1. */
  388. sprom_extract_r1(&out->r1, in);
  389. } else {
  390. if (out->revision == 0)
  391. goto unsupported;
  392. if (out->revision >= 1 && out->revision <= 3)
  393. sprom_extract_r1(&out->r1, in);
  394. if (out->revision >= 2 && out->revision <= 3)
  395. sprom_extract_r2(&out->r2, in);
  396. if (out->revision == 3)
  397. sprom_extract_r3(&out->r3, in);
  398. if (out->revision >= 4)
  399. goto unsupported;
  400. }
  401. return 0;
  402. unsupported:
  403. ssb_printk(KERN_WARNING PFX "Unsupported SPROM revision %d "
  404. "detected. Will extract v1\n", out->revision);
  405. sprom_extract_r1(&out->r1, in);
  406. return 0;
  407. }
  408. static int ssb_pci_sprom_get(struct ssb_bus *bus,
  409. struct ssb_sprom *sprom)
  410. {
  411. int err = -ENOMEM;
  412. u16 *buf;
  413. buf = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
  414. if (!buf)
  415. goto out;
  416. sprom_do_read(bus, buf);
  417. err = sprom_check_crc(buf);
  418. if (err) {
  419. ssb_printk(KERN_WARNING PFX
  420. "WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
  421. }
  422. err = sprom_extract(bus, sprom, buf);
  423. kfree(buf);
  424. out:
  425. return err;
  426. }
  427. static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
  428. struct ssb_boardinfo *bi)
  429. {
  430. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
  431. &bi->vendor);
  432. pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
  433. &bi->type);
  434. pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
  435. &bi->rev);
  436. }
  437. int ssb_pci_get_invariants(struct ssb_bus *bus,
  438. struct ssb_init_invariants *iv)
  439. {
  440. int err;
  441. err = ssb_pci_sprom_get(bus, &iv->sprom);
  442. if (err)
  443. goto out;
  444. ssb_pci_get_boardinfo(bus, &iv->boardinfo);
  445. out:
  446. return err;
  447. }
  448. #ifdef CONFIG_SSB_DEBUG
  449. static int ssb_pci_assert_buspower(struct ssb_bus *bus)
  450. {
  451. if (likely(bus->powered_up))
  452. return 0;
  453. printk(KERN_ERR PFX "FATAL ERROR: Bus powered down "
  454. "while accessing PCI MMIO space\n");
  455. if (bus->power_warn_count <= 10) {
  456. bus->power_warn_count++;
  457. dump_stack();
  458. }
  459. return -ENODEV;
  460. }
  461. #else /* DEBUG */
  462. static inline int ssb_pci_assert_buspower(struct ssb_bus *bus)
  463. {
  464. return 0;
  465. }
  466. #endif /* DEBUG */
  467. static u16 ssb_pci_read16(struct ssb_device *dev, u16 offset)
  468. {
  469. struct ssb_bus *bus = dev->bus;
  470. if (unlikely(ssb_pci_assert_buspower(bus)))
  471. return 0xFFFF;
  472. if (unlikely(bus->mapped_device != dev)) {
  473. if (unlikely(ssb_pci_switch_core(bus, dev)))
  474. return 0xFFFF;
  475. }
  476. return ioread16(bus->mmio + offset);
  477. }
  478. static u32 ssb_pci_read32(struct ssb_device *dev, u16 offset)
  479. {
  480. struct ssb_bus *bus = dev->bus;
  481. if (unlikely(ssb_pci_assert_buspower(bus)))
  482. return 0xFFFFFFFF;
  483. if (unlikely(bus->mapped_device != dev)) {
  484. if (unlikely(ssb_pci_switch_core(bus, dev)))
  485. return 0xFFFFFFFF;
  486. }
  487. return ioread32(bus->mmio + offset);
  488. }
  489. static void ssb_pci_write16(struct ssb_device *dev, u16 offset, u16 value)
  490. {
  491. struct ssb_bus *bus = dev->bus;
  492. if (unlikely(ssb_pci_assert_buspower(bus)))
  493. return;
  494. if (unlikely(bus->mapped_device != dev)) {
  495. if (unlikely(ssb_pci_switch_core(bus, dev)))
  496. return;
  497. }
  498. iowrite16(value, bus->mmio + offset);
  499. }
  500. static void ssb_pci_write32(struct ssb_device *dev, u16 offset, u32 value)
  501. {
  502. struct ssb_bus *bus = dev->bus;
  503. if (unlikely(ssb_pci_assert_buspower(bus)))
  504. return;
  505. if (unlikely(bus->mapped_device != dev)) {
  506. if (unlikely(ssb_pci_switch_core(bus, dev)))
  507. return;
  508. }
  509. iowrite32(value, bus->mmio + offset);
  510. }
  511. /* Not "static", as it's used in main.c */
  512. const struct ssb_bus_ops ssb_pci_ops = {
  513. .read16 = ssb_pci_read16,
  514. .read32 = ssb_pci_read32,
  515. .write16 = ssb_pci_write16,
  516. .write32 = ssb_pci_write32,
  517. };
  518. static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len)
  519. {
  520. int i, pos = 0;
  521. for (i = 0; i < SSB_SPROMSIZE_WORDS; i++) {
  522. pos += snprintf(buf + pos, buf_len - pos - 1,
  523. "%04X", swab16(sprom[i]) & 0xFFFF);
  524. }
  525. pos += snprintf(buf + pos, buf_len - pos - 1, "\n");
  526. return pos + 1;
  527. }
  528. static int hex2sprom(u16 *sprom, const char *dump, size_t len)
  529. {
  530. char tmp[5] = { 0 };
  531. int cnt = 0;
  532. unsigned long parsed;
  533. if (len < SSB_SPROMSIZE_BYTES * 2)
  534. return -EINVAL;
  535. while (cnt < SSB_SPROMSIZE_WORDS) {
  536. memcpy(tmp, dump, 4);
  537. dump += 4;
  538. parsed = simple_strtoul(tmp, NULL, 16);
  539. sprom[cnt++] = swab16((u16)parsed);
  540. }
  541. return 0;
  542. }
  543. static ssize_t ssb_pci_attr_sprom_show(struct device *pcidev,
  544. struct device_attribute *attr,
  545. char *buf)
  546. {
  547. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  548. struct ssb_bus *bus;
  549. u16 *sprom;
  550. int err = -ENODEV;
  551. ssize_t count = 0;
  552. bus = ssb_pci_dev_to_bus(pdev);
  553. if (!bus)
  554. goto out;
  555. err = -ENOMEM;
  556. sprom = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
  557. if (!sprom)
  558. goto out;
  559. /* Use interruptible locking, as the SPROM write might
  560. * be holding the lock for several seconds. So allow userspace
  561. * to cancel operation. */
  562. err = -ERESTARTSYS;
  563. if (mutex_lock_interruptible(&bus->pci_sprom_mutex))
  564. goto out_kfree;
  565. sprom_do_read(bus, sprom);
  566. mutex_unlock(&bus->pci_sprom_mutex);
  567. count = sprom2hex(sprom, buf, PAGE_SIZE);
  568. err = 0;
  569. out_kfree:
  570. kfree(sprom);
  571. out:
  572. return err ? err : count;
  573. }
  574. static ssize_t ssb_pci_attr_sprom_store(struct device *pcidev,
  575. struct device_attribute *attr,
  576. const char *buf, size_t count)
  577. {
  578. struct pci_dev *pdev = container_of(pcidev, struct pci_dev, dev);
  579. struct ssb_bus *bus;
  580. u16 *sprom;
  581. int res = 0, err = -ENODEV;
  582. bus = ssb_pci_dev_to_bus(pdev);
  583. if (!bus)
  584. goto out;
  585. err = -ENOMEM;
  586. sprom = kcalloc(SSB_SPROMSIZE_WORDS, sizeof(u16), GFP_KERNEL);
  587. if (!sprom)
  588. goto out;
  589. err = hex2sprom(sprom, buf, count);
  590. if (err) {
  591. err = -EINVAL;
  592. goto out_kfree;
  593. }
  594. err = sprom_check_crc(sprom);
  595. if (err) {
  596. err = -EINVAL;
  597. goto out_kfree;
  598. }
  599. /* Use interruptible locking, as the SPROM write might
  600. * be holding the lock for several seconds. So allow userspace
  601. * to cancel operation. */
  602. err = -ERESTARTSYS;
  603. if (mutex_lock_interruptible(&bus->pci_sprom_mutex))
  604. goto out_kfree;
  605. err = ssb_devices_freeze(bus);
  606. if (err == -EOPNOTSUPP) {
  607. ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
  608. "No suspend support. Is CONFIG_PM enabled?\n");
  609. goto out_unlock;
  610. }
  611. if (err) {
  612. ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
  613. goto out_unlock;
  614. }
  615. res = sprom_do_write(bus, sprom);
  616. err = ssb_devices_thaw(bus);
  617. if (err)
  618. ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
  619. out_unlock:
  620. mutex_unlock(&bus->pci_sprom_mutex);
  621. out_kfree:
  622. kfree(sprom);
  623. out:
  624. if (res)
  625. return res;
  626. return err ? err : count;
  627. }
  628. static DEVICE_ATTR(ssb_sprom, 0600,
  629. ssb_pci_attr_sprom_show,
  630. ssb_pci_attr_sprom_store);
  631. void ssb_pci_exit(struct ssb_bus *bus)
  632. {
  633. struct pci_dev *pdev;
  634. if (bus->bustype != SSB_BUSTYPE_PCI)
  635. return;
  636. pdev = bus->host_pci;
  637. device_remove_file(&pdev->dev, &dev_attr_ssb_sprom);
  638. }
  639. int ssb_pci_init(struct ssb_bus *bus)
  640. {
  641. struct pci_dev *pdev;
  642. int err;
  643. if (bus->bustype != SSB_BUSTYPE_PCI)
  644. return 0;
  645. pdev = bus->host_pci;
  646. mutex_init(&bus->pci_sprom_mutex);
  647. err = device_create_file(&pdev->dev, &dev_attr_ssb_sprom);
  648. if (err)
  649. goto out;
  650. out:
  651. return err;
  652. }