arcmsr_hba.c 66 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Erich Chen
  6. ** Description: SCSI RAID Device Driver for
  7. ** ARECA RAID Host adapter
  8. *******************************************************************************
  9. ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
  10. **
  11. ** Web site: www.areca.com.tw
  12. ** E-mail: support@areca.com.tw
  13. **
  14. ** This program is free software; you can redistribute it and/or modify
  15. ** it under the terms of the GNU General Public License version 2 as
  16. ** published by the Free Software Foundation.
  17. ** This program is distributed in the hope that it will be useful,
  18. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. ** GNU General Public License for more details.
  21. *******************************************************************************
  22. ** Redistribution and use in source and binary forms, with or without
  23. ** modification, are permitted provided that the following conditions
  24. ** are met:
  25. ** 1. Redistributions of source code must retain the above copyright
  26. ** notice, this list of conditions and the following disclaimer.
  27. ** 2. Redistributions in binary form must reproduce the above copyright
  28. ** notice, this list of conditions and the following disclaimer in the
  29. ** documentation and/or other materials provided with the distribution.
  30. ** 3. The name of the author may not be used to endorse or promote products
  31. ** derived from this software without specific prior written permission.
  32. **
  33. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  34. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  35. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  36. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  37. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  38. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  39. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  40. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  41. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  42. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  43. *******************************************************************************
  44. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  45. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  46. *******************************************************************************
  47. */
  48. #include <linux/module.h>
  49. #include <linux/reboot.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/pci_ids.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/moduleparam.h>
  54. #include <linux/errno.h>
  55. #include <linux/types.h>
  56. #include <linux/delay.h>
  57. #include <linux/dma-mapping.h>
  58. #include <linux/timer.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <asm/dma.h>
  62. #include <asm/io.h>
  63. #include <asm/system.h>
  64. #include <asm/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Erich Chen <support@areca.com.tw>");
  74. MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/13xx/16xx) SATA/SAS RAID HOST Adapter");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  78. struct scsi_cmnd *cmd);
  79. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  80. static int arcmsr_abort(struct scsi_cmnd *);
  81. static int arcmsr_bus_reset(struct scsi_cmnd *);
  82. static int arcmsr_bios_param(struct scsi_device *sdev,
  83. struct block_device *bdev, sector_t capacity, int *info);
  84. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  85. void (*done) (struct scsi_cmnd *));
  86. static int arcmsr_probe(struct pci_dev *pdev,
  87. const struct pci_device_id *id);
  88. static void arcmsr_remove(struct pci_dev *pdev);
  89. static void arcmsr_shutdown(struct pci_dev *pdev);
  90. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  91. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  92. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  93. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  94. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
  95. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
  96. static const char *arcmsr_info(struct Scsi_Host *);
  97. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  98. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
  99. int queue_depth)
  100. {
  101. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  102. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  103. scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
  104. return queue_depth;
  105. }
  106. static struct scsi_host_template arcmsr_scsi_host_template = {
  107. .module = THIS_MODULE,
  108. .name = "ARCMSR ARECA SATA/SAS RAID HOST Adapter"
  109. ARCMSR_DRIVER_VERSION,
  110. .info = arcmsr_info,
  111. .queuecommand = arcmsr_queue_command,
  112. .eh_abort_handler = arcmsr_abort,
  113. .eh_bus_reset_handler = arcmsr_bus_reset,
  114. .bios_param = arcmsr_bios_param,
  115. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  116. .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
  117. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  118. .sg_tablesize = ARCMSR_MAX_SG_ENTRIES,
  119. .max_sectors = ARCMSR_MAX_XFER_SECTORS,
  120. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  121. .use_clustering = ENABLE_CLUSTERING,
  122. .use_sg_chaining = ENABLE_SG_CHAINING,
  123. .shost_attrs = arcmsr_host_attrs,
  124. };
  125. #ifdef CONFIG_SCSI_ARCMSR_AER
  126. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev);
  127. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  128. pci_channel_state_t state);
  129. static struct pci_error_handlers arcmsr_pci_error_handlers = {
  130. .error_detected = arcmsr_pci_error_detected,
  131. .slot_reset = arcmsr_pci_slot_reset,
  132. };
  133. #endif
  134. static struct pci_device_id arcmsr_device_id_table[] = {
  135. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
  136. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
  137. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
  138. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
  139. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
  140. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
  141. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
  142. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
  143. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
  145. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
  147. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
  149. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
  151. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
  152. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
  153. {0, 0}, /* Terminating entry */
  154. };
  155. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  156. static struct pci_driver arcmsr_pci_driver = {
  157. .name = "arcmsr",
  158. .id_table = arcmsr_device_id_table,
  159. .probe = arcmsr_probe,
  160. .remove = arcmsr_remove,
  161. .shutdown = arcmsr_shutdown,
  162. #ifdef CONFIG_SCSI_ARCMSR_AER
  163. .err_handler = &arcmsr_pci_error_handlers,
  164. #endif
  165. };
  166. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  167. {
  168. irqreturn_t handle_state;
  169. struct AdapterControlBlock *acb = dev_id;
  170. spin_lock(acb->host->host_lock);
  171. handle_state = arcmsr_interrupt(acb);
  172. spin_unlock(acb->host->host_lock);
  173. return handle_state;
  174. }
  175. static int arcmsr_bios_param(struct scsi_device *sdev,
  176. struct block_device *bdev, sector_t capacity, int *geom)
  177. {
  178. int ret, heads, sectors, cylinders, total_capacity;
  179. unsigned char *buffer;/* return copy of block device's partition table */
  180. buffer = scsi_bios_ptable(bdev);
  181. if (buffer) {
  182. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  183. kfree(buffer);
  184. if (ret != -1)
  185. return ret;
  186. }
  187. total_capacity = capacity;
  188. heads = 64;
  189. sectors = 32;
  190. cylinders = total_capacity / (heads * sectors);
  191. if (cylinders > 1024) {
  192. heads = 255;
  193. sectors = 63;
  194. cylinders = total_capacity / (heads * sectors);
  195. }
  196. geom[0] = heads;
  197. geom[1] = sectors;
  198. geom[2] = cylinders;
  199. return 0;
  200. }
  201. static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
  202. {
  203. struct pci_dev *pdev = acb->pdev;
  204. u16 dev_id;
  205. pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
  206. switch (dev_id) {
  207. case 0x1201 : {
  208. acb->adapter_type = ACB_ADAPTER_TYPE_B;
  209. }
  210. break;
  211. default : acb->adapter_type = ACB_ADAPTER_TYPE_A;
  212. }
  213. }
  214. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  215. {
  216. switch (acb->adapter_type) {
  217. case ACB_ADAPTER_TYPE_A: {
  218. struct pci_dev *pdev = acb->pdev;
  219. void *dma_coherent;
  220. dma_addr_t dma_coherent_handle, dma_addr;
  221. struct CommandControlBlock *ccb_tmp;
  222. uint32_t intmask_org;
  223. int i, j;
  224. acb->pmu = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  225. if (!acb->pmu) {
  226. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n",
  227. acb->host->host_no);
  228. }
  229. dma_coherent = dma_alloc_coherent(&pdev->dev,
  230. ARCMSR_MAX_FREECCB_NUM *
  231. sizeof (struct CommandControlBlock) + 0x20,
  232. &dma_coherent_handle, GFP_KERNEL);
  233. if (!dma_coherent)
  234. return -ENOMEM;
  235. acb->dma_coherent = dma_coherent;
  236. acb->dma_coherent_handle = dma_coherent_handle;
  237. if (((unsigned long)dma_coherent & 0x1F)) {
  238. dma_coherent = dma_coherent +
  239. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  240. dma_coherent_handle = dma_coherent_handle +
  241. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  242. }
  243. dma_addr = dma_coherent_handle;
  244. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  245. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  246. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  247. ccb_tmp->acb = acb;
  248. acb->pccb_pool[i] = ccb_tmp;
  249. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  250. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  251. ccb_tmp++;
  252. }
  253. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  254. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  255. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  256. acb->devstate[i][j] = ARECA_RAID_GONE;
  257. /*
  258. ** here we need to tell iop 331 our ccb_tmp.HighPart
  259. ** if ccb_tmp.HighPart is not zero
  260. */
  261. intmask_org = arcmsr_disable_outbound_ints(acb);
  262. }
  263. break;
  264. case ACB_ADAPTER_TYPE_B: {
  265. struct pci_dev *pdev = acb->pdev;
  266. struct MessageUnit_B *reg;
  267. void *mem_base0, *mem_base1;
  268. void *dma_coherent;
  269. dma_addr_t dma_coherent_handle, dma_addr;
  270. uint32_t intmask_org;
  271. struct CommandControlBlock *ccb_tmp;
  272. int i, j;
  273. dma_coherent = dma_alloc_coherent(&pdev->dev,
  274. ((ARCMSR_MAX_FREECCB_NUM *
  275. sizeof(struct CommandControlBlock) + 0x20) +
  276. sizeof(struct MessageUnit_B)),
  277. &dma_coherent_handle, GFP_KERNEL);
  278. if (!dma_coherent)
  279. return -ENOMEM;
  280. acb->dma_coherent = dma_coherent;
  281. acb->dma_coherent_handle = dma_coherent_handle;
  282. if (((unsigned long)dma_coherent & 0x1F)) {
  283. dma_coherent = dma_coherent +
  284. (0x20 - ((unsigned long)dma_coherent & 0x1F));
  285. dma_coherent_handle = dma_coherent_handle +
  286. (0x20 - ((unsigned long)dma_coherent_handle & 0x1F));
  287. }
  288. reg = (struct MessageUnit_B *)(dma_coherent +
  289. ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock));
  290. dma_addr = dma_coherent_handle;
  291. ccb_tmp = (struct CommandControlBlock *)dma_coherent;
  292. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  293. ccb_tmp->cdb_shifted_phyaddr = dma_addr >> 5;
  294. ccb_tmp->acb = acb;
  295. acb->pccb_pool[i] = ccb_tmp;
  296. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  297. dma_addr = dma_addr + sizeof(struct CommandControlBlock);
  298. ccb_tmp++;
  299. }
  300. reg = (struct MessageUnit_B *)(dma_coherent +
  301. ARCMSR_MAX_FREECCB_NUM * sizeof(struct CommandControlBlock));
  302. acb->pmu = (struct MessageUnit *)reg;
  303. mem_base0 = ioremap(pci_resource_start(pdev, 0),
  304. pci_resource_len(pdev, 0));
  305. mem_base1 = ioremap(pci_resource_start(pdev, 2),
  306. pci_resource_len(pdev, 2));
  307. reg->drv2iop_doorbell_reg = (uint32_t *)((char *)mem_base0 +
  308. ARCMSR_DRV2IOP_DOORBELL);
  309. reg->drv2iop_doorbell_mask_reg = (uint32_t *)((char *)mem_base0 +
  310. ARCMSR_DRV2IOP_DOORBELL_MASK);
  311. reg->iop2drv_doorbell_reg = (uint32_t *)((char *)mem_base0 +
  312. ARCMSR_IOP2DRV_DOORBELL);
  313. reg->iop2drv_doorbell_mask_reg = (uint32_t *)((char *)mem_base0 +
  314. ARCMSR_IOP2DRV_DOORBELL_MASK);
  315. reg->ioctl_wbuffer_reg = (uint32_t *)((char *)mem_base1 +
  316. ARCMSR_IOCTL_WBUFFER);
  317. reg->ioctl_rbuffer_reg = (uint32_t *)((char *)mem_base1 +
  318. ARCMSR_IOCTL_RBUFFER);
  319. reg->msgcode_rwbuffer_reg = (uint32_t *)((char *)mem_base1 +
  320. ARCMSR_MSGCODE_RWBUFFER);
  321. acb->vir2phy_offset = (unsigned long)ccb_tmp -(unsigned long)dma_addr;
  322. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  323. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  324. acb->devstate[i][j] = ARECA_RAID_GOOD;
  325. /*
  326. ** here we need to tell iop 331 our ccb_tmp.HighPart
  327. ** if ccb_tmp.HighPart is not zero
  328. */
  329. intmask_org = arcmsr_disable_outbound_ints(acb);
  330. }
  331. break;
  332. }
  333. return 0;
  334. }
  335. static int arcmsr_probe(struct pci_dev *pdev,
  336. const struct pci_device_id *id)
  337. {
  338. struct Scsi_Host *host;
  339. struct AdapterControlBlock *acb;
  340. uint8_t bus, dev_fun;
  341. int error;
  342. error = pci_enable_device(pdev);
  343. if (error)
  344. goto out;
  345. pci_set_master(pdev);
  346. host = scsi_host_alloc(&arcmsr_scsi_host_template,
  347. sizeof(struct AdapterControlBlock));
  348. if (!host) {
  349. error = -ENOMEM;
  350. goto out_disable_device;
  351. }
  352. acb = (struct AdapterControlBlock *)host->hostdata;
  353. memset(acb, 0, sizeof (struct AdapterControlBlock));
  354. error = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
  355. if (error) {
  356. error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  357. if (error) {
  358. printk(KERN_WARNING
  359. "scsi%d: No suitable DMA mask available\n",
  360. host->host_no);
  361. goto out_host_put;
  362. }
  363. }
  364. bus = pdev->bus->number;
  365. dev_fun = pdev->devfn;
  366. acb->host = host;
  367. acb->pdev = pdev;
  368. host->max_sectors = ARCMSR_MAX_XFER_SECTORS;
  369. host->max_lun = ARCMSR_MAX_TARGETLUN;
  370. host->max_id = ARCMSR_MAX_TARGETID;/*16:8*/
  371. host->max_cmd_len = 16; /*this is issue of 64bit LBA, over 2T byte*/
  372. host->sg_tablesize = ARCMSR_MAX_SG_ENTRIES;
  373. host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
  374. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  375. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  376. host->unique_id = (bus << 8) | dev_fun;
  377. host->irq = pdev->irq;
  378. error = pci_request_regions(pdev, "arcmsr");
  379. if (error) {
  380. goto out_host_put;
  381. }
  382. arcmsr_define_adapter_type(acb);
  383. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  384. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  385. ACB_F_MESSAGE_WQBUFFER_READED);
  386. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  387. INIT_LIST_HEAD(&acb->ccb_free_list);
  388. error = arcmsr_alloc_ccb_pool(acb);
  389. if (error)
  390. goto out_release_regions;
  391. error = request_irq(pdev->irq, arcmsr_do_interrupt,
  392. IRQF_SHARED, "arcmsr", acb);
  393. if (error)
  394. goto out_free_ccb_pool;
  395. arcmsr_iop_init(acb);
  396. pci_set_drvdata(pdev, host);
  397. if (strncmp(acb->firm_version, "V1.42", 5) >= 0)
  398. host->max_sectors= ARCMSR_MAX_XFER_SECTORS_B;
  399. error = scsi_add_host(host, &pdev->dev);
  400. if (error)
  401. goto out_free_irq;
  402. error = arcmsr_alloc_sysfs_attr(acb);
  403. if (error)
  404. goto out_free_sysfs;
  405. scsi_scan_host(host);
  406. #ifdef CONFIG_SCSI_ARCMSR_AER
  407. pci_enable_pcie_error_reporting(pdev);
  408. #endif
  409. return 0;
  410. out_free_sysfs:
  411. out_free_irq:
  412. free_irq(pdev->irq, acb);
  413. out_free_ccb_pool:
  414. arcmsr_free_ccb_pool(acb);
  415. iounmap(acb->pmu);
  416. out_release_regions:
  417. pci_release_regions(pdev);
  418. out_host_put:
  419. scsi_host_put(host);
  420. out_disable_device:
  421. pci_disable_device(pdev);
  422. out:
  423. return error;
  424. }
  425. static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
  426. {
  427. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  428. uint32_t Index;
  429. uint8_t Retries = 0x00;
  430. do {
  431. for (Index = 0; Index < 100; Index++) {
  432. if (readl(&reg->outbound_intstatus) &
  433. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  434. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  435. &reg->outbound_intstatus);
  436. return 0x00;
  437. }
  438. msleep(10);
  439. }/*max 1 seconds*/
  440. } while (Retries++ < 20);/*max 20 sec*/
  441. return 0xff;
  442. }
  443. static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
  444. {
  445. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  446. uint32_t Index;
  447. uint8_t Retries = 0x00;
  448. do {
  449. for (Index = 0; Index < 100; Index++) {
  450. if (readl(reg->iop2drv_doorbell_reg)
  451. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  452. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN
  453. , reg->iop2drv_doorbell_reg);
  454. return 0x00;
  455. }
  456. msleep(10);
  457. }/*max 1 seconds*/
  458. } while (Retries++ < 20);/*max 20 sec*/
  459. return 0xff;
  460. }
  461. static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
  462. {
  463. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  464. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  465. if (arcmsr_hba_wait_msgint_ready(acb))
  466. printk(KERN_NOTICE
  467. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  468. , acb->host->host_no);
  469. }
  470. static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
  471. {
  472. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  473. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell_reg);
  474. if (arcmsr_hbb_wait_msgint_ready(acb))
  475. printk(KERN_NOTICE
  476. "arcmsr%d: wait 'abort all outstanding command' timeout \n"
  477. , acb->host->host_no);
  478. }
  479. static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  480. {
  481. switch (acb->adapter_type) {
  482. case ACB_ADAPTER_TYPE_A: {
  483. arcmsr_abort_hba_allcmd(acb);
  484. }
  485. break;
  486. case ACB_ADAPTER_TYPE_B: {
  487. arcmsr_abort_hbb_allcmd(acb);
  488. }
  489. }
  490. }
  491. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  492. {
  493. struct scsi_cmnd *pcmd = ccb->pcmd;
  494. scsi_dma_unmap(pcmd);
  495. }
  496. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb, int stand_flag)
  497. {
  498. struct AdapterControlBlock *acb = ccb->acb;
  499. struct scsi_cmnd *pcmd = ccb->pcmd;
  500. arcmsr_pci_unmap_dma(ccb);
  501. if (stand_flag == 1)
  502. atomic_dec(&acb->ccboutstandingcount);
  503. ccb->startdone = ARCMSR_CCB_DONE;
  504. ccb->ccb_flags = 0;
  505. list_add_tail(&ccb->list, &acb->ccb_free_list);
  506. pcmd->scsi_done(pcmd);
  507. }
  508. static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
  509. {
  510. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  511. int retry_count = 30;
  512. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  513. do {
  514. if (!arcmsr_hba_wait_msgint_ready(acb))
  515. break;
  516. else {
  517. retry_count--;
  518. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  519. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  520. }
  521. } while (retry_count != 0);
  522. }
  523. static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
  524. {
  525. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  526. int retry_count = 30;
  527. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell_reg);
  528. do {
  529. if (!arcmsr_hbb_wait_msgint_ready(acb))
  530. break;
  531. else {
  532. retry_count--;
  533. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  534. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  535. }
  536. } while (retry_count != 0);
  537. }
  538. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  539. {
  540. switch (acb->adapter_type) {
  541. case ACB_ADAPTER_TYPE_A: {
  542. arcmsr_flush_hba_cache(acb);
  543. }
  544. break;
  545. case ACB_ADAPTER_TYPE_B: {
  546. arcmsr_flush_hbb_cache(acb);
  547. }
  548. }
  549. }
  550. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  551. {
  552. struct scsi_cmnd *pcmd = ccb->pcmd;
  553. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  554. pcmd->result = DID_OK << 16;
  555. if (sensebuffer) {
  556. int sense_data_length =
  557. sizeof(struct SENSE_DATA) < sizeof(pcmd->sense_buffer)
  558. ? sizeof(struct SENSE_DATA) : sizeof(pcmd->sense_buffer);
  559. memset(sensebuffer, 0, sizeof(pcmd->sense_buffer));
  560. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  561. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  562. sensebuffer->Valid = 1;
  563. }
  564. }
  565. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  566. {
  567. u32 orig_mask = 0;
  568. switch (acb->adapter_type) {
  569. case ACB_ADAPTER_TYPE_A : {
  570. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  571. orig_mask = readl(&reg->outbound_intmask)|\
  572. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE;
  573. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  574. &reg->outbound_intmask);
  575. }
  576. break;
  577. case ACB_ADAPTER_TYPE_B : {
  578. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  579. orig_mask = readl(reg->iop2drv_doorbell_mask_reg) & \
  580. (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  581. writel(0, reg->iop2drv_doorbell_mask_reg);
  582. }
  583. break;
  584. }
  585. return orig_mask;
  586. }
  587. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, \
  588. struct CommandControlBlock *ccb, uint32_t flag_ccb)
  589. {
  590. uint8_t id, lun;
  591. id = ccb->pcmd->device->id;
  592. lun = ccb->pcmd->device->lun;
  593. if (!(flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR)) {
  594. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  595. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  596. ccb->pcmd->result = DID_OK << 16;
  597. arcmsr_ccb_complete(ccb, 1);
  598. } else {
  599. switch (ccb->arcmsr_cdb.DeviceStatus) {
  600. case ARCMSR_DEV_SELECT_TIMEOUT: {
  601. acb->devstate[id][lun] = ARECA_RAID_GONE;
  602. ccb->pcmd->result = DID_NO_CONNECT << 16;
  603. arcmsr_ccb_complete(ccb, 1);
  604. }
  605. break;
  606. case ARCMSR_DEV_ABORTED:
  607. case ARCMSR_DEV_INIT_FAIL: {
  608. acb->devstate[id][lun] = ARECA_RAID_GONE;
  609. ccb->pcmd->result = DID_BAD_TARGET << 16;
  610. arcmsr_ccb_complete(ccb, 1);
  611. }
  612. break;
  613. case ARCMSR_DEV_CHECK_CONDITION: {
  614. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  615. arcmsr_report_sense_info(ccb);
  616. arcmsr_ccb_complete(ccb, 1);
  617. }
  618. break;
  619. default:
  620. printk(KERN_NOTICE
  621. "arcmsr%d: scsi id = %d lun = %d"
  622. " isr get command error done, "
  623. "but got unknown DeviceStatus = 0x%x \n"
  624. , acb->host->host_no
  625. , id
  626. , lun
  627. , ccb->arcmsr_cdb.DeviceStatus);
  628. acb->devstate[id][lun] = ARECA_RAID_GONE;
  629. ccb->pcmd->result = DID_NO_CONNECT << 16;
  630. arcmsr_ccb_complete(ccb, 1);
  631. break;
  632. }
  633. }
  634. }
  635. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, uint32_t flag_ccb)
  636. {
  637. struct CommandControlBlock *ccb;
  638. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  639. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  640. if (ccb->startdone == ARCMSR_CCB_ABORTED) {
  641. struct scsi_cmnd *abortcmd = ccb->pcmd;
  642. if (abortcmd) {
  643. abortcmd->result |= DID_ABORT << 16;
  644. arcmsr_ccb_complete(ccb, 1);
  645. printk(KERN_NOTICE "arcmsr%d: ccb ='0x%p' \
  646. isr got aborted command \n", acb->host->host_no, ccb);
  647. }
  648. }
  649. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  650. done acb = '0x%p'"
  651. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  652. " ccboutstandingcount = %d \n"
  653. , acb->host->host_no
  654. , acb
  655. , ccb
  656. , ccb->acb
  657. , ccb->startdone
  658. , atomic_read(&acb->ccboutstandingcount));
  659. }
  660. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  661. }
  662. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  663. {
  664. int i = 0;
  665. uint32_t flag_ccb;
  666. switch (acb->adapter_type) {
  667. case ACB_ADAPTER_TYPE_A: {
  668. struct MessageUnit_A __iomem *reg = \
  669. (struct MessageUnit_A *)acb->pmu;
  670. uint32_t outbound_intstatus;
  671. outbound_intstatus = readl(&reg->outbound_intstatus) & \
  672. acb->outbound_int_enable;
  673. /*clear and abort all outbound posted Q*/
  674. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  675. while (((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) \
  676. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  677. arcmsr_drain_donequeue(acb, flag_ccb);
  678. }
  679. }
  680. break;
  681. case ACB_ADAPTER_TYPE_B: {
  682. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  683. /*clear all outbound posted Q*/
  684. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  685. if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
  686. writel(0, &reg->done_qbuffer[i]);
  687. arcmsr_drain_donequeue(acb, flag_ccb);
  688. }
  689. writel(0, &reg->post_qbuffer[i]);
  690. }
  691. reg->doneq_index = 0;
  692. reg->postq_index = 0;
  693. }
  694. break;
  695. }
  696. }
  697. static void arcmsr_remove(struct pci_dev *pdev)
  698. {
  699. struct Scsi_Host *host = pci_get_drvdata(pdev);
  700. struct AdapterControlBlock *acb =
  701. (struct AdapterControlBlock *) host->hostdata;
  702. int poll_count = 0;
  703. arcmsr_free_sysfs_attr(acb);
  704. scsi_remove_host(host);
  705. arcmsr_stop_adapter_bgrb(acb);
  706. arcmsr_flush_adapter_cache(acb);
  707. arcmsr_disable_outbound_ints(acb);
  708. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  709. acb->acb_flags &= ~ACB_F_IOP_INITED;
  710. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++) {
  711. if (!atomic_read(&acb->ccboutstandingcount))
  712. break;
  713. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  714. msleep(25);
  715. }
  716. if (atomic_read(&acb->ccboutstandingcount)) {
  717. int i;
  718. arcmsr_abort_allcmd(acb);
  719. arcmsr_done4abort_postqueue(acb);
  720. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  721. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  722. if (ccb->startdone == ARCMSR_CCB_START) {
  723. ccb->startdone = ARCMSR_CCB_ABORTED;
  724. ccb->pcmd->result = DID_ABORT << 16;
  725. arcmsr_ccb_complete(ccb, 1);
  726. }
  727. }
  728. }
  729. free_irq(pdev->irq, acb);
  730. iounmap(acb->pmu);
  731. arcmsr_free_ccb_pool(acb);
  732. pci_release_regions(pdev);
  733. scsi_host_put(host);
  734. pci_disable_device(pdev);
  735. pci_set_drvdata(pdev, NULL);
  736. }
  737. static void arcmsr_shutdown(struct pci_dev *pdev)
  738. {
  739. struct Scsi_Host *host = pci_get_drvdata(pdev);
  740. struct AdapterControlBlock *acb =
  741. (struct AdapterControlBlock *)host->hostdata;
  742. arcmsr_stop_adapter_bgrb(acb);
  743. arcmsr_flush_adapter_cache(acb);
  744. }
  745. static int arcmsr_module_init(void)
  746. {
  747. int error = 0;
  748. error = pci_register_driver(&arcmsr_pci_driver);
  749. return error;
  750. }
  751. static void arcmsr_module_exit(void)
  752. {
  753. pci_unregister_driver(&arcmsr_pci_driver);
  754. }
  755. module_init(arcmsr_module_init);
  756. module_exit(arcmsr_module_exit);
  757. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, \
  758. u32 intmask_org)
  759. {
  760. u32 mask;
  761. switch (acb->adapter_type) {
  762. case ACB_ADAPTER_TYPE_A : {
  763. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  764. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  765. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE);
  766. writel(mask, &reg->outbound_intmask);
  767. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  768. }
  769. break;
  770. case ACB_ADAPTER_TYPE_B : {
  771. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  772. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | \
  773. ARCMSR_IOP2DRV_DATA_READ_OK | ARCMSR_IOP2DRV_CDB_DONE);
  774. writel(mask, reg->iop2drv_doorbell_mask_reg);
  775. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  776. }
  777. }
  778. }
  779. static void arcmsr_build_ccb(struct AdapterControlBlock *acb,
  780. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  781. {
  782. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  783. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  784. uint32_t address_lo, address_hi;
  785. int arccdbsize = 0x30;
  786. int nseg;
  787. ccb->pcmd = pcmd;
  788. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  789. arcmsr_cdb->Bus = 0;
  790. arcmsr_cdb->TargetID = pcmd->device->id;
  791. arcmsr_cdb->LUN = pcmd->device->lun;
  792. arcmsr_cdb->Function = 1;
  793. arcmsr_cdb->CdbLength = (uint8_t)pcmd->cmd_len;
  794. arcmsr_cdb->Context = (unsigned long)arcmsr_cdb;
  795. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  796. nseg = scsi_dma_map(pcmd);
  797. BUG_ON(nseg < 0);
  798. if (nseg) {
  799. int length, i, cdb_sgcount = 0;
  800. struct scatterlist *sg;
  801. /* map stor port SG list to our iop SG List. */
  802. scsi_for_each_sg(pcmd, sg, nseg, i) {
  803. /* Get the physical address of the current data pointer */
  804. length = cpu_to_le32(sg_dma_len(sg));
  805. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  806. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  807. if (address_hi == 0) {
  808. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  809. pdma_sg->address = address_lo;
  810. pdma_sg->length = length;
  811. psge += sizeof (struct SG32ENTRY);
  812. arccdbsize += sizeof (struct SG32ENTRY);
  813. } else {
  814. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  815. pdma_sg->addresshigh = address_hi;
  816. pdma_sg->address = address_lo;
  817. pdma_sg->length = length|IS_SG64_ADDR;
  818. psge += sizeof (struct SG64ENTRY);
  819. arccdbsize += sizeof (struct SG64ENTRY);
  820. }
  821. cdb_sgcount++;
  822. }
  823. arcmsr_cdb->sgcount = (uint8_t)cdb_sgcount;
  824. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  825. if ( arccdbsize > 256)
  826. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  827. }
  828. if (pcmd->sc_data_direction == DMA_TO_DEVICE ) {
  829. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  830. ccb->ccb_flags |= CCB_FLAG_WRITE;
  831. }
  832. }
  833. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  834. {
  835. uint32_t cdb_shifted_phyaddr = ccb->cdb_shifted_phyaddr;
  836. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  837. atomic_inc(&acb->ccboutstandingcount);
  838. ccb->startdone = ARCMSR_CCB_START;
  839. switch (acb->adapter_type) {
  840. case ACB_ADAPTER_TYPE_A: {
  841. struct MessageUnit_A *reg = (struct MessageUnit_A *)acb->pmu;
  842. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  843. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  844. &reg->inbound_queueport);
  845. else {
  846. writel(cdb_shifted_phyaddr, &reg->inbound_queueport);
  847. }
  848. }
  849. break;
  850. case ACB_ADAPTER_TYPE_B: {
  851. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  852. uint32_t ending_index, index = reg->postq_index;
  853. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  854. writel(0, &reg->post_qbuffer[ending_index]);
  855. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  856. writel(cdb_shifted_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
  857. &reg->post_qbuffer[index]);
  858. }
  859. else {
  860. writel(cdb_shifted_phyaddr, &reg->post_qbuffer[index]);
  861. }
  862. index++;
  863. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  864. reg->postq_index = index;
  865. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell_reg);
  866. }
  867. break;
  868. }
  869. }
  870. static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
  871. {
  872. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  873. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  874. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  875. if (arcmsr_hba_wait_msgint_ready(acb)) {
  876. printk(KERN_NOTICE
  877. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  878. , acb->host->host_no);
  879. }
  880. }
  881. static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
  882. {
  883. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  884. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  885. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell_reg);
  886. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  887. printk(KERN_NOTICE
  888. "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
  889. , acb->host->host_no);
  890. }
  891. }
  892. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  893. {
  894. switch (acb->adapter_type) {
  895. case ACB_ADAPTER_TYPE_A: {
  896. arcmsr_stop_hba_bgrb(acb);
  897. }
  898. break;
  899. case ACB_ADAPTER_TYPE_B: {
  900. arcmsr_stop_hbb_bgrb(acb);
  901. }
  902. break;
  903. }
  904. }
  905. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  906. {
  907. dma_free_coherent(&acb->pdev->dev,
  908. ARCMSR_MAX_FREECCB_NUM * sizeof (struct CommandControlBlock) + 0x20,
  909. acb->dma_coherent,
  910. acb->dma_coherent_handle);
  911. }
  912. void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  913. {
  914. switch (acb->adapter_type) {
  915. case ACB_ADAPTER_TYPE_A: {
  916. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  917. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  918. }
  919. break;
  920. case ACB_ADAPTER_TYPE_B: {
  921. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  922. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  923. }
  924. break;
  925. }
  926. }
  927. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  928. {
  929. switch (acb->adapter_type) {
  930. case ACB_ADAPTER_TYPE_A: {
  931. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  932. /*
  933. ** push inbound doorbell tell iop, driver data write ok
  934. ** and wait reply on next hwinterrupt for next Qbuffer post
  935. */
  936. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  937. }
  938. break;
  939. case ACB_ADAPTER_TYPE_B: {
  940. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  941. /*
  942. ** push inbound doorbell tell iop, driver data write ok
  943. ** and wait reply on next hwinterrupt for next Qbuffer post
  944. */
  945. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell_reg);
  946. }
  947. break;
  948. }
  949. }
  950. struct QBUFFER *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  951. {
  952. static struct QBUFFER *qbuffer;
  953. switch (acb->adapter_type) {
  954. case ACB_ADAPTER_TYPE_A: {
  955. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  956. qbuffer = (struct QBUFFER __iomem *) &reg->message_rbuffer;
  957. }
  958. break;
  959. case ACB_ADAPTER_TYPE_B: {
  960. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  961. qbuffer = (struct QBUFFER __iomem *) reg->ioctl_rbuffer_reg;
  962. }
  963. break;
  964. }
  965. return qbuffer;
  966. }
  967. static struct QBUFFER *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  968. {
  969. static struct QBUFFER *pqbuffer;
  970. switch (acb->adapter_type) {
  971. case ACB_ADAPTER_TYPE_A: {
  972. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  973. pqbuffer = (struct QBUFFER *) &reg->message_wbuffer;
  974. }
  975. break;
  976. case ACB_ADAPTER_TYPE_B: {
  977. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  978. pqbuffer = (struct QBUFFER __iomem *)reg->ioctl_wbuffer_reg;
  979. }
  980. break;
  981. }
  982. return pqbuffer;
  983. }
  984. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  985. {
  986. struct QBUFFER *prbuffer;
  987. struct QBUFFER *pQbuffer;
  988. uint8_t *iop_data;
  989. int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
  990. rqbuf_lastindex = acb->rqbuf_lastindex;
  991. rqbuf_firstindex = acb->rqbuf_firstindex;
  992. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  993. iop_data = (uint8_t *)prbuffer->data;
  994. iop_len = prbuffer->data_len;
  995. my_empty_len = (rqbuf_firstindex - rqbuf_lastindex -1)&(ARCMSR_MAX_QBUFFER -1);
  996. if (my_empty_len >= iop_len)
  997. {
  998. while (iop_len > 0) {
  999. pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
  1000. memcpy(pQbuffer, iop_data,1);
  1001. rqbuf_lastindex++;
  1002. rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1003. iop_data++;
  1004. iop_len--;
  1005. }
  1006. acb->rqbuf_lastindex = rqbuf_lastindex;
  1007. arcmsr_iop_message_read(acb);
  1008. }
  1009. else {
  1010. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1011. }
  1012. }
  1013. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1014. {
  1015. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1016. if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
  1017. uint8_t *pQbuffer;
  1018. struct QBUFFER *pwbuffer;
  1019. uint8_t *iop_data;
  1020. int32_t allxfer_len = 0;
  1021. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1022. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1023. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1024. while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
  1025. (allxfer_len < 124)) {
  1026. pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
  1027. memcpy(iop_data, pQbuffer, 1);
  1028. acb->wqbuf_firstindex++;
  1029. acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1030. iop_data++;
  1031. allxfer_len++;
  1032. }
  1033. pwbuffer->data_len = allxfer_len;
  1034. arcmsr_iop_message_wrote(acb);
  1035. }
  1036. if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
  1037. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1038. }
  1039. }
  1040. static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
  1041. {
  1042. uint32_t outbound_doorbell;
  1043. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  1044. outbound_doorbell = readl(&reg->outbound_doorbell);
  1045. writel(outbound_doorbell, &reg->outbound_doorbell);
  1046. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
  1047. arcmsr_iop2drv_data_wrote_handle(acb);
  1048. }
  1049. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
  1050. arcmsr_iop2drv_data_read_handle(acb);
  1051. }
  1052. }
  1053. static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
  1054. {
  1055. uint32_t flag_ccb;
  1056. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  1057. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1058. arcmsr_drain_donequeue(acb, flag_ccb);
  1059. }
  1060. }
  1061. static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
  1062. {
  1063. uint32_t index;
  1064. uint32_t flag_ccb;
  1065. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1066. index = reg->doneq_index;
  1067. while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
  1068. writel(0, &reg->done_qbuffer[index]);
  1069. arcmsr_drain_donequeue(acb, flag_ccb);
  1070. index++;
  1071. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1072. reg->doneq_index = index;
  1073. }
  1074. }
  1075. static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
  1076. {
  1077. uint32_t outbound_intstatus;
  1078. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  1079. outbound_intstatus = readl(&reg->outbound_intstatus) & \
  1080. acb->outbound_int_enable;
  1081. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
  1082. return 1;
  1083. }
  1084. writel(outbound_intstatus, &reg->outbound_intstatus);
  1085. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
  1086. arcmsr_hba_doorbell_isr(acb);
  1087. }
  1088. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
  1089. arcmsr_hba_postqueue_isr(acb);
  1090. }
  1091. return 0;
  1092. }
  1093. static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
  1094. {
  1095. uint32_t outbound_doorbell;
  1096. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1097. outbound_doorbell = readl(reg->iop2drv_doorbell_reg) & \
  1098. acb->outbound_int_enable;
  1099. if (!outbound_doorbell)
  1100. return 1;
  1101. writel(~outbound_doorbell, reg->iop2drv_doorbell_reg);
  1102. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
  1103. arcmsr_iop2drv_data_wrote_handle(acb);
  1104. }
  1105. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
  1106. arcmsr_iop2drv_data_read_handle(acb);
  1107. }
  1108. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
  1109. arcmsr_hbb_postqueue_isr(acb);
  1110. }
  1111. return 0;
  1112. }
  1113. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  1114. {
  1115. switch (acb->adapter_type) {
  1116. case ACB_ADAPTER_TYPE_A: {
  1117. if (arcmsr_handle_hba_isr(acb)) {
  1118. return IRQ_NONE;
  1119. }
  1120. }
  1121. break;
  1122. case ACB_ADAPTER_TYPE_B: {
  1123. if (arcmsr_handle_hbb_isr(acb)) {
  1124. return IRQ_NONE;
  1125. }
  1126. }
  1127. break;
  1128. }
  1129. return IRQ_HANDLED;
  1130. }
  1131. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  1132. {
  1133. if (acb) {
  1134. /* stop adapter background rebuild */
  1135. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  1136. uint32_t intmask_org;
  1137. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1138. intmask_org = arcmsr_disable_outbound_ints(acb);
  1139. arcmsr_stop_adapter_bgrb(acb);
  1140. arcmsr_flush_adapter_cache(acb);
  1141. arcmsr_enable_outbound_ints(acb, intmask_org);
  1142. }
  1143. }
  1144. }
  1145. void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
  1146. {
  1147. int32_t wqbuf_firstindex, wqbuf_lastindex;
  1148. uint8_t *pQbuffer;
  1149. struct QBUFFER *pwbuffer;
  1150. uint8_t *iop_data;
  1151. int32_t allxfer_len = 0;
  1152. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1153. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1154. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1155. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1156. wqbuf_firstindex = acb->wqbuf_firstindex;
  1157. wqbuf_lastindex = acb->wqbuf_lastindex;
  1158. while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
  1159. pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
  1160. memcpy(iop_data, pQbuffer, 1);
  1161. wqbuf_firstindex++;
  1162. wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1163. iop_data++;
  1164. allxfer_len++;
  1165. }
  1166. acb->wqbuf_firstindex = wqbuf_firstindex;
  1167. pwbuffer->data_len = allxfer_len;
  1168. arcmsr_iop_message_wrote(acb);
  1169. }
  1170. }
  1171. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, \
  1172. struct scsi_cmnd *cmd)
  1173. {
  1174. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  1175. int retvalue = 0, transfer_len = 0;
  1176. char *buffer;
  1177. struct scatterlist *sg;
  1178. uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
  1179. (uint32_t ) cmd->cmnd[6] << 16 |
  1180. (uint32_t ) cmd->cmnd[7] << 8 |
  1181. (uint32_t ) cmd->cmnd[8];
  1182. /* 4 bytes: Areca io control code */
  1183. sg = scsi_sglist(cmd);
  1184. buffer = kmap_atomic(sg->page, KM_IRQ0) + sg->offset;
  1185. if (scsi_sg_count(cmd) > 1) {
  1186. retvalue = ARCMSR_MESSAGE_FAIL;
  1187. goto message_out;
  1188. }
  1189. transfer_len += sg->length;
  1190. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  1191. retvalue = ARCMSR_MESSAGE_FAIL;
  1192. goto message_out;
  1193. }
  1194. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
  1195. switch(controlcode) {
  1196. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  1197. unsigned long *ver_addr;
  1198. dma_addr_t buf_handle;
  1199. uint8_t *pQbuffer, *ptmpQbuffer;
  1200. int32_t allxfer_len = 0;
  1201. ver_addr = pci_alloc_consistent(acb->pdev, 1032, &buf_handle);
  1202. if (!ver_addr) {
  1203. retvalue = ARCMSR_MESSAGE_FAIL;
  1204. goto message_out;
  1205. }
  1206. ptmpQbuffer = (uint8_t *) ver_addr;
  1207. while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
  1208. && (allxfer_len < 1031)) {
  1209. pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
  1210. memcpy(ptmpQbuffer, pQbuffer, 1);
  1211. acb->rqbuf_firstindex++;
  1212. acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
  1213. ptmpQbuffer++;
  1214. allxfer_len++;
  1215. }
  1216. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1217. struct QBUFFER *prbuffer;
  1218. uint8_t *iop_data;
  1219. int32_t iop_len;
  1220. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1221. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1222. iop_data = (uint8_t *)prbuffer->data;
  1223. iop_len = readl(&prbuffer->data_len);
  1224. while (iop_len > 0) {
  1225. acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
  1226. acb->rqbuf_lastindex++;
  1227. acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1228. iop_data++;
  1229. iop_len--;
  1230. }
  1231. arcmsr_iop_message_read(acb);
  1232. }
  1233. memcpy(pcmdmessagefld->messagedatabuffer, (uint8_t *)ver_addr, allxfer_len);
  1234. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  1235. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1236. pci_free_consistent(acb->pdev, 1032, ver_addr, buf_handle);
  1237. }
  1238. break;
  1239. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  1240. unsigned long *ver_addr;
  1241. dma_addr_t buf_handle;
  1242. int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
  1243. uint8_t *pQbuffer, *ptmpuserbuffer;
  1244. ver_addr = pci_alloc_consistent(acb->pdev, 1032, &buf_handle);
  1245. if (!ver_addr) {
  1246. retvalue = ARCMSR_MESSAGE_FAIL;
  1247. goto message_out;
  1248. }
  1249. ptmpuserbuffer = (uint8_t *)ver_addr;
  1250. user_len = pcmdmessagefld->cmdmessage.Length;
  1251. memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
  1252. wqbuf_lastindex = acb->wqbuf_lastindex;
  1253. wqbuf_firstindex = acb->wqbuf_firstindex;
  1254. if (wqbuf_lastindex != wqbuf_firstindex) {
  1255. struct SENSE_DATA *sensebuffer =
  1256. (struct SENSE_DATA *)cmd->sense_buffer;
  1257. arcmsr_post_ioctldata2iop(acb);
  1258. /* has error report sensedata */
  1259. sensebuffer->ErrorCode = 0x70;
  1260. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1261. sensebuffer->AdditionalSenseLength = 0x0A;
  1262. sensebuffer->AdditionalSenseCode = 0x20;
  1263. sensebuffer->Valid = 1;
  1264. retvalue = ARCMSR_MESSAGE_FAIL;
  1265. } else {
  1266. my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
  1267. &(ARCMSR_MAX_QBUFFER - 1);
  1268. if (my_empty_len >= user_len) {
  1269. while (user_len > 0) {
  1270. pQbuffer =
  1271. &acb->wqbuffer[acb->wqbuf_lastindex];
  1272. memcpy(pQbuffer, ptmpuserbuffer, 1);
  1273. acb->wqbuf_lastindex++;
  1274. acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
  1275. ptmpuserbuffer++;
  1276. user_len--;
  1277. }
  1278. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  1279. acb->acb_flags &=
  1280. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1281. arcmsr_post_ioctldata2iop(acb);
  1282. }
  1283. } else {
  1284. /* has error report sensedata */
  1285. struct SENSE_DATA *sensebuffer =
  1286. (struct SENSE_DATA *)cmd->sense_buffer;
  1287. sensebuffer->ErrorCode = 0x70;
  1288. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  1289. sensebuffer->AdditionalSenseLength = 0x0A;
  1290. sensebuffer->AdditionalSenseCode = 0x20;
  1291. sensebuffer->Valid = 1;
  1292. retvalue = ARCMSR_MESSAGE_FAIL;
  1293. }
  1294. }
  1295. pci_free_consistent(acb->pdev, 1032, ver_addr, buf_handle);
  1296. }
  1297. break;
  1298. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  1299. uint8_t *pQbuffer = acb->rqbuffer;
  1300. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1301. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1302. arcmsr_iop_message_read(acb);
  1303. }
  1304. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  1305. acb->rqbuf_firstindex = 0;
  1306. acb->rqbuf_lastindex = 0;
  1307. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1308. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1309. }
  1310. break;
  1311. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  1312. uint8_t *pQbuffer = acb->wqbuffer;
  1313. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1314. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1315. arcmsr_iop_message_read(acb);
  1316. }
  1317. acb->acb_flags |=
  1318. (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  1319. ACB_F_MESSAGE_WQBUFFER_READED);
  1320. acb->wqbuf_firstindex = 0;
  1321. acb->wqbuf_lastindex = 0;
  1322. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  1323. pcmdmessagefld->cmdmessage.ReturnCode =
  1324. ARCMSR_MESSAGE_RETURNCODE_OK;
  1325. }
  1326. break;
  1327. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  1328. uint8_t *pQbuffer;
  1329. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  1330. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  1331. arcmsr_iop_message_read(acb);
  1332. }
  1333. acb->acb_flags |=
  1334. (ACB_F_MESSAGE_WQBUFFER_CLEARED
  1335. | ACB_F_MESSAGE_RQBUFFER_CLEARED
  1336. | ACB_F_MESSAGE_WQBUFFER_READED);
  1337. acb->rqbuf_firstindex = 0;
  1338. acb->rqbuf_lastindex = 0;
  1339. acb->wqbuf_firstindex = 0;
  1340. acb->wqbuf_lastindex = 0;
  1341. pQbuffer = acb->rqbuffer;
  1342. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1343. pQbuffer = acb->wqbuffer;
  1344. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  1345. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1346. }
  1347. break;
  1348. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  1349. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
  1350. }
  1351. break;
  1352. case ARCMSR_MESSAGE_SAY_HELLO: {
  1353. int8_t *hello_string = "Hello! I am ARCMSR";
  1354. memcpy(pcmdmessagefld->messagedatabuffer, hello_string
  1355. , (int16_t)strlen(hello_string));
  1356. pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
  1357. }
  1358. break;
  1359. case ARCMSR_MESSAGE_SAY_GOODBYE:
  1360. arcmsr_iop_parking(acb);
  1361. break;
  1362. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
  1363. arcmsr_flush_adapter_cache(acb);
  1364. break;
  1365. default:
  1366. retvalue = ARCMSR_MESSAGE_FAIL;
  1367. }
  1368. message_out:
  1369. sg = scsi_sglist(cmd);
  1370. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1371. return retvalue;
  1372. }
  1373. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  1374. {
  1375. struct list_head *head = &acb->ccb_free_list;
  1376. struct CommandControlBlock *ccb = NULL;
  1377. if (!list_empty(head)) {
  1378. ccb = list_entry(head->next, struct CommandControlBlock, list);
  1379. list_del(head->next);
  1380. }
  1381. return ccb;
  1382. }
  1383. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  1384. struct scsi_cmnd *cmd)
  1385. {
  1386. switch (cmd->cmnd[0]) {
  1387. case INQUIRY: {
  1388. unsigned char inqdata[36];
  1389. char *buffer;
  1390. struct scatterlist *sg;
  1391. if (cmd->device->lun) {
  1392. cmd->result = (DID_TIME_OUT << 16);
  1393. cmd->scsi_done(cmd);
  1394. return;
  1395. }
  1396. inqdata[0] = TYPE_PROCESSOR;
  1397. /* Periph Qualifier & Periph Dev Type */
  1398. inqdata[1] = 0;
  1399. /* rem media bit & Dev Type Modifier */
  1400. inqdata[2] = 0;
  1401. /* ISO, ECMA, & ANSI versions */
  1402. inqdata[4] = 31;
  1403. /* length of additional data */
  1404. strncpy(&inqdata[8], "Areca ", 8);
  1405. /* Vendor Identification */
  1406. strncpy(&inqdata[16], "RAID controller ", 16);
  1407. /* Product Identification */
  1408. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  1409. sg = scsi_sglist(cmd);
  1410. buffer = kmap_atomic(sg->page, KM_IRQ0) + sg->offset;
  1411. memcpy(buffer, inqdata, sizeof(inqdata));
  1412. sg = scsi_sglist(cmd);
  1413. kunmap_atomic(buffer - sg->offset, KM_IRQ0);
  1414. cmd->scsi_done(cmd);
  1415. }
  1416. break;
  1417. case WRITE_BUFFER:
  1418. case READ_BUFFER: {
  1419. if (arcmsr_iop_message_xfer(acb, cmd))
  1420. cmd->result = (DID_ERROR << 16);
  1421. cmd->scsi_done(cmd);
  1422. }
  1423. break;
  1424. default:
  1425. cmd->scsi_done(cmd);
  1426. }
  1427. }
  1428. static int arcmsr_queue_command(struct scsi_cmnd *cmd,
  1429. void (* done)(struct scsi_cmnd *))
  1430. {
  1431. struct Scsi_Host *host = cmd->device->host;
  1432. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  1433. struct CommandControlBlock *ccb;
  1434. int target = cmd->device->id;
  1435. int lun = cmd->device->lun;
  1436. cmd->scsi_done = done;
  1437. cmd->host_scribble = NULL;
  1438. cmd->result = 0;
  1439. if (acb->acb_flags & ACB_F_BUS_RESET) {
  1440. printk(KERN_NOTICE "arcmsr%d: bus reset"
  1441. " and return busy \n"
  1442. , acb->host->host_no);
  1443. return SCSI_MLQUEUE_HOST_BUSY;
  1444. }
  1445. if (target == 16) {
  1446. /* virtual device for iop message transfer */
  1447. arcmsr_handle_virtual_command(acb, cmd);
  1448. return 0;
  1449. }
  1450. if (acb->devstate[target][lun] == ARECA_RAID_GONE) {
  1451. uint8_t block_cmd;
  1452. block_cmd = cmd->cmnd[0] & 0x0f;
  1453. if (block_cmd == 0x08 || block_cmd == 0x0a) {
  1454. printk(KERN_NOTICE
  1455. "arcmsr%d: block 'read/write'"
  1456. "command with gone raid volume"
  1457. " Cmd = %2x, TargetId = %d, Lun = %d \n"
  1458. , acb->host->host_no
  1459. , cmd->cmnd[0]
  1460. , target, lun);
  1461. cmd->result = (DID_NO_CONNECT << 16);
  1462. cmd->scsi_done(cmd);
  1463. return 0;
  1464. }
  1465. }
  1466. if (atomic_read(&acb->ccboutstandingcount) >=
  1467. ARCMSR_MAX_OUTSTANDING_CMD)
  1468. return SCSI_MLQUEUE_HOST_BUSY;
  1469. ccb = arcmsr_get_freeccb(acb);
  1470. if (!ccb)
  1471. return SCSI_MLQUEUE_HOST_BUSY;
  1472. arcmsr_build_ccb(acb, ccb, cmd);
  1473. arcmsr_post_ccb(acb, ccb);
  1474. return 0;
  1475. }
  1476. static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
  1477. {
  1478. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  1479. char *acb_firm_model = acb->firm_model;
  1480. char *acb_firm_version = acb->firm_version;
  1481. char *iop_firm_model = (char *) (&reg->message_rwbuffer[15]);
  1482. char *iop_firm_version = (char *) (&reg->message_rwbuffer[17]);
  1483. int count;
  1484. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  1485. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1486. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1487. miscellaneous data' timeout \n", acb->host->host_no);
  1488. }
  1489. count = 8;
  1490. while (count) {
  1491. *acb_firm_model = readb(iop_firm_model);
  1492. acb_firm_model++;
  1493. iop_firm_model++;
  1494. count--;
  1495. }
  1496. count = 16;
  1497. while (count) {
  1498. *acb_firm_version = readb(iop_firm_version);
  1499. acb_firm_version++;
  1500. iop_firm_version++;
  1501. count--;
  1502. }
  1503. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n"
  1504. , acb->host->host_no
  1505. , acb->firm_version);
  1506. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  1507. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  1508. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  1509. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  1510. }
  1511. static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
  1512. {
  1513. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1514. uint32_t *lrwbuffer = reg->msgcode_rwbuffer_reg;
  1515. char *acb_firm_model = acb->firm_model;
  1516. char *acb_firm_version = acb->firm_version;
  1517. char *iop_firm_model = (char *) (&lrwbuffer[15]);
  1518. /*firm_model,15,60-67*/
  1519. char *iop_firm_version = (char *) (&lrwbuffer[17]);
  1520. /*firm_version,17,68-83*/
  1521. int count;
  1522. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell_reg);
  1523. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1524. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  1525. miscellaneous data' timeout \n", acb->host->host_no);
  1526. }
  1527. count = 8;
  1528. while (count)
  1529. {
  1530. *acb_firm_model = readb(iop_firm_model);
  1531. acb_firm_model++;
  1532. iop_firm_model++;
  1533. count--;
  1534. }
  1535. count = 16;
  1536. while (count)
  1537. {
  1538. *acb_firm_version = readb(iop_firm_version);
  1539. acb_firm_version++;
  1540. iop_firm_version++;
  1541. count--;
  1542. }
  1543. printk(KERN_INFO "ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n",
  1544. acb->host->host_no,
  1545. acb->firm_version);
  1546. lrwbuffer++;
  1547. acb->firm_request_len = readl(lrwbuffer++);
  1548. /*firm_request_len,1,04-07*/
  1549. acb->firm_numbers_queue = readl(lrwbuffer++);
  1550. /*firm_numbers_queue,2,08-11*/
  1551. acb->firm_sdram_size = readl(lrwbuffer++);
  1552. /*firm_sdram_size,3,12-15*/
  1553. acb->firm_hd_channels = readl(lrwbuffer);
  1554. /*firm_ide_channels,4,16-19*/
  1555. }
  1556. static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  1557. {
  1558. switch (acb->adapter_type) {
  1559. case ACB_ADAPTER_TYPE_A: {
  1560. arcmsr_get_hba_config(acb);
  1561. }
  1562. break;
  1563. case ACB_ADAPTER_TYPE_B: {
  1564. arcmsr_get_hbb_config(acb);
  1565. }
  1566. break;
  1567. }
  1568. }
  1569. static void arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
  1570. struct CommandControlBlock *poll_ccb)
  1571. {
  1572. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  1573. struct CommandControlBlock *ccb;
  1574. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  1575. polling_hba_ccb_retry:
  1576. poll_count++;
  1577. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  1578. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1579. while (1) {
  1580. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  1581. if (poll_ccb_done)
  1582. break;
  1583. else {
  1584. msleep(25);
  1585. if (poll_count > 100)
  1586. break;
  1587. goto polling_hba_ccb_retry;
  1588. }
  1589. }
  1590. ccb = (struct CommandControlBlock *)(acb->vir2phy_offset + (flag_ccb << 5));
  1591. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1592. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1593. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  1594. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  1595. " poll command abort successfully \n"
  1596. , acb->host->host_no
  1597. , ccb->pcmd->device->id
  1598. , ccb->pcmd->device->lun
  1599. , ccb);
  1600. ccb->pcmd->result = DID_ABORT << 16;
  1601. arcmsr_ccb_complete(ccb, 1);
  1602. poll_ccb_done = 1;
  1603. continue;
  1604. }
  1605. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1606. " command done ccb = '0x%p'"
  1607. "ccboutstandingcount = %d \n"
  1608. , acb->host->host_no
  1609. , ccb
  1610. , atomic_read(&acb->ccboutstandingcount));
  1611. continue;
  1612. }
  1613. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1614. }
  1615. }
  1616. static void arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb, \
  1617. struct CommandControlBlock *poll_ccb)
  1618. {
  1619. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1620. struct CommandControlBlock *ccb;
  1621. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  1622. int index;
  1623. polling_hbb_ccb_retry:
  1624. poll_count++;
  1625. /* clear doorbell interrupt */
  1626. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1627. while (1) {
  1628. index = reg->doneq_index;
  1629. if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
  1630. if (poll_ccb_done)
  1631. break;
  1632. else {
  1633. msleep(25);
  1634. if (poll_count > 100)
  1635. break;
  1636. goto polling_hbb_ccb_retry;
  1637. }
  1638. }
  1639. writel(0, &reg->done_qbuffer[index]);
  1640. index++;
  1641. /*if last index number set it to 0 */
  1642. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1643. reg->doneq_index = index;
  1644. /* check ifcommand done with no error*/
  1645. ccb = (struct CommandControlBlock *)\
  1646. (acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1647. poll_ccb_done = (ccb == poll_ccb) ? 1:0;
  1648. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  1649. if (ccb->startdone == ARCMSR_CCB_ABORTED) {
  1650. printk(KERN_NOTICE "arcmsr%d: \
  1651. scsi id = %d lun = %d ccb = '0x%p' poll command abort successfully \n"
  1652. ,acb->host->host_no
  1653. ,ccb->pcmd->device->id
  1654. ,ccb->pcmd->device->lun
  1655. ,ccb);
  1656. ccb->pcmd->result = DID_ABORT << 16;
  1657. arcmsr_ccb_complete(ccb, 1);
  1658. continue;
  1659. }
  1660. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  1661. " command done ccb = '0x%p'"
  1662. "ccboutstandingcount = %d \n"
  1663. , acb->host->host_no
  1664. , ccb
  1665. , atomic_read(&acb->ccboutstandingcount));
  1666. continue;
  1667. }
  1668. arcmsr_report_ccb_state(acb, ccb, flag_ccb);
  1669. } /*drain reply FIFO*/
  1670. }
  1671. static void arcmsr_polling_ccbdone(struct AdapterControlBlock *acb, \
  1672. struct CommandControlBlock *poll_ccb)
  1673. {
  1674. switch (acb->adapter_type) {
  1675. case ACB_ADAPTER_TYPE_A: {
  1676. arcmsr_polling_hba_ccbdone(acb,poll_ccb);
  1677. }
  1678. break;
  1679. case ACB_ADAPTER_TYPE_B: {
  1680. arcmsr_polling_hbb_ccbdone(acb,poll_ccb);
  1681. }
  1682. }
  1683. }
  1684. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  1685. {
  1686. uint32_t cdb_phyaddr, ccb_phyaddr_hi32;
  1687. dma_addr_t dma_coherent_handle;
  1688. /*
  1689. ********************************************************************
  1690. ** here we need to tell iop 331 our freeccb.HighPart
  1691. ** if freeccb.HighPart is not zero
  1692. ********************************************************************
  1693. */
  1694. dma_coherent_handle = acb->dma_coherent_handle;
  1695. cdb_phyaddr = (uint32_t)(dma_coherent_handle);
  1696. ccb_phyaddr_hi32 = (uint32_t)((cdb_phyaddr >> 16) >> 16);
  1697. /*
  1698. ***********************************************************************
  1699. ** if adapter type B, set window of "post command Q"
  1700. ***********************************************************************
  1701. */
  1702. switch (acb->adapter_type) {
  1703. case ACB_ADAPTER_TYPE_A: {
  1704. if (ccb_phyaddr_hi32 != 0) {
  1705. struct MessageUnit_A __iomem *reg = \
  1706. (struct MessageUnit_A *)acb->pmu;
  1707. uint32_t intmask_org;
  1708. intmask_org = arcmsr_disable_outbound_ints(acb);
  1709. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  1710. &reg->message_rwbuffer[0]);
  1711. writel(ccb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  1712. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  1713. &reg->inbound_msgaddr0);
  1714. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1715. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  1716. part physical address timeout\n",
  1717. acb->host->host_no);
  1718. return 1;
  1719. }
  1720. arcmsr_enable_outbound_ints(acb, intmask_org);
  1721. }
  1722. }
  1723. break;
  1724. case ACB_ADAPTER_TYPE_B: {
  1725. unsigned long post_queue_phyaddr;
  1726. uint32_t *rwbuffer;
  1727. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1728. uint32_t intmask_org;
  1729. intmask_org = arcmsr_disable_outbound_ints(acb);
  1730. reg->postq_index = 0;
  1731. reg->doneq_index = 0;
  1732. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell_reg);
  1733. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1734. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  1735. acb->host->host_no);
  1736. return 1;
  1737. }
  1738. post_queue_phyaddr = cdb_phyaddr + ARCMSR_MAX_FREECCB_NUM * \
  1739. sizeof(struct CommandControlBlock) + offsetof(struct MessageUnit_B, post_qbuffer) ;
  1740. rwbuffer = reg->msgcode_rwbuffer_reg;
  1741. /* driver "set config" signature */
  1742. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  1743. /* normal should be zero */
  1744. writel(ccb_phyaddr_hi32, rwbuffer++);
  1745. /* postQ size (256 + 8)*4 */
  1746. writel(post_queue_phyaddr, rwbuffer++);
  1747. /* doneQ size (256 + 8)*4 */
  1748. writel(post_queue_phyaddr + 1056, rwbuffer++);
  1749. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  1750. writel(1056, rwbuffer);
  1751. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell_reg);
  1752. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1753. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  1754. timeout \n",acb->host->host_no);
  1755. return 1;
  1756. }
  1757. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell_reg);
  1758. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1759. printk(KERN_NOTICE "arcmsr%d: 'can not set diver mode \n"\
  1760. ,acb->host->host_no);
  1761. return 1;
  1762. }
  1763. arcmsr_enable_outbound_ints(acb, intmask_org);
  1764. }
  1765. break;
  1766. }
  1767. return 0;
  1768. }
  1769. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  1770. {
  1771. uint32_t firmware_state = 0;
  1772. switch (acb->adapter_type) {
  1773. case ACB_ADAPTER_TYPE_A: {
  1774. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  1775. do {
  1776. firmware_state = readl(&reg->outbound_msgaddr1);
  1777. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  1778. }
  1779. break;
  1780. case ACB_ADAPTER_TYPE_B: {
  1781. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1782. do {
  1783. firmware_state = readl(reg->iop2drv_doorbell_reg);
  1784. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  1785. }
  1786. break;
  1787. }
  1788. }
  1789. static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
  1790. {
  1791. struct MessageUnit_A __iomem *reg = (struct MessageUnit_A *)acb->pmu;
  1792. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1793. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  1794. if (arcmsr_hba_wait_msgint_ready(acb)) {
  1795. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1796. rebulid' timeout \n", acb->host->host_no);
  1797. }
  1798. }
  1799. static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
  1800. {
  1801. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1802. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  1803. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell_reg);
  1804. if (arcmsr_hbb_wait_msgint_ready(acb)) {
  1805. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  1806. rebulid' timeout \n",acb->host->host_no);
  1807. }
  1808. }
  1809. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  1810. {
  1811. switch (acb->adapter_type) {
  1812. case ACB_ADAPTER_TYPE_A:
  1813. arcmsr_start_hba_bgrb(acb);
  1814. break;
  1815. case ACB_ADAPTER_TYPE_B:
  1816. arcmsr_start_hbb_bgrb(acb);
  1817. break;
  1818. }
  1819. }
  1820. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  1821. {
  1822. switch (acb->adapter_type) {
  1823. case ACB_ADAPTER_TYPE_A: {
  1824. struct MessageUnit_A *reg = (struct MessageUnit_A *)acb->pmu;
  1825. uint32_t outbound_doorbell;
  1826. /* empty doorbell Qbuffer if door bell ringed */
  1827. outbound_doorbell = readl(&reg->outbound_doorbell);
  1828. /*clear doorbell interrupt */
  1829. writel(outbound_doorbell, &reg->outbound_doorbell);
  1830. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1831. }
  1832. break;
  1833. case ACB_ADAPTER_TYPE_B: {
  1834. struct MessageUnit_B *reg = (struct MessageUnit_B *)acb->pmu;
  1835. /*clear interrupt and message state*/
  1836. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell_reg);
  1837. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell_reg);
  1838. /* let IOP know data has been read */
  1839. }
  1840. break;
  1841. }
  1842. }
  1843. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  1844. {
  1845. uint32_t intmask_org;
  1846. arcmsr_wait_firmware_ready(acb);
  1847. arcmsr_iop_confirm(acb);
  1848. /* disable all outbound interrupt */
  1849. intmask_org = arcmsr_disable_outbound_ints(acb);
  1850. arcmsr_get_firmware_spec(acb);
  1851. /*start background rebuild*/
  1852. arcmsr_start_adapter_bgrb(acb);
  1853. /* empty doorbell Qbuffer if door bell ringed */
  1854. arcmsr_clear_doorbell_queue_buffer(acb);
  1855. /* enable outbound Post Queue,outbound doorbell Interrupt */
  1856. arcmsr_enable_outbound_ints(acb, intmask_org);
  1857. acb->acb_flags |= ACB_F_IOP_INITED;
  1858. }
  1859. static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
  1860. {
  1861. struct CommandControlBlock *ccb;
  1862. uint32_t intmask_org;
  1863. int i = 0;
  1864. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  1865. /* talk to iop 331 outstanding command aborted */
  1866. arcmsr_abort_allcmd(acb);
  1867. /* wait for 3 sec for all command aborted*/
  1868. ssleep(3);
  1869. /* disable all outbound interrupt */
  1870. intmask_org = arcmsr_disable_outbound_ints(acb);
  1871. /* clear all outbound posted Q */
  1872. arcmsr_done4abort_postqueue(acb);
  1873. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1874. ccb = acb->pccb_pool[i];
  1875. if (ccb->startdone == ARCMSR_CCB_START) {
  1876. ccb->startdone = ARCMSR_CCB_ABORTED;
  1877. arcmsr_ccb_complete(ccb, 1);
  1878. }
  1879. }
  1880. /* enable all outbound interrupt */
  1881. arcmsr_enable_outbound_ints(acb, intmask_org);
  1882. }
  1883. }
  1884. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  1885. {
  1886. struct AdapterControlBlock *acb =
  1887. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1888. int i;
  1889. acb->num_resets++;
  1890. acb->acb_flags |= ACB_F_BUS_RESET;
  1891. for (i = 0; i < 400; i++) {
  1892. if (!atomic_read(&acb->ccboutstandingcount))
  1893. break;
  1894. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1895. msleep(25);
  1896. }
  1897. arcmsr_iop_reset(acb);
  1898. acb->acb_flags &= ~ACB_F_BUS_RESET;
  1899. return SUCCESS;
  1900. }
  1901. static void arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  1902. struct CommandControlBlock *ccb)
  1903. {
  1904. u32 intmask;
  1905. ccb->startdone = ARCMSR_CCB_ABORTED;
  1906. /*
  1907. ** Wait for 3 sec for all command done.
  1908. */
  1909. ssleep(3);
  1910. intmask = arcmsr_disable_outbound_ints(acb);
  1911. arcmsr_polling_ccbdone(acb, ccb);
  1912. arcmsr_enable_outbound_ints(acb, intmask);
  1913. }
  1914. static int arcmsr_abort(struct scsi_cmnd *cmd)
  1915. {
  1916. struct AdapterControlBlock *acb =
  1917. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  1918. int i = 0;
  1919. printk(KERN_NOTICE
  1920. "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
  1921. acb->host->host_no, cmd->device->id, cmd->device->lun);
  1922. acb->num_aborts++;
  1923. /*
  1924. ************************************************
  1925. ** the all interrupt service routine is locked
  1926. ** we need to handle it as soon as possible and exit
  1927. ************************************************
  1928. */
  1929. if (!atomic_read(&acb->ccboutstandingcount))
  1930. return SUCCESS;
  1931. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1932. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1933. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  1934. arcmsr_abort_one_cmd(acb, ccb);
  1935. break;
  1936. }
  1937. }
  1938. return SUCCESS;
  1939. }
  1940. static const char *arcmsr_info(struct Scsi_Host *host)
  1941. {
  1942. struct AdapterControlBlock *acb =
  1943. (struct AdapterControlBlock *) host->hostdata;
  1944. static char buf[256];
  1945. char *type;
  1946. int raid6 = 1;
  1947. switch (acb->pdev->device) {
  1948. case PCI_DEVICE_ID_ARECA_1110:
  1949. case PCI_DEVICE_ID_ARECA_1200:
  1950. case PCI_DEVICE_ID_ARECA_1202:
  1951. case PCI_DEVICE_ID_ARECA_1210:
  1952. raid6 = 0;
  1953. /*FALLTHRU*/
  1954. case PCI_DEVICE_ID_ARECA_1120:
  1955. case PCI_DEVICE_ID_ARECA_1130:
  1956. case PCI_DEVICE_ID_ARECA_1160:
  1957. case PCI_DEVICE_ID_ARECA_1170:
  1958. case PCI_DEVICE_ID_ARECA_1201:
  1959. case PCI_DEVICE_ID_ARECA_1220:
  1960. case PCI_DEVICE_ID_ARECA_1230:
  1961. case PCI_DEVICE_ID_ARECA_1260:
  1962. case PCI_DEVICE_ID_ARECA_1270:
  1963. case PCI_DEVICE_ID_ARECA_1280:
  1964. type = "SATA";
  1965. break;
  1966. case PCI_DEVICE_ID_ARECA_1380:
  1967. case PCI_DEVICE_ID_ARECA_1381:
  1968. case PCI_DEVICE_ID_ARECA_1680:
  1969. case PCI_DEVICE_ID_ARECA_1681:
  1970. type = "SAS";
  1971. break;
  1972. default:
  1973. type = "X-TYPE";
  1974. break;
  1975. }
  1976. sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
  1977. type, raid6 ? "( RAID6 capable)" : "",
  1978. ARCMSR_DRIVER_VERSION);
  1979. return buf;
  1980. }
  1981. #ifdef CONFIG_SCSI_ARCMSR_AER
  1982. static pci_ers_result_t arcmsr_pci_slot_reset(struct pci_dev *pdev)
  1983. {
  1984. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1985. struct AdapterControlBlock *acb =
  1986. (struct AdapterControlBlock *) host->hostdata;
  1987. uint32_t intmask_org;
  1988. int i, j;
  1989. if (pci_enable_device(pdev)) {
  1990. return PCI_ERS_RESULT_DISCONNECT;
  1991. }
  1992. pci_set_master(pdev);
  1993. intmask_org = arcmsr_disable_outbound_ints(acb);
  1994. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  1995. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  1996. ACB_F_MESSAGE_WQBUFFER_READED);
  1997. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  1998. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  1999. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  2000. acb->devstate[i][j] = ARECA_RAID_GONE;
  2001. arcmsr_wait_firmware_ready(acb);
  2002. arcmsr_iop_confirm(acb);
  2003. /* disable all outbound interrupt */
  2004. arcmsr_get_firmware_spec(acb);
  2005. /*start background rebuild*/
  2006. arcmsr_start_adapter_bgrb(acb);
  2007. /* empty doorbell Qbuffer if door bell ringed */
  2008. arcmsr_clear_doorbell_queue_buffer(acb);
  2009. /* enable outbound Post Queue,outbound doorbell Interrupt */
  2010. arcmsr_enable_outbound_ints(acb, intmask_org);
  2011. acb->acb_flags |= ACB_F_IOP_INITED;
  2012. pci_enable_pcie_error_reporting(pdev);
  2013. return PCI_ERS_RESULT_RECOVERED;
  2014. }
  2015. static void arcmsr_pci_ers_need_reset_forepart(struct pci_dev *pdev)
  2016. {
  2017. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2018. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)host->hostdata;
  2019. struct CommandControlBlock *ccb;
  2020. uint32_t intmask_org;
  2021. int i = 0;
  2022. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  2023. /* talk to iop 331 outstanding command aborted */
  2024. arcmsr_abort_allcmd(acb);
  2025. /* wait for 3 sec for all command aborted*/
  2026. ssleep(3);
  2027. /* disable all outbound interrupt */
  2028. intmask_org = arcmsr_disable_outbound_ints(acb);
  2029. /* clear all outbound posted Q */
  2030. arcmsr_done4abort_postqueue(acb);
  2031. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  2032. ccb = acb->pccb_pool[i];
  2033. if (ccb->startdone == ARCMSR_CCB_START) {
  2034. ccb->startdone = ARCMSR_CCB_ABORTED;
  2035. arcmsr_ccb_complete(ccb, 1);
  2036. }
  2037. }
  2038. /* enable all outbound interrupt */
  2039. arcmsr_enable_outbound_ints(acb, intmask_org);
  2040. }
  2041. pci_disable_device(pdev);
  2042. }
  2043. static void arcmsr_pci_ers_disconnect_forepart(struct pci_dev *pdev)
  2044. {
  2045. struct Scsi_Host *host = pci_get_drvdata(pdev);
  2046. struct AdapterControlBlock *acb = \
  2047. (struct AdapterControlBlock *)host->hostdata;
  2048. arcmsr_stop_adapter_bgrb(acb);
  2049. arcmsr_flush_adapter_cache(acb);
  2050. }
  2051. static pci_ers_result_t arcmsr_pci_error_detected(struct pci_dev *pdev,
  2052. pci_channel_state_t state)
  2053. {
  2054. switch (state) {
  2055. case pci_channel_io_frozen:
  2056. arcmsr_pci_ers_need_reset_forepart(pdev);
  2057. return PCI_ERS_RESULT_NEED_RESET;
  2058. case pci_channel_io_perm_failure:
  2059. arcmsr_pci_ers_disconnect_forepart(pdev);
  2060. return PCI_ERS_RESULT_DISCONNECT;
  2061. break;
  2062. default:
  2063. return PCI_ERS_RESULT_NEED_RESET;
  2064. }
  2065. }
  2066. #endif